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1. 发明授权

US5366906A Wafer level integration and testing 失效
标题翻译：晶圆级集成和测试
公开(公告)号：US5366906A
公开(公告)日：1994-11-22
申请号：US962000
申请日：1992-10-16
申请人： Robert J. Wojnarowski , Constantine A. Neugebauer , Wolfgang Daum , Bernard Gorowitz , Eric J. Wildi , Michael Gdula , Stanton E. Weaver, Jr. , Anthony A. Immorlica, Jr.
发明人： Robert J. Wojnarowski , Constantine A. Neugebauer , Wolfgang Daum , Bernard Gorowitz , Eric J. Wildi , Michael Gdula , Stanton E. Weaver, Jr. , Anthony A. Immorlica, Jr.
IPC分类号： G01R31/3185 , H01L21/301 , H01L21/66 , H01L23/538 , H01L23/58 , G01R31/26
CPC分类号： H01L22/22 , H01L22/32 , H01L23/5389 , H01L24/24 , H01L24/82 , G01R31/318505 , G01R31/318533 , H01L2224/2402 , H01L2224/24137 , H01L2224/24227 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2924/3011 , H01L2924/351
摘要： In fabricating wafer scale integrated interconnects, a temporary or permanent dielectric layer and a pattern of electrical conductors are used to provide wafer scale integration or testing and burn-in. A resist can be used to cover the areas of IC pads on the wafer while the remainder of the pattern of electrical conductors is removed to provide for repair of the wafer scale integration structure. The pattern of electrical conductors may be configured so that the conductor lengths between at least some sub-circuits on a plurality of wafers are substantially electrically equal for signal propagation purposes; an additional wafer may be laminated to the wafer using an adhesive; controlled curfs may be cut into the wafer; and the wafer may be interconnected to an interface ring.
摘要翻译：在制造晶片级集成互连件时，使用临时或永久的电介质层和电导体图案来提供晶片级整合或测试和老化。可以使用抗蚀剂来覆盖晶片上的IC焊盘的区域，而去除电导体图案的其余部分以提供晶片级整合结构的修复。电导体的图案可以被配置为使得在多个晶片上的至少一些子电路之间的导体长度对于信号传播目的而基本上是电相等的; 可以使用粘合剂将另外的晶片层压到晶片上; 受控的曲折可以被切入晶片; 并且晶片可以互连到接口环。

2. 发明授权

US5279706A Method and apparatus for fabricating a metal interconnection pattern for an integrated circuit module 失效
标题翻译：用于制造用于集成电路模块的金属互连图案的方法和装置
公开(公告)号：US5279706A
公开(公告)日：1994-01-18
申请号：US959883
申请日：1992-10-13
申请人： Ernest W. Balch , Stanton E. Weaver, Jr. , William H. King , Bernard Gorowitz
发明人： Ernest W. Balch , Stanton E. Weaver, Jr. , William H. King , Bernard Gorowitz
IPC分类号： H01L21/60 , H01L21/48 , H01L23/12 , H01L23/498 , H05K3/00 , H05K3/06 , H05K3/34 , H05K3/40 , B44C1/22 , C23F1/00
CPC分类号： H05K3/403 , H01L21/4846 , H01L23/49805 , H01L24/82 , H01L2224/48225 , H01L2224/48227 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H05K2203/135 , H05K3/0082 , H05K3/064 , H05K3/3442
摘要： A method for fabricating a metal interconnection pattern for an integrated circuit module is provided comprising the steps of: aligning only one face of the module, forming a metal layer on at least one other face of the module, applying a coating of photoresist to the metal layer, exposing predetermined portions of the photoresist to reflected radiation, and shaping the metal layer in accordance with the exposed photoresist portions.
摘要翻译：提供了一种用于制造用于集成电路模块的金属互连图案的方法，包括以下步骤：仅对准模块的一个面，在模块的至少另一个表面上形成金属层，向金属施加光致抗蚀剂涂层将光致抗蚀剂的预定部分暴露于反射辐射，以及根据曝光的光致抗蚀剂部分对金属层成形。

3. 发明授权

US5391516A Method for enhancement of semiconductor device contact pads 失效
标题翻译：用于增强半导体器件接触焊盘的方法
公开(公告)号：US5391516A
公开(公告)日：1995-02-21
申请号：US774427
申请日：1991-10-10
申请人： Robert J. Wojnarowski , Bernard Gorowitz
发明人： Robert J. Wojnarowski , Bernard Gorowitz
IPC分类号： H01L21/768 , H01L21/268 , H01L21/311 , H01L21/441
CPC分类号： H01L21/76877 , H01L24/05 , H01L2924/12042 , H01L2924/14
摘要： Semiconductor device contact pads are enhanced by forming a metal plate over at least a portion of the contact pad. "Enhancement" includes repair such as by bridging a reinforcing pad area over probe damage, general reinforcement or enlargement of a contact pad, and placement of a protective buffer pad over a contact pad. These methods are applicable to any semiconductor device with contact pads on a surface thereof, such as entire wafers, individual dice, and multi-chip High Density Interconnect (HDI) modules. The pad enhancement plate is formed by applying a planarizing dielectric layer over the entire device (if not already formed in the initial stages of HDI processing), and an enhancement access via is then formed to expose a portion of the contact pad to be enhanced. The entire device is metallized, and metal not over the exposed portion of the contact pad is subsequently removed. Localized heating of the metal plate can be achieved by a laser to effectuate a selective pseudo-weld or produce sintering for a low resistance ohmic contact.
摘要翻译：通过在接触垫的至少一部分上形成金属板来增强半导体器件接触焊盘。 “增强”包括修复，例如通过桥接加强垫区域超过探测器损伤，通常加强或扩大接触垫，以及将保护性缓冲垫放置在接触垫上。这些方法适用于具有其表面上的接触焊盘的任何半导体器件，例如整个晶片，单个晶片和多芯片高密度互连（HDI）模块。通过在整个装置（如果在HDI处理的初始阶段尚未形成）中施加平坦化介电层来形成焊盘增强板，然后形成增强接入通路，以使接触焊盘的一部分暴露出增强。整个装置被金属化，并且随后去除接触垫的暴露部分之上的金属。可以通过激光来实现金属板的局部加热，以实现选择性伪焊接或产生用于低电阻欧姆接触的烧结。

4. 发明授权

US5527741A Fabrication and structures of circuit modules with flexible interconnect layers 失效
标题翻译：具有柔性互连层的电路模块的制造和结构
公开(公告)号：US5527741A
公开(公告)日：1996-06-18
申请号：US321346
申请日：1994-10-11
申请人： Herbert S. Cole , Raymond A. Fillion , Bernard Gorowitz , Ronald F. Kolc , Robert J. Wojnarowski
发明人： Herbert S. Cole , Raymond A. Fillion , Bernard Gorowitz , Ronald F. Kolc , Robert J. Wojnarowski
IPC分类号： H01L21/60 , H01L21/48 , H01L23/538 , H05K3/32
CPC分类号： H05K3/32 , H01L21/4857 , H01L23/5383 , H01L23/5387 , H01L24/24 , H01L24/82 , H01L2224/04105 , H01L2224/24137 , H01L2224/32225 , H01L2224/73267 , H01L2224/82047 , H01L2224/92144 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01025 , H01L2924/01027 , H01L2924/01029 , H01L2924/01078 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , Y10T29/4913
摘要： A method for fabricating a circuit module includes applying an outer insulative layer over a first patterned metallization layer on a first surface of a base insulative layer. A second surface of the base insulative layer has a second patterned metallization layer. At least one circuit chip having chip pads is attached to the second surface of the base insulative layer. Respective vias are formed to expose selected portions of the first patterned metallization layer, the second patterned metallization layer, and the chip pads. A patterned outer metallization layer is applied over the outer insulative layer to extend through selected ones of the vias to interconnect selected ones of the chip pads and selected portions of the first and second metallization layers.
摘要翻译：一种用于制造电路模块的方法包括在绝缘层的第一表面上的第一图案化金属化层上施加外部绝缘层。基极绝缘层的第二表面具有第二图案化金属化层。具有芯片焊盘的至少一个电路芯片附接到基极绝缘层的第二表面。形成各个通孔以暴露第一图案化金属化层，第二图案化金属化层和芯片焊盘的选定部分。图案化的外部金属化层被施加在外部绝缘层上以延伸通过选定的通孔以互连所选择的芯片焊盘和第一和第二金属化层的选定部分。

5. 发明授权

US06298551B1 Methods of forming compliant interface structures with partially open interiors for coupling two electrically conductive contact areas 有权
标题翻译：形成具有部分开放内部的柔性界面结构以耦合两个导电接触区域的方法
公开(公告)号：US06298551B1
公开(公告)日：2001-10-09
申请号：US09459586
申请日：1999-12-13
申请人： Robert John Wojnarowski , Barry Scott Whitmore , Bernard Gorowitz
发明人： Robert John Wojnarowski , Barry Scott Whitmore , Bernard Gorowitz
IPC分类号： H05K336
CPC分类号： H01L24/02 , H01L21/4853 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L2224/0401 , H01L2224/16 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2924/3511 , H05K3/326 , H05K3/3436 , H05K3/4092 , H05K2201/0373 , H05K2201/10257 , H05K2201/10378 , Y02P70/613 , Y10S438/94 , Y10T29/49124 , Y10T29/49126 , Y10T29/4913 , H01L2924/00
摘要： An interface includes a surface having an electrically conductive pad; a compliant coating over the surface having a via extending to the pad; metallization patterned over the compliant coating and extending into the via; a low modulus dielectric interface layer overlying the compliant coating and having an interface via extending to the metallization; and a floating pad structure including floating pad metallization patterned over the dielectric interface layer with a first portion forming a central pad and a second portion forming an extension from the central pad extending into the interface via. Another interface includes a substrate including a low modulus dielectric interface material having a hole extending at least partially therethrough and a floating contact structure including electrically conductive material coating the hole with at least some of the floating pad metallization forming an extension from the hole. A conductive contact area interface may include an electrically conductive first contact area; an electrically conductive second contact area facing and being substantially aligned with the first contact area; and at least one interface structure coupled between the first and second contact areas and including an electrical conductor having a partially open interior to form a compliant joint between the first and second contact areas.
摘要翻译：界面包括具有导电垫的表面; 表面上的柔顺涂层具有延伸到垫的通孔; 金属化图案化在柔性涂层上并延伸到通孔中; 覆盖顺应性涂层并具有延伸到金属化的界面的低模量介电界面层; 以及浮动衬垫结构，其包括在电介质界面层上图案化的浮动衬垫金属化，第一部分形成中心焊盘，第二部分形成从延伸到接口通孔的中心焊盘的延伸部分。另一个界面包括一个衬底，该衬底包括一个具有至少部分贯穿其中延伸的孔的低模量介电界面材料，以及一个浮动接触结构，其包括导电材料，该导电材料涂覆孔，浮动金属化中的至少一些从孔形成延伸。导电接触区界面可以包括导电的第一接触区域; 面向并基本上与第一接触区域对准的导电的第二接触区域; 以及耦合在所述第一和第二接触区域之间的至少一个接口结构，并且包括具有部分敞开的内部的电导体，以在所述第一和第二接触区域之间形成柔性接头。

6. 发明授权

US5657537A Method for fabricating a stack of two dimensional circuit modules 失效
标题翻译：制造二维电路模块的方法
公开(公告)号：US5657537A
公开(公告)日：1997-08-19
申请号：US453109
申请日：1995-05-30
申请人： Richard Joseph Saia , Bernard Gorowitz , Kevin Matthew Durocher
发明人： Richard Joseph Saia , Bernard Gorowitz , Kevin Matthew Durocher
IPC分类号： H01L21/98 , H01L23/538 , H01L25/065 , H05K1/03 , H05K1/14 , H05K3/40 , H05K3/46 , H05K3/36
CPC分类号： H01L25/50 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L25/0652 , H05K1/144 , H05K3/403 , H01L2224/24225 , H01L2224/24227 , H01L2224/2919 , H01L2224/8384 , H01L2225/06513 , H01L2225/06551 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H05K1/0306 , H05K2201/09581 , H05K3/4611 , H05K3/4629 , H05K3/4685 , Y10T29/49126
摘要： A method for fabricating a stack of circuit modules includes providing a plurality of substrates having module interconnection layers. Each of the substrates has a circuit chip with chip pads positioned therein and an electrically conductive feed-through line extending from a first surface of the substrate to a second surface of the substrate with the first surface being perpendicular to the second surface. Each of the module interconnection layers is situated over a respective first surface of each of the substrates and includes a module dielectric layer having module vias therein and a module pattern of electrical conductors extending through the module vias to couple the selected chip pads to the feed-through line. The plurality of substrates are stacked. A side interconnection layer is applied over a side surface including the second surfaces of the substrates. The side interconnection layer includes a side dielectric layer having side vias therein aligned with predetermined ones of the feed-through lines and a side pattern of electrical conductors extending through the side vias.
摘要翻译：一种用于制造电路模块堆叠的方法包括提供具有模块互连层的多个基板。每个基板具有其中设置有芯片焊盘的电路芯片，以及导电的馈通线，其从基板的第一表面延伸到基板的第二表面，其中第一表面垂直于第二表面。每个模块互连层位于每个基板的相应的第一表面上，并且包括其中具有模块通孔的模块介电层和延伸穿过模块通孔的电导体的模块图案，以将所选择的芯片焊盘耦合到馈送 - 通过线。堆叠多个基板。侧面互连层被施加在包括基板的第二表面的侧表面上。侧面互连层包括侧面介电层，其侧面通孔与预定的馈通线对准，并且电导体的侧面图案延伸穿过侧面通孔。

7. 发明授权

US5857858A Demountable and repairable low pitch interconnect for stacked multichip modules 失效
标题翻译：用于堆叠多芯片模块的可拆卸和可修复的低间距互连
公开(公告)号：US5857858A
公开(公告)日：1999-01-12
申请号：US773625
申请日：1996-12-23
申请人： Bernard Gorowitz , Robert John Wojnarowski , Ronald Frank Kolc
发明人： Bernard Gorowitz , Robert John Wojnarowski , Ronald Frank Kolc
IPC分类号： H01L25/065 , H05K1/14 , H05K3/32 , H05K3/40 , H05K1/11
CPC分类号： H05K3/325 , H01L25/0652 , H05K1/144 , H01L2924/0002 , H01L2924/3011 , H05K3/403
摘要： Connection elements which, for example, may be used to facilitate interconnection to and stacking of electronic assemblies or may include an elongated conductive core, such as a wire or a hollow tube structure, coated with a layer of elastomeric material containing conductive particle such that the elastomeric material is conductive at least when compressed. The substrates of multi-chip modules (MCMs) have electrical connection sites in the form of metal-lined channels in the substrate edges, and the connection elements are pressed into the channels. Separate compression or clamping elements may be employed to enhance conductivity, as well as to facilitate external connections. The elongated conductive core may take the form of a hollow tube structure which may be expanded under internal pressure to compress the layer of elastomeric material. The compression elements may take the form of printed circuit boards. In alternative embodiments the connection elements may be clamped between conductive channels of side-by-side substrates or between opposed conductive channels of stacked substrates.
摘要翻译：连接元件例如可用于促进电子组件的互连和堆叠，或者可以包括细长导电芯，例如线或中空管结构，涂覆有包含导电颗粒的弹性体材料层，使得至少在压缩时弹性材料是导电的。多芯片模块（MCM）的基板在基板边缘中具有金属衬里通道形式的电连接位置，并且连接元件被压入通道中。可以使用单独的压缩或夹紧元件来增强导电性，并且便于外部连接。细长导电芯可以采取中空管结构的形式，其可以在内部压力下膨胀以压缩弹性体材料层。压缩元件可以采用印刷电路板的形式。在替代实施例中，连接元件可以被夹持在并排衬底的导电沟道之间或层叠衬底的相对的导电沟道之间。

8. 发明授权

US5757072A Structure for protecting air bridges on semiconductor chips from damage 失效
公开(公告)号：US5757072A
公开(公告)日：1998-05-26
申请号：US663506
申请日：1996-06-14
申请人： Bernard Gorowitz , Charles Adrian Becker , Renato Guida , Thomas Bert Gorczyca , James Wilson Rose
发明人： Bernard Gorowitz , Charles Adrian Becker , Renato Guida , Thomas Bert Gorczyca , James Wilson Rose
IPC分类号： H01L21/768 , H01L23/00 , H01L23/522 , H01L23/538 , H01L27/00 , B23K26/00 , H01L23/48 , H01L29/34 , H05K3/30
CPC分类号： H01L23/562 , H01L23/5221 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L2224/04105 , H01L2224/2402 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01049 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/1423 , H01L2924/15153 , H01L2924/15165 , H01L2924/15787 , H01L2924/3011 , H01L2924/3025
摘要： A protective cap is deposited over the top and sides of an air bridge structure located on an integrated circuit chip. The protective cap provides mechanical strength during the application of a high density interconnect structure over the chips, to prevent deformation of the sensitive (air bridge) structure, and also to prevent any contamination from intruding under the air bridge. More importantly, the protective cap does not impede the performance of the air bridge and therefore does not need to be removed, thereby eliminating the necessity of ablating the HDI structure. Furthermore, the protective cap allows additional area for metallization to provide alternate circuits for coupling, power or ground planes, etc.

9. 发明授权

US4845050A Method of making mo/tiw or w/tiw ohmic contacts to silicon 失效
标题翻译：制造硅/钨丝或w / tiw欧姆接触硅的方法
公开(公告)号：US4845050A
公开(公告)日：1989-07-04
申请号：US121183
申请日：1987-11-16
申请人： Manjin J. Kim , Dale M. Brown , Simon S. Cohen , Bernard Gorowitz , Richard J. Saia
发明人： Manjin J. Kim , Dale M. Brown , Simon S. Cohen , Bernard Gorowitz , Richard J. Saia
IPC分类号： H01L21/285 , H01L21/768
CPC分类号： H01L21/28512 , H01L21/76879 , Y10S148/003
摘要： A conductive member consisting of a first conductor of an alloy of titanium and tungsten and a second conductor of a refractory metal such as molybdenum is sintered to a conductive member of silicon to a temperature in the range of 600.degree. C. to 650.degree. C. in a reducing atmosphere to form a low resistance contact.
摘要翻译：将由钛和钨的合金的第一导体和诸如钼的难熔金属的第二导体组成的导电构件烧结到硅的导电构件至600℃至650℃的温度。在还原气氛中形成低电阻接触。

10. 发明授权

US4444618A Processes and gas mixtures for the reactive ion etching of aluminum and aluminum alloys 失效
标题翻译：用于铝和铝合金反应离子蚀刻的工艺和气体混合物
公开(公告)号：US4444618A
公开(公告)日：1984-04-24
申请号：US471617
申请日：1983-03-03
申请人： Richard J. Saia , Bernard Gorowitz
发明人： Richard J. Saia , Bernard Gorowitz
IPC分类号： C23F4/00 , C23F1/12 , H01L21/02 , H01L21/302 , H01L21/3065 , H01L21/3213 , C23F1/02 , C03C15/00 , C03C25/06
CPC分类号： H01L21/02071
摘要： A method and gas mixture of boron trichloride, carbon tetrachloride and oxygen useful for the reactive ion etching of aluminum and aluminum alloys to form metallizations for microelectronic devices and circuits is provided. The method and gas mixture provide consistent induction periods, high etch rates, high selectivity between photoresist and silicon dioxide, and minimal loading effects with good dimensional control. Also provided is a two step, two gas mixture process particularly useful in preventing linewidth loss due to excessive resist erosion during long overetches wherein the boron trichloride, carbon tetrachloride and oxygen gas mixture is used for etching and subsequently a boron trichloride-oxygen gas mixture is used for the overetch.
摘要翻译：提供了用于铝和铝合金的反应离子蚀刻的三氯化硼，四氯化碳和氧气的方法和气体混合物，以形成用于微电子器件和电路的金属化。该方法和气体混合物提供一致的诱导期，高蚀刻速率，光致抗蚀剂和二氧化硅之间的高选择性，以及具有良好尺寸控制的最小负载效应。还提供两步二气混合方法，其特别可用于防止在长时间过蚀刻过程中过度的抗蚀剂侵蚀引起的线宽损失，其中使用三氯化硼，四氯化碳和氧气混合物进行蚀刻，随后将三氯化硼 - 氧气混合物用于overetch。

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