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1. 发明授权

US06614103B1 Plastic packaging of LED arrays 有权
公开(公告)号：US06614103B1
公开(公告)日：2003-09-02
申请号：US09654163
申请日：2000-09-01
申请人： Kevin Matthew Durocher , Ernest Wayne Balch , Vikram B. Krishnamurthy , Richard Joseph Saia , Herbert Stanley Cole , Ronald Frank Kolc
发明人： Kevin Matthew Durocher , Ernest Wayne Balch , Vikram B. Krishnamurthy , Richard Joseph Saia , Herbert Stanley Cole , Ronald Frank Kolc
IPC分类号： B60Q100
CPC分类号： H01L23/13 , H01L23/3677 , H01L23/49833 , H01L24/48 , H01L24/97 , H01L33/46 , H01L33/62 , H01L2224/05599 , H01L2224/16 , H01L2224/45099 , H01L2224/48091 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/01058 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/07811 , H01L2924/10329 , H01L2924/12041 , H01L2924/12042 , H01L2924/1433 , H01L2924/15153 , H01L2924/15157 , H01L2924/15165 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , Y10S362/80 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.

2. 发明授权

US06242282B1 Circuit chip package and fabrication method 有权
公开(公告)号：US06242282B1
公开(公告)日：2001-06-05
申请号：US09411101
申请日：1999-10-04
申请人： Raymond Albert Fillion , Ernest Wayne Balch , Ronald Frank Kolc , William Edward Burdick, Jr. , Robert John Wojnarowski , Leonard Richard Douglas , Thomas Bert Gorczyca
发明人： Raymond Albert Fillion , Ernest Wayne Balch , Ronald Frank Kolc , William Edward Burdick, Jr. , Robert John Wojnarowski , Leonard Richard Douglas , Thomas Bert Gorczyca
IPC分类号： H01L2144
CPC分类号： H01L24/48 , H01L21/4853 , H01L21/486 , H01L23/5389 , H01L24/11 , H01L24/19 , H01L2224/0401 , H01L2224/05624 , H01L2224/13099 , H01L2224/24227 , H01L2224/4824 , H01L2224/48463 , H01L2224/85399 , H01L2224/92144 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/0103 , H01L2924/01073 , H01L2924/014 , H01L2924/04953 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad. In related embodiments vias are pre-metallized and coupled to chip pads of the circuit chips by an electrically conductive binder. Thin film passive components and multilayer interconnections can additionally be incorporated into the package.

3. 发明授权

US06239980B1 Multimodule interconnect structure and process 有权
标题翻译：多模块互连结构和过程
公开(公告)号：US06239980B1
公开(公告)日：2001-05-29
申请号：US09144486
申请日：1998-08-31
申请人： Raymond Albert Fillion , Wolfgang Daum , Ronald Frank Kolc , Donald William Kuk , Rob Ert John Wojnarowski
发明人： Raymond Albert Fillion , Wolfgang Daum , Ronald Frank Kolc , Donald William Kuk , Rob Ert John Wojnarowski
IPC分类号： H05K114
CPC分类号： H01L23/5389 , H01L23/3107 , H01L23/3135 , H01L23/5383 , H01L23/5385 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/97 , H01L25/0655 , H01L2224/02377 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/24137 , H01L2224/24227 , H01L2224/291 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/81801 , H01L2224/82039 , H01L2224/8319 , H01L2224/8385 , H01L2224/83851 , H01L2224/9202 , H01L2224/97 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10329 , H01L2924/12042 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15192 , H01L2924/15787 , H01L2924/181 , H05K3/323 , H05K3/3436 , H05K3/4688 , Y10T29/49121 , Y10T29/49126 , Y10T29/49144 , H01L2924/00014 , H01L2224/81 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要： A circuit design is logically partitioned into a plurality of blocks. As a first hierarchial assembly level, the blocks are fabricated as individual submodules each including at least one electronic component with component connection pads on a top surface, and a first interconnect structure including at least one interconnect layer bonded to the top surfaces, and interconnecting selected ones of the component connection pads. Submodule connection pads are provided on upper surfaces of the submodules. As a second hierarchial assembly level, a second interconnect structure is bonded to the upper surfaces and interconnects selected ones of the submodule connection pads.
摘要翻译：逻辑上将电路设计分割成多个块。作为第一层级组装级别，块被制造为各个子模块，每个子模块包括至少一个电子部件，其中顶部表面上具有部件连接焊盘，以及第一互连结构，其包括结合到顶部表面的至少一个互连层，组件连接垫中的一个。在子模块的上表面上提供子模块连接垫。作为第二层级组装级别，第二互连结构被结合到上表面并互连所选择的子模块连接焊盘。

4. 发明授权

US06730533B2 Plastic packaging of LED arrays 有权
公开(公告)号：US06730533B2
公开(公告)日：2004-05-04
申请号：US10387862
申请日：2003-03-14
申请人： Kevin Matthew Durocher , Ernest Wayne Balch , Vikram B. Krishnamurthy , Richard Joseph Saia , Herbert Stanley Cole , Ronald Frank Kolc
发明人： Kevin Matthew Durocher , Ernest Wayne Balch , Vikram B. Krishnamurthy , Richard Joseph Saia , Herbert Stanley Cole , Ronald Frank Kolc
IPC分类号： H01L2100
CPC分类号： H01L23/13 , H01L23/3677 , H01L23/49833 , H01L24/48 , H01L24/97 , H01L33/46 , H01L33/62 , H01L2224/05599 , H01L2224/16 , H01L2224/45099 , H01L2224/48091 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/01058 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/07811 , H01L2924/10329 , H01L2924/12041 , H01L2924/12042 , H01L2924/1433 , H01L2924/15153 , H01L2924/15157 , H01L2924/15165 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , Y10S362/80 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.

5. 发明授权

US06396153B2 Circuit chip package and fabrication method 有权
标题翻译：电路芯片封装及制作方法
公开(公告)号：US06396153B2
公开(公告)日：2002-05-28
申请号：US09768598
申请日：2001-01-25
申请人： Raymond Albert Fillion , Ernest Wayne Balch , Ronald Frank Kolc , William Edward Burdick, Jr. , Robert John Wojnarowski , Leonard Richard Douglas , Thomas Bert Gorczyca
发明人： Raymond Albert Fillion , Ernest Wayne Balch , Ronald Frank Kolc , William Edward Burdick, Jr. , Robert John Wojnarowski , Leonard Richard Douglas , Thomas Bert Gorczyca
IPC分类号： H01L2348
CPC分类号： H01L24/48 , H01L21/4853 , H01L21/486 , H01L23/5389 , H01L24/11 , H01L24/19 , H01L2224/0401 , H01L2224/05624 , H01L2224/13099 , H01L2224/24227 , H01L2224/4824 , H01L2224/48463 , H01L2224/85399 , H01L2224/92144 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/0103 , H01L2924/01073 , H01L2924/014 , H01L2924/04953 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad. In related embodiments vias are pre-metallized and coupled to chip pads of the circuit chips by an electrically conductive binder. Thin film passive components and multilayer interconnections can additionally be incorporated into the package.
摘要翻译：一种用于封装至少一个电路芯片的方法包括：提供包括具有第一侧和第二侧的绝缘材料的互连层，在第二侧的第二侧金属化部分上而不是在第二侧非金属化部分上图案化的初始金属化第二侧，至少一个从第一侧延伸到第二侧金属化部分之一的衬底通孔;以及至少一个芯片通孔，其从第一侧延伸到第二侧非金属化部分之一; 将所述至少一个电路芯片定位在所述第二侧上，所述至少一个电路芯片的至少一个芯片焊盘与所述至少一个芯片通孔对准; 以及在所述互连层的第一侧和所述通孔的选定部分上图案化连接金属化，以便延伸到所述至少一个第二侧金属化部分和所述至少一个芯片焊盘。在相关实施例中，通孔被预先金属化并且通过导电粘合剂耦合到电路芯片的芯片焊盘。薄膜无源元件和多层互连可另外包含在封装中。

6. 发明授权

US06239482B1 Integrated circuit package including window frame 有权
标题翻译：集成电路封装包括窗框
公开(公告)号：US06239482B1
公开(公告)日：2001-05-29
申请号：US09334572
申请日：1999-06-21
申请人： Raymond Albert Fillion , William Edward Burdick, Jr. , Ronald Frank Kolc , James Wilson Rose , Glenn Scott Claydon
发明人： Raymond Albert Fillion , William Edward Burdick, Jr. , Ronald Frank Kolc , James Wilson Rose , Glenn Scott Claydon
IPC分类号： H01L2302
CPC分类号： H01L24/25 , H01L23/13 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L2224/04105 , H01L2224/12105 , H01L2224/24137 , H01L2224/24195 , H01L2224/24225 , H01L2224/24227 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/15151 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043
摘要： An integrated circuit package includes at least one integrated circuit element coupled to a polymer film; a window frame coupled to the polymer film and surrounding the at least one integrated circuit element; and encapsulant material positioned between the at least one integrated circuit element and the window frame.
摘要翻译：集成电路封装包括耦合到聚合物膜的至少一个集成电路元件; 耦合到所述聚合物膜并围绕所述至少一个集成电路元件的窗框; 以及位于所述至少一个集成电路元件和所述窗框之间的密封材料。

7. 发明授权

US06733711B2 Plastic packaging of LED arrays 有权
标题翻译： LED阵列的塑料包装
公开(公告)号：US06733711B2
公开(公告)日：2004-05-11
申请号：US10387835
申请日：2003-03-14
申请人： Kevin Matthew Durocher , Ernest Wayne Balch , Vikram B. Krishnamurthy , Richard Joseph Saia , Herbert Stanley Cole , Ronald Frank Kolc
发明人： Kevin Matthew Durocher , Ernest Wayne Balch , Vikram B. Krishnamurthy , Richard Joseph Saia , Herbert Stanley Cole , Ronald Frank Kolc
IPC分类号： B29C4514
CPC分类号： H01L23/13 , H01L23/3677 , H01L23/49833 , H01L24/48 , H01L24/97 , H01L33/46 , H01L33/62 , H01L2224/05599 , H01L2224/16 , H01L2224/45099 , H01L2224/48091 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/01058 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/07811 , H01L2924/10329 , H01L2924/12041 , H01L2924/12042 , H01L2924/1433 , H01L2924/15153 , H01L2924/15157 , H01L2924/15165 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , Y10S362/80 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.
摘要翻译：提供了一种柔性电路模块，包括至少一个刚性载体，安装在至少一个刚性载体的第一侧上的至少一个固态装置，支撑至少一个刚性载体的第二侧的柔性基座，导电互连图案，以及多个馈通电极，其从所述至少一个刚性载体的第一侧延伸到第二侧，并将导电互连图案与多个固态中的至少一个电连接设备。固态器件可以是LED芯片以形成LED阵列模块。

8. 发明授权

US06507113B1 Electronic interface structures and methods of fabrication 有权
标题翻译：电子接口结构和制造方法
公开(公告)号：US06507113B1
公开(公告)日：2003-01-14
申请号：US09443410
申请日：1999-11-19
申请人： Raymond Albert Fillion , Robert John Wojnarowski , Ronald Frank Kolc
发明人： Raymond Albert Fillion , Robert John Wojnarowski , Ronald Frank Kolc
IPC分类号： H01L2348
CPC分类号： H01L23/49838 , H01L23/49811 , H01L24/02 , H01L2224/02125 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/12042 , H05K1/0271 , H05K1/114 , H05K3/326 , H05K3/4007 , H05K3/4644 , H05K2201/0133 , H05K2201/0187 , H05K2201/0367 , H05K2201/09663 , H01L2924/00012 , H01L2924/00
摘要： One type of electronic interface structure includes a base; at least one elastomeric island supported by the base; and patterned metallization overlying the at least one elastomeric island and including at least one floating pad at least partially overlying the at least one elastomeric island. Another type of electronic interface structure includes a base; a first dielectric layer overlying the base and having at least one first dielectric layer opening therein; a second dielectric layer overlying the first dielectric layer; and patterned metallization overlying the second dielectric layer and including at least one floating pad at least partially overlying the at least one opening.
摘要翻译：电子接口结构的一种类型包括基座; 由基座支撑的至少一个弹性岛; 以及覆盖所述至少一个弹性体岛并且包括至少部分地覆盖所述至少一个弹性体岛的至少一个浮动垫的图案化金属化。另一种类型的电子接口结构包括基座; 覆盖所述基底并且在其中开有至少一个第一介电层的第一介电层; 覆盖所述第一介电层的第二电介质层; 以及覆盖在所述第二介电层上并且包括至少部分地覆盖所述至少一个开口的至少一个浮动焊盘的图案化金属化。

9. 发明授权

US5857858A Demountable and repairable low pitch interconnect for stacked multichip modules 失效
标题翻译：用于堆叠多芯片模块的可拆卸和可修复的低间距互连
公开(公告)号：US5857858A
公开(公告)日：1999-01-12
申请号：US773625
申请日：1996-12-23
申请人： Bernard Gorowitz , Robert John Wojnarowski , Ronald Frank Kolc
发明人： Bernard Gorowitz , Robert John Wojnarowski , Ronald Frank Kolc
IPC分类号： H01L25/065 , H05K1/14 , H05K3/32 , H05K3/40 , H05K1/11
CPC分类号： H05K3/325 , H01L25/0652 , H05K1/144 , H01L2924/0002 , H01L2924/3011 , H05K3/403
摘要： Connection elements which, for example, may be used to facilitate interconnection to and stacking of electronic assemblies or may include an elongated conductive core, such as a wire or a hollow tube structure, coated with a layer of elastomeric material containing conductive particle such that the elastomeric material is conductive at least when compressed. The substrates of multi-chip modules (MCMs) have electrical connection sites in the form of metal-lined channels in the substrate edges, and the connection elements are pressed into the channels. Separate compression or clamping elements may be employed to enhance conductivity, as well as to facilitate external connections. The elongated conductive core may take the form of a hollow tube structure which may be expanded under internal pressure to compress the layer of elastomeric material. The compression elements may take the form of printed circuit boards. In alternative embodiments the connection elements may be clamped between conductive channels of side-by-side substrates or between opposed conductive channels of stacked substrates.
摘要翻译：连接元件例如可用于促进电子组件的互连和堆叠，或者可以包括细长导电芯，例如线或中空管结构，涂覆有包含导电颗粒的弹性体材料层，使得至少在压缩时弹性材料是导电的。多芯片模块（MCM）的基板在基板边缘中具有金属衬里通道形式的电连接位置，并且连接元件被压入通道中。可以使用单独的压缩或夹紧元件来增强导电性，并且便于外部连接。细长导电芯可以采取中空管结构的形式，其可以在内部压力下膨胀以压缩弹性体材料层。压缩元件可以采用印刷电路板的形式。在替代实施例中，连接元件可以被夹持在并排衬底的导电沟道之间或层叠衬底的相对的导电沟道之间。

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