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1. 发明授权

US5527741A Fabrication and structures of circuit modules with flexible interconnect layers 失效
标题翻译：具有柔性互连层的电路模块的制造和结构
公开(公告)号：US5527741A
公开(公告)日：1996-06-18
申请号：US321346
申请日：1994-10-11
申请人： Herbert S. Cole , Raymond A. Fillion , Bernard Gorowitz , Ronald F. Kolc , Robert J. Wojnarowski
发明人： Herbert S. Cole , Raymond A. Fillion , Bernard Gorowitz , Ronald F. Kolc , Robert J. Wojnarowski
IPC分类号： H01L21/60 , H01L21/48 , H01L23/538 , H05K3/32
CPC分类号： H05K3/32 , H01L21/4857 , H01L23/5383 , H01L23/5387 , H01L24/24 , H01L24/82 , H01L2224/04105 , H01L2224/24137 , H01L2224/32225 , H01L2224/73267 , H01L2224/82047 , H01L2224/92144 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01025 , H01L2924/01027 , H01L2924/01029 , H01L2924/01078 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , Y10T29/4913
摘要： A method for fabricating a circuit module includes applying an outer insulative layer over a first patterned metallization layer on a first surface of a base insulative layer. A second surface of the base insulative layer has a second patterned metallization layer. At least one circuit chip having chip pads is attached to the second surface of the base insulative layer. Respective vias are formed to expose selected portions of the first patterned metallization layer, the second patterned metallization layer, and the chip pads. A patterned outer metallization layer is applied over the outer insulative layer to extend through selected ones of the vias to interconnect selected ones of the chip pads and selected portions of the first and second metallization layers.
摘要翻译：一种用于制造电路模块的方法包括在绝缘层的第一表面上的第一图案化金属化层上施加外部绝缘层。基极绝缘层的第二表面具有第二图案化金属化层。具有芯片焊盘的至少一个电路芯片附接到基极绝缘层的第二表面。形成各个通孔以暴露第一图案化金属化层，第二图案化金属化层和芯片焊盘的选定部分。图案化的外部金属化层被施加在外部绝缘层上以延伸通过选定的通孔以互连所选择的芯片焊盘和第一和第二金属化层的选定部分。

2. 发明授权

US5353498A Method for fabricating an integrated circuit module 失效
标题翻译：集成电路模块的制造方法
公开(公告)号：US5353498A
公开(公告)日：1994-10-11
申请号：US87434
申请日：1993-07-09
申请人： Raymond A. Fillion , Robert J. Wojnarowski , Michael Gdula , Herbert S. Cole , Eric J. Wildi , Wolfgang Daum
发明人： Raymond A. Fillion , Robert J. Wojnarowski , Michael Gdula , Herbert S. Cole , Eric J. Wildi , Wolfgang Daum
IPC分类号： H01L23/52 , H01L21/56 , H01L21/58 , H01L21/68 , H01L23/29 , H01L23/433 , H01L23/538 , H01L25/04 , H01L25/065 , H01L25/18 , H05K3/34
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/293 , H01L23/295 , H01L23/4334 , H01L23/538 , H01L23/5389 , H01L24/24 , H01L24/29 , H01L24/82 , H01L24/83 , H01L24/96 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L2224/04105 , H01L2224/2402 , H01L2224/24137 , H01L2224/24195 , H01L2224/2518 , H01L2224/2919 , H01L2224/82039 , H01L2224/83192 , H01L2224/8385 , H01L2225/06517 , H01L2225/0652 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06589 , H01L2225/1035 , H01L2225/1058 , H01L2225/1064 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/12042 , H01L2924/14 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , Y10T29/49144
摘要： Substrate material is molded directly to semiconductor chips and other electrical components that are positioned for integrated circuit module fabrication. Chips having contact pads are placed face down on a layer of adhesive supported by a base. A mold form is positioned around the chips. Substrate molding material is added within the mold form, and the substrate molding material is then hardened. A dielectric layer having vias aligned with predetermined ones of the contact pads and having an electrical conductor extending through the vias is situated on the hardened substrate molding material and the faces of the chips. A thermal plug may be affixed to the backside of a chip before substrate molding material is added. A connector frame may be placed on the adhesive layer before substrate molding material is added. A dielectric layer may be placed over the backsides of the chips before the substrate molding material is added to enhance repairability. A portion of the chips and substrate molding material may be removed after the substrate molding material is hardened.
摘要翻译：基板材料直接模制到半导体芯片和其他用于集成电路模块制造的电气部件。具有接触垫的芯片面朝下放置在由基底支撑的粘合剂层上。模具周围位于芯片周围。在模具形式中加入基材成型材料，然后将基材成型材料硬化。具有与预定接触焊盘对准的通孔并具有延伸通过通孔的电导体的通孔的电介质层位于硬化的基底成型材料和芯片的表面上。在添加基板模制材料之前，可以将热塞固定到芯片的背面。在添加基材模塑材料之前，连接器框架可以放置在粘合剂层上。在添加基底成型材料之前，可以将电介质层放置在芯片的背面上以增强可修复性。芯片和基材成型材料的一部分可以在基材模塑材料硬化之后被去除。

3. 发明授权

US5422513A Integrated circuit chip placement in a high density interconnect structure 失效
标题翻译：集成电路芯片放置在高密度互连结构中
公开(公告)号：US5422513A
公开(公告)日：1995-06-06
申请号：US329516
申请日：1993-10-04
申请人： Walter M. Marcinkiewicz , Raymond A. Fillion , Barry S. Whitmore , Robert J. Wojnarowski
发明人： Walter M. Marcinkiewicz , Raymond A. Fillion , Barry S. Whitmore , Robert J. Wojnarowski
IPC分类号： H01L23/538 , H01L23/485 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L23/5389 , H01L24/24 , H01L24/82 , H01L2224/2402 , H01L2224/24227 , H01L2924/01011 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01322 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/19041 , H01L2924/3011
摘要： A high density interconnect (HDI) structure having a dielectric multi-layer interconnect structure on a substrate is fabricated by forming a chip well, placing a chip in the well, and connecting the chip to the interconnect structure. Additionally, temperature sensitive chips or devices may be located beneath the dielectric multi-layer interconnect structure. A spacer die may be located in the substrate while the interconnect structure is fabricated and removed after a chip well aligned with the spacer die is formed, in order to accommodate a chip thickness which is greater than the dielectric multi-layer interconnect structure thickness.
摘要翻译：通过形成芯片，将芯片放置在阱中，并将芯片连接到互连结构来制造在衬底上具有电介质多层互连结构的高密度互连（HDI）结构。此外，温度敏感的芯片或器件可以位于电介质多层互连结构之下。间隔管芯可以位于衬底中，同时在形成与间隔管芯形成良好对准的芯片之后制造和移除互连结构，以便适应大于电介质多层互连结构厚度的芯片厚度。

4. 发明授权

US5353195A Integral power and ground structure for multi-chip modules 失效
标题翻译：多芯片模块的集成电源和接地结构
公开(公告)号：US5353195A
公开(公告)日：1994-10-04
申请号：US87433
申请日：1993-07-09
申请人： Raymond A. Fillion , Robert J. Wojnarowski
发明人： Raymond A. Fillion , Robert J. Wojnarowski
IPC分类号： H01L23/50 , H01L23/538 , H05K7/02
CPC分类号： H01L24/82 , H01L23/50 , H01L23/5389 , H01L24/24 , H01L2224/24225 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2224/82039 , H01L2224/82047 , H01L2224/92144 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043
摘要： A multi-chip module includes a substrate supporting a plurality of chips. A dielectric layer which overlies the chips and the substrate has a connection surface and a substrate surface with metallization planes having plane openings patterned on each surface and vias aligned with predetermined pads on the chips and predetermined portions of the metallization plane of the substrate surface. An adhesive layer is situated between the substrate and the substrate surface of the dielectric layer, and a pattern of electrical conductors extends through the vias to interconnect selected chips and selected portions of the metallization planes. In a related design, the dielectric layer may be a board having chip openings and conductive through-connections aligned with predetermined portions of the metallization plane of the substrate surface. The board can be thick enough that chip wells are not necessary for each chip, in which case, a base dielectric layer having vias aligned with chip pads, through-connections and the connection surface overlies the board and supports a pattern of electrical conductors which interconnect the chips and metallization planes.
摘要翻译：多芯片模块包括支撑多个芯片的基板。覆盖芯片和衬底的电介质层具有连接表面和衬底表面，其中金属化平面具有在每个表面上图案化的平面开口，并且与衬底表面的芯片和金属化平面的预定部分上的预定焊盘对准的通孔。粘合剂层位于基底和介电层的基底表面之间，并且电导体的图形延伸穿过通孔以互连选定的切屑和金属化平面的选定部分。在相关设计中，电介质层可以是具有芯片开口和与衬底表面的金属化平面的预定部分对准的导电贯穿连接的板。板可以足够厚，使得每个芯片不需要芯片阱，在这种情况下，具有与芯片焊盘，通孔连接对准的通孔的基底介电层，并且连接表面覆盖在板上并且支撑电连接的图案芯片和金属化平面。

5. 发明授权

US5391516A Method for enhancement of semiconductor device contact pads 失效
标题翻译：用于增强半导体器件接触焊盘的方法
公开(公告)号：US5391516A
公开(公告)日：1995-02-21
申请号：US774427
申请日：1991-10-10
申请人： Robert J. Wojnarowski , Bernard Gorowitz
发明人： Robert J. Wojnarowski , Bernard Gorowitz
IPC分类号： H01L21/768 , H01L21/268 , H01L21/311 , H01L21/441
CPC分类号： H01L21/76877 , H01L24/05 , H01L2924/12042 , H01L2924/14
摘要： Semiconductor device contact pads are enhanced by forming a metal plate over at least a portion of the contact pad. "Enhancement" includes repair such as by bridging a reinforcing pad area over probe damage, general reinforcement or enlargement of a contact pad, and placement of a protective buffer pad over a contact pad. These methods are applicable to any semiconductor device with contact pads on a surface thereof, such as entire wafers, individual dice, and multi-chip High Density Interconnect (HDI) modules. The pad enhancement plate is formed by applying a planarizing dielectric layer over the entire device (if not already formed in the initial stages of HDI processing), and an enhancement access via is then formed to expose a portion of the contact pad to be enhanced. The entire device is metallized, and metal not over the exposed portion of the contact pad is subsequently removed. Localized heating of the metal plate can be achieved by a laser to effectuate a selective pseudo-weld or produce sintering for a low resistance ohmic contact.
摘要翻译：通过在接触垫的至少一部分上形成金属板来增强半导体器件接触焊盘。 “增强”包括修复，例如通过桥接加强垫区域超过探测器损伤，通常加强或扩大接触垫，以及将保护性缓冲垫放置在接触垫上。这些方法适用于具有其表面上的接触焊盘的任何半导体器件，例如整个晶片，单个晶片和多芯片高密度互连（HDI）模块。通过在整个装置（如果在HDI处理的初始阶段尚未形成）中施加平坦化介电层来形成焊盘增强板，然后形成增强接入通路，以使接触焊盘的一部分暴露出增强。整个装置被金属化，并且随后去除接触垫的暴露部分之上的金属。可以通过激光来实现金属板的局部加热，以实现选择性伪焊接或产生用于低电阻欧姆接触的烧结。

6. 发明授权

US5366906A Wafer level integration and testing 失效
标题翻译：晶圆级集成和测试
公开(公告)号：US5366906A
公开(公告)日：1994-11-22
申请号：US962000
申请日：1992-10-16
申请人： Robert J. Wojnarowski , Constantine A. Neugebauer , Wolfgang Daum , Bernard Gorowitz , Eric J. Wildi , Michael Gdula , Stanton E. Weaver, Jr. , Anthony A. Immorlica, Jr.
发明人： Robert J. Wojnarowski , Constantine A. Neugebauer , Wolfgang Daum , Bernard Gorowitz , Eric J. Wildi , Michael Gdula , Stanton E. Weaver, Jr. , Anthony A. Immorlica, Jr.
IPC分类号： G01R31/3185 , H01L21/301 , H01L21/66 , H01L23/538 , H01L23/58 , G01R31/26
CPC分类号： H01L22/22 , H01L22/32 , H01L23/5389 , H01L24/24 , H01L24/82 , G01R31/318505 , G01R31/318533 , H01L2224/2402 , H01L2224/24137 , H01L2224/24227 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2924/3011 , H01L2924/351
摘要： In fabricating wafer scale integrated interconnects, a temporary or permanent dielectric layer and a pattern of electrical conductors are used to provide wafer scale integration or testing and burn-in. A resist can be used to cover the areas of IC pads on the wafer while the remainder of the pattern of electrical conductors is removed to provide for repair of the wafer scale integration structure. The pattern of electrical conductors may be configured so that the conductor lengths between at least some sub-circuits on a plurality of wafers are substantially electrically equal for signal propagation purposes; an additional wafer may be laminated to the wafer using an adhesive; controlled curfs may be cut into the wafer; and the wafer may be interconnected to an interface ring.
摘要翻译：在制造晶片级集成互连件时，使用临时或永久的电介质层和电导体图案来提供晶片级整合或测试和老化。可以使用抗蚀剂来覆盖晶片上的IC焊盘的区域，而去除电导体图案的其余部分以提供晶片级整合结构的修复。电导体的图案可以被配置为使得在多个晶片上的至少一些子电路之间的导体长度对于信号传播目的而基本上是电相等的; 可以使用粘合剂将另外的晶片层压到晶片上; 受控的曲折可以被切入晶片; 并且晶片可以互连到接口环。

7. 发明授权

US5157589A Mutliple lamination high density interconnect process and structure employing thermoplastic adhesives having sequentially decreasing T.sub.G ' s 失效
标题翻译： MUTLIPLE LAMINATION高密度互连过程和结构使用具有顺序降低的热塑性粘合剂
公开(公告)号：US5157589A
公开(公告)日：1992-10-20
申请号：US546963
申请日：1990-07-02
申请人： Herbert S. Cole, Jr. , James W. Rose , Charles W. Eichelberger , Robert J. Wojnarowski
发明人： Herbert S. Cole, Jr. , James W. Rose , Charles W. Eichelberger , Robert J. Wojnarowski
IPC分类号： H01L23/13 , H01L23/498 , H01L23/538 , H01L25/04 , H01L25/18 , H05K1/18 , H05K3/38 , H05K3/46
CPC分类号： H01L23/5389 , H01L23/13 , H01L23/49822 , H01L24/24 , H01L24/82 , H05K3/4635 , H05K3/4673 , H01L2224/2402 , H01L2224/24227 , H01L2224/73267 , H01L2224/82039 , H01L2224/92244 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01074 , H01L2924/01082 , H01L2924/04953 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15787 , H05K1/185 , H05K2201/0129 , H05K2201/0154 , H05K2201/0195 , H05K3/386 , H05K3/4644
摘要： A high density interconnect structure incorporating a plurality of laminated dieletric layers is fabricated using thermoplastic adhesive layers of progressively lower glass transition temperature in order to maintain the stability of the already fabricated structure during the addition of the later laminations. This structure also facilitates the removal of only a portion of the high density interconnect structure where a fault in the system can be corrected in one of the upper layers of the high density interconnect structure.

8. 发明授权

US5562838A Optical light pipe and microwave waveguide interconnects in multichip modules formed using adaptive lithography 失效
公开(公告)号：US5562838A
公开(公告)日：1996-10-08
申请号：US037833
申请日：1993-03-29
申请人： Robert J. Wojnarowski , Herbert S. Cole , John L. Henkes
发明人： Robert J. Wojnarowski , Herbert S. Cole , John L. Henkes
IPC分类号： B29D11/00 , G02B6/12 , G02B6/122 , G02B6/13 , G02B6/36 , G02B6/42 , G02B6/43 , G02B6/00
CPC分类号： B29D11/00701 , G02B6/1221 , G02B6/13 , G02B6/421 , G02B6/43 , G02B2006/12173 , G02B2006/12176
摘要： HDI fabrication techniques are employed to form a variety of optical waveguide structures in polymer materials. Adaptive optical connections are formed, taking into account the actual position and orientation of devices which may deviate from the ideal. Structures include solid light-conducting structures, hollow light-conducting structures which are also suitable for conducting cooling fluid, and optical switching devices employing liquid crystal material. A "shrink back" method may be used to form a tunnel in polymer material which is then filled with an uncured polymer material that shrinks upon curing.

9. 发明授权

US5554305A Processing low dielectric constant materials for high speed electronics 失效
公开(公告)号：US5554305A
公开(公告)日：1996-09-10
申请号：US411178
申请日：1995-03-27
申请人： Robert J. Wojnarowski , Herbert S. Cole , Theresa A. Sitnik-Nieters , Wolfgang Daum
发明人： Robert J. Wojnarowski , Herbert S. Cole , Theresa A. Sitnik-Nieters , Wolfgang Daum
IPC分类号： B32B7/02 , B32B18/00 , H01L21/48 , H01L21/60 , H01L23/498 , H01L23/538 , H05K1/02 , H05K1/03 , H05K3/00 , H05K3/38 , H01L21/3105
CPC分类号： H05K1/0313 , H01L21/481 , H01L23/49894 , H01L23/5389 , H01L24/24 , H01L24/82 , H05K1/024 , H05K1/0373 , H05K3/0032 , H01L2224/2402 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01052 , H01L2924/01074 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/3011 , H05K2201/0116 , H05K2201/015 , H05K2201/0158 , H05K2203/083 , H05K2203/122 , H05K3/386 , Y10S521/918 , Y10T29/49124 , Y10T29/49155
摘要： A method for processing a low dielectric constant material includes dispersing an additive material in a porous low dielectric constant layer, fabricating a desired electronic structure, and then removing the additive material from the pores of the low dielectric constant layer. The removal of the additive material from the pores can be accomplished by sublimation, evaporation, and diffusion. Applications for the low dielectric constant layer include the use as an overlay layer for interconnecting a circuit chip supported by a substrate and the use as printed circuit board material.

10. 发明授权

US5449427A Processing low dielectric constant materials for high speed electronics 失效
标题翻译：加工用于高速电子的低介电常数材料
公开(公告)号：US5449427A
公开(公告)日：1995-09-12
申请号：US247820
申请日：1994-05-23
申请人： Robert J. Wojnarowski , Herbert S. Cole , Theresa A. Sitnik-Nieters , Wolfgang Daum
发明人： Robert J. Wojnarowski , Herbert S. Cole , Theresa A. Sitnik-Nieters , Wolfgang Daum
IPC分类号： B32B7/02 , B32B18/00 , H01L21/48 , H01L21/60 , H01L23/498 , H01L23/538 , H05K1/02 , H05K1/03 , H05K3/00 , H05K3/38 , B32B31/12 , B32B31/14
CPC分类号： H05K1/0313 , H01L21/481 , H01L23/49894 , H01L23/5389 , H01L24/24 , H01L24/82 , H05K1/024 , H05K1/0373 , H05K3/0032 , H01L2224/2402 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01052 , H01L2924/01074 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/3011 , H05K2201/0116 , H05K2201/015 , H05K2201/0158 , H05K2203/083 , H05K2203/122 , H05K3/386 , Y10S521/918 , Y10T29/49124 , Y10T29/49155
摘要： A method for processing a low dielectric constant material includes dispersing an additive material in a porous low dielectric constant layer, fabricating a desired electronic structure, and then removing the additive material from the pores of the low dielectric constant layer. The removal of the additive material from the pores can be accomplished by sublimation, evaporation, and diffusion. Applications for the low dielectric constant layer include the use as an overlay layer for interconnecting a circuit chip supported by a substrate and the use as printed circuit board material.
摘要翻译：用于处理低介电常数材料的方法包括将添加剂材料分散在多孔低介电常数层中，制造所需的电子结构，然后从低介电常数层的孔中除去添加剂材料。从孔中去除添加剂材料可以通过升华，蒸发和扩散来实现。用于低介电常数层的应用包括用作互连由衬底支撑的电路芯片和用作印刷电路板材料的覆盖层的用途。

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