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1. 发明授权

US06952240B2 Image sampling circuit with a blank reference combined with the video input 有权
标题翻译：具有空白参考的图像采样电路与视频输入相结合
公开(公告)号：US06952240B2
公开(公告)日：2005-10-04
申请号：US09860905
申请日：2001-05-18
申请人： Richard L. Gower , Eric G. Hoffman , Bhupendra K. Ahuja , J. Antonio Salcedo
发明人： Richard L. Gower , Eric G. Hoffman , Bhupendra K. Ahuja , J. Antonio Salcedo
IPC分类号： H03F3/00 , H03F3/45 , H04N5/16 , H04N5/20 , H04N5/217 , H04N5/361 , H04N5/378 , H04N5/52
CPC分类号： H04N5/2176 , H03F3/005 , H03F3/45197 , H03F2203/45504 , H03F2203/45616 , H03F2203/45726 , H04N5/16 , H04N5/20
摘要： A programmable gain amplifier having three separately programmable amplifiers. A programmable transconductance amplifier is followed by a programmable transimpedance amplifier, then a programmable switched capacitor amplifier. In one embodiment, this programmable gain amplifier is implemented in an analog front-end (AFE) circuit. One AFE embodiment provides a coarse pre-gain offset a black reference level sampler, and a fine post-gain offset in the programmable switched capacitor amplifier. In one embodiment, an ADC reference is sampled, and is subtracted directly from the video signal in the switched capacitor amplifier so that the zero level of the video signal is made to correspond to the zero level of the ADC. In another embodiment, a piece-wise linear approximation of an exponential gain function is implemented by programming the transconductance and transimpedance amplifiers to provide exponential jumps in gain, while the switched capacitor amplifier is programmed to interpolate as needed between the exponential gain levels.
摘要翻译：具有三个可单独编程的放大器的可编程增益放大器。可编程跨导放大器之后是可编程跨阻抗放大器，然后是可编程开关电容放大器。在一个实施例中，该可编程增益放大器在模拟前端（AFE）电路中实现。一个AFE实施例在可编程开关电容放大器中提供黑色参考电平采样器的粗预增益偏移和精细后增益偏移。在一个实施例中，对ADC参考进行采样，并且直接从开关电容放大器中的视频信号中减去，以使视频信号的零电平对应于ADC的零电平。在另一个实施例中，通过编程跨导和跨阻抗放大器来提供指数增益函数的分段线性近似来提供增益中的指数跳跃，而开关电容放大器被编程为根据需要在指数增益水平之间内插。

2. 发明授权

US5909187A Current steering circuit for a digital-to-analog converter 失效
标题翻译：用于数模转换器的电流转向电路
公开(公告)号：US5909187A
公开(公告)日：1999-06-01
申请号：US918344
申请日：1997-08-26
申请人： Bhupendra K. Ahuja
发明人： Bhupendra K. Ahuja
IPC分类号： H03K17/041 , H03M1/74 , H03M1/66
CPC分类号： H03K17/04106 , H03M1/742
摘要： An improved current steering cell for a DAC which eliminates the need for an inverter reduces the noise at the common mode. The cell includes a first and a second current steering MOS transistor of a first polarity type, each having a gate and a pair of current passing terminals. The cell has an input terminal for receiving digital input signals coupled to the gate of the first of the pair of current steering transistors, and a common mode node for receiving an input current coupled to the same one of the pair of current passing terminals of each current steering MOS transistor. The current output terminal of the cell is coupled to the other of the pair of current passing terminals of the first of the current steering MOS transistors. Finally, the cell includes a third MOS transistor of the opposite polarity type to the current steering MOS transistors, having a gate and a pair of current passing terminals for passing a current through the transistor, the gate of the third MOS transistor being coupled to the gate of the first MOS current steering transistor, and the current passing terminals of the third MOS transistor being coupled between the gate of the second MOS current steering transistor and one of the pair of current passing terminals of the second MOS current steering transistor.
摘要翻译：用于DAC的改进的电流转向单元消除了对逆变器的需要，降低了在共模下的噪声。电池包括第一极性类型的第一和第二电流转向MOS晶体管，每个具有栅极和一对电流通过端子。电池具有用于接收耦合到一对电流转向晶体管中的第一对的栅极的数字输入信号的输入端子，以及用于接收耦合到每对电流对的一对电流通过端子中的相同一个的输入电流的共模节点电流转向MOS晶体管。电池的电流输出端子耦合到第一电流转向MOS晶体管的一对电流通过端子中的另一个。最后，电池包括与电流转向MOS晶体管相反极性类型的第三MOS晶体管，具有用于使电流通过晶体管的栅极和一对电流通过端子，第三MOS晶体管的栅极耦合到并且第三MOS晶体管的电流通过端子耦合在第二MOS电流转向晶体管的栅极和第二MOS电流转向晶体管的一对电流通过端子中的一个之间。

3. 发明授权

US4442529A Power supply rejection characteristics of CMOS circuits 失效
标题翻译： CMOS电路的电源抑制特性
公开(公告)号：US4442529A
公开(公告)日：1984-04-10
申请号：US231478
申请日：1981-02-04
申请人： Bhupendra K. Ahuja , Mirmira R. Dwarakanath
发明人： Bhupendra K. Ahuja , Mirmira R. Dwarakanath
IPC分类号： H01L27/092 , G05F1/46 , H01L21/8238 , H01L27/02 , H01L29/78 , H01L27/04 , H04L3/00
CPC分类号： H01L27/0218 , G05F1/467
摘要： In a conventional CMOS integrated circuit such as a switched capacitor filter, power supply noise signals are coupled from the substrate to high impedance nodes via various parasitic capacitances. To minimize these noise signals and thereby improve the power supply rejection ratio of the circuit, only N-channel transistors are coupled to the nodes. Additionally, the P-tubs of these transistors are connected to an on-chip regulated power supply. Moreover, for certain metallic runners and capacitors of the circuit that are connected to the specified nodes and parasitically coupled to the substrate, grounded P-tubs are formed directly under the runners and capacitors.
摘要翻译：在诸如开关电容滤波器的常规CMOS集成电路中，电源噪声信号通过各种寄生电容从衬底耦合到高阻抗节点。为了最小化这些噪声信号，从而提高电路的电源抑制比，只有N沟道晶体管耦合到节点。此外，这些晶体管的P型桶连接到片上稳压电源。此外，对于连接到指定节点并寄生耦合到基板的电路的某些金属流道和电容器，接地的P型桶形成在流道和电容器的正下方。

4. 发明授权

US07221209B2 Precision floating gate reference temperature coefficient compensation circuit and method 有权
标题翻译：精密浮栅参考温度系数补偿电路及方法
公开(公告)号：US07221209B2
公开(公告)日：2007-05-22
申请号：US11129455
申请日：2005-05-12
申请人： Bhupendra K. Ahuja , Hoa Vu , Carlos Laber
发明人： Bhupendra K. Ahuja , Hoa Vu , Carlos Laber
IPC分类号： H01L35/00
CPC分类号： G05F3/30
摘要： A circuit and corresponding method for a precision floating gate voltage reference that uses a feedback loop, conduction of tunnel devices, and a bandgap cell to accurately program a desired charge level on a floating gate and provide a predictable and programmable temperature coefficient parameter for such voltage reference. In one embodiment, a bandgap cell is coupled through a capacitor to the floating gate storage node for providing a voltage source for canceling the temperature coefficient (TC) of the storage capacitor. The circuit and method enables TC to be minimized by either choosing the proper voltage source characteristics or alternatively, by choosing the proper ratio of two capacitors. The bandgap cell can alternatively be designed to have positive TC (PTAT voltage sources) or negative TC (VBE junction).
摘要翻译：一种用于精密浮动栅极电压基准的电路和相应方法，其使用反馈回路，隧道装置的导通以及带隙单元来精确地编程浮动栅极上的期望电荷电平，并为这种电压提供可预测和可编程的温度系数参数参考。在一个实施例中，带隙单元通过电容器耦合到浮动栅极存储节点，用于提供用于消除存储电容器的温度系数（TC）的电压源。电路和方法可以通过选择适当的电压源特性或者通过选择两个电容器的适当比例来最小化TC。可替代地，带隙单元可被设计为具有正的TC（PTAT电压源）或负的TC（VBE结）。

5. 发明授权

US06246283B1 Power efficient line driver 有权
公开(公告)号：US06246283B1
公开(公告)日：2001-06-12
申请号：US09432507
申请日：1999-11-02
申请人： Bhupendra K. Ahuja , Cary L. Delano , Adya S. Tripathi
发明人： Bhupendra K. Ahuja , Cary L. Delano , Adya S. Tripathi
IPC分类号： H03F136
CPC分类号： H03F1/0244 , H03F2200/331 , H03H11/1217
摘要： A signal processing circuit is described including a frequency selective network in a feedback loop. An analog-to-analog converter in the feedback loop is coupled to the frequency selective network. A continuous-time feedback path provides feedback from the output terminal of the analog-to-analog converter to the frequency selective network.

6. 发明授权

US07371005B1 Automatic circuit and method for temperature compensation of oscillator frequency variation over temperature for a real time clock chip 有权
标题翻译：用于实时时钟芯片的振荡器频率变化温度补偿的自动电路和方法
公开(公告)号：US07371005B1
公开(公告)日：2008-05-13
申请号：US11818387
申请日：2007-06-14
申请人： Bhupendra K. Ahuja , Hoa Vu , Teck-Boon Serm
发明人： Bhupendra K. Ahuja , Hoa Vu , Teck-Boon Serm
IPC分类号： G04B17/20 , H03L1/00
CPC分类号： G04F5/06 , H03L1/02 , H03L1/022 , H03L1/027 , H03L1/028
摘要： An automatic temperature compensated real-time clock (RTC) chip includes a clock portion having a crystal oscillator block including crystal compensation circuitry adapted to be coupled to a crystal. The crystal compensation circuitry includes a non-linear capacitor DAC including a plurality of load capacitors, wherein the load capacitors have respective switches which switch respective ones of the load capacitors to change a parallel resonance frequency (fp) generated by the oscillator block. The capacitor DAC is arranged so that Analog Trimming (ATR) bits received cause an arrangement of the switches to provide a non-linear change in overall load capacitance to result in a linear relationship between fp and the ATR bits. A temperature sensor block is coupled to the crystal for measuring a temperature of at least the crystal. An A/D converter is coupled to the temperature sensor for outputting a digital temperature signal representative of the temperature of the crystal. A DSP engine receives the digital temperature signal and calculates frequency correction needed to correct for frequency inaccuracy and determines a bit sequence including the ATR bits appropriate to achieve the frequency correction.
摘要翻译：自动温度补偿实时时钟（RTC）芯片包括具有晶体振荡器模块的时钟部分，该晶体振荡器模块包括适于耦合到晶体的晶体补偿电路。晶体补偿电路包括包括多个负载电容器的非线性电容器DAC，其中负载电容器具有切换各个负载电容器的相应开关，以改变由振荡器模块产生的并联谐振频率（fp）。电容器DAC被布置成使得接收的模拟微调（ATR）位导致开关的布置，以提供总负载电容的非线性变化，从而导致fp与ATR位之间的线性关系。温度传感器模块耦合到晶体以测量至少晶体的温度。 A / D转换器耦合到温度传感器，用于输出代表晶体温度的数字温度信号。 DSP引擎接收数字温度信号并计算校正频率不准确所需的频率校正，并确定包括适合于实现频率校正的ATR位的比特序列。

7. 再颁专利

USRE43236E1 Automatic circuit and method for temperature compensation of oscillator frequency variation over temperature for a real time clock chip 有权
标题翻译：用于实时时钟芯片的振荡器频率变化温度补偿的自动电路和方法
公开(公告)号：USRE43236E1
公开(公告)日：2012-03-13
申请号：US12779885
申请日：2010-05-13
申请人： Hoa Vu , Teck-Boon Serm , Bhupendra K. Ahuja
发明人： Hoa Vu , Teck-Boon Serm , Bhupendra K. Ahuja
IPC分类号： G04B17/20 , H03L1/00
CPC分类号： G04F5/06 , H03L1/02 , H03L1/022 , H03L1/027 , H03L1/028
摘要： An automatic temperature compensated real-time clock (RTC) chip includes a clock portion having a crystal oscillator block including crystal compensation circuitry adapted to be coupled to a crystal. The crystal compensation circuitry includes a non-linear capacitor DAC including a plurality of load capacitors, wherein the load capacitors have respective switches which switch respective ones of the load capacitors to change a parallel resonance frequency (fp) generated by the oscillator block. The capacitor DAC is arranged so that Analog Trimming (ATR) bits received cause an arrangement of the switches to provide a non-linear change in overall load capacitance to result in a linear relationship between fp and the ATR bits. A temperature sensor block is coupled to the crystal for measuring a temperature of at least the crystal. An A/D converter is coupled to the temperature sensor for outputting a digital temperature signal representative of the temperature of the crystal. A DSP engine receives the digital temperature signal and calculates frequency correction needed to correct for frequency inaccuracy and determines a bit sequence including the ATR bits appropriate to achieve the frequency correction.
摘要翻译：自动温度补偿实时时钟（RTC）芯片包括具有晶体振荡器模块的时钟部分，该晶体振荡器模块包括适于耦合到晶体的晶体补偿电路。晶体补偿电路包括包括多个负载电容器的非线性电容器DAC，其中负载电容器具有切换各个负载电容器的相应开关，以改变由振荡器模块产生的并联谐振频率（fp）。电容器DAC被布置成使得接收的模拟微调（ATR）位导致开关的布置，以提供总负载电容的非线性变化，从而导致fp与ATR位之间的线性关系。温度传感器模块耦合到晶体以测量至少晶体的温度。 A / D转换器耦合到温度传感器，用于输出代表晶体温度的数字温度信号。 DSP引擎接收数字温度信号并计算校正频率不准确所需的频率校正，并确定包括适合于实现频率校正的ATR位的比特序列。

8. 发明申请

US20080117722A1 AUTOMATIC CIRCUIT AND METHOD FOR TEMPERATURE COMPENSATION OF OSCILLATOR FREQUENCY VARIATION OVER TEMPERATURE FOR A REAL TIME CLOCK CHIP 有权
标题翻译：用于实时时钟芯片的振荡器频率变化温度补偿的自动电路和方法
公开(公告)号：US20080117722A1
公开(公告)日：2008-05-22
申请号：US11818387
申请日：2007-06-14
申请人： Bhupendra K. Ahuja , Hoa Vu , Teck-Boon Serm
发明人： Bhupendra K. Ahuja , Hoa Vu , Teck-Boon Serm
IPC分类号： G04G3/02 , G04G3/00 , G04G5/00
CPC分类号： G04F5/06 , H03L1/02 , H03L1/022 , H03L1/027 , H03L1/028
摘要： An automatic temperature compensated real-time clock (RTC) chip includes a clock portion having a crystal oscillator block including crystal compensation circuitry adapted to be coupled to a crystal. The crystal compensation circuitry includes a non-linear capacitor DAC including a plurality of load capacitors, wherein the load capacitors have respective switches which switch respective ones of the load capacitors to change a parallel resonance frequency (fp) generated by the oscillator block. The capacitor DAC is arranged so that Analog Trimming (ATR) bits received cause an arrangement of the switches to provide a non-linear change in overall load capacitance to result in a linear relationship between fp and the ATR bits. A temperature sensor block is coupled to the crystal for measuring a temperature of at least the crystal. An A/D converter is coupled to the temperature sensor for outputting a digital temperature signal representative of the temperature of the crystal. A DSP engine receives the digital temperature signal and calculates frequency correction needed to correct for frequency inaccuracy and determines a bit sequence including the ATR bits appropriate to achieve the frequency correction.
摘要翻译：自动温度补偿实时时钟（RTC）芯片包括具有晶体振荡器模块的时钟部分，该晶体振荡器模块包括适于耦合到晶体的晶体补偿电路。晶体补偿电路包括包括多个负载电容器的非线性电容器DAC，其中负载电容器具有切换各个负载电容器的相应开关，以改变由振荡器模块产生的并联谐振频率（fp）。电容器DAC被布置成使得接收的模拟微调（ATR）位导致开关的布置，以提供总负载电容的非线性变化，从而导致fp与ATR位之间的线性关系。温度传感器模块耦合到晶体以测量至少晶体的温度。 A / D转换器耦合到温度传感器，用于输出代表晶体温度的数字温度信号。 DSP引擎接收数字温度信号并计算校正频率不准确所需的频率校正，并确定包括适合于实现频率校正的ATR位的比特序列。

9. 发明授权

US5586306A Integrated circuit servo system control for computer mass storage device with distributed control functionality to reduce transport delay 失效
标题翻译：用于具有分布式控制功能的计算机大容量存储设备的集成电路伺服系统控制，以减少传输
公开(公告)号：US5586306A
公开(公告)日：1996-12-17
申请号：US448098
申请日：1995-05-23
申请人： Paul M. Romano , Larry D. King , John S. Geldman , Bhupendra K. Ahuja , Palaksha Setty , Petro Estakhri , Son Ho , Phuc Tran , Maryam Imam
发明人： Paul M. Romano , Larry D. King , John S. Geldman , Bhupendra K. Ahuja , Palaksha Setty , Petro Estakhri , Son Ho , Phuc Tran , Maryam Imam
IPC分类号： G11B5/55 , G11B5/596 , G11B19/02 , G11B19/12 , G11B19/20 , G11B19/28 , G11B20/10 , G11B21/08 , G11B21/10 , G11B27/30 , G11B33/10 , G06F3/00
CPC分类号： G11B27/3027 , G11B19/02 , G11B19/12 , G11B19/20 , G11B19/28 , G11B20/10 , G11B21/083 , G11B21/106 , G11B5/5526 , G11B5/59605 , G11B5/59655 , G11B33/10
摘要： An integrated circuit controls the low level, electromechanical functionality of a computer mass storage device, such as a magnetic disk drive incorporating a spindle motor for rotatably controlling a disk and an actuator for positioning at least one read/write head with respect to the disk, to read or write encoded data configured in information data sectors and to sense encoded data of servo data sectors. A servo subsystem is coupled to an output of the read/write head for detecting the servo data sectors and providing a control signal in response thereto. An analog-to-digital subsystem is also coupled to an output of the read/write head and is operative in response to the servo subsystem control signal for converting the encoded data of the servo data sectors to digital transducer position information representative of a position of the read/write head with respect to the data tracks. A data processing subsystem is coupled to the analog-to-digital subsystem for processing the digital transducer position information and providing digital motion control signals in response thereto. A digital-to-analog subsystem is coupled to the data processing subsystem for providing analog control signals to the spindle motor and the actuator in response to the digital motion control signals.
摘要翻译：集成电路控制计算机大容量存储装置的低级机电功能，例如包括用于可旋转地控制盘的主轴电机的磁盘驱动器和用于相对于盘定位至少一个读/写头的致动器，读取或写入配置在信息数据扇区中的编码数据，并读取伺服数据扇区的编码数据。伺服子系统耦合到读/写头的输出端，用于检测伺服数据扇区并提供响应于此的控制信号。模拟数字子系统还耦合到读/写头的输出端，并响应于伺服子系统控制信号操作，用于将伺服数据扇区的编码数据转换为数字换能器位置信息，该位置信息表示相对于数据轨道的读/写头。数据处理子系统耦合到模数 - 数字子系统，用于处理数字换能器位置信息并响应于此提供数字运动控制信号。数字到模拟子系统耦合到数据处理子系统，用于响应于数字运动控制信号向主轴电动机和致动器提供模拟控制信号。

10. 发明授权

US06281747B1 Power efficient line driver 有权
公开(公告)号：US06281747B1
公开(公告)日：2001-08-28
申请号：US09769234
申请日：2001-01-24
申请人： Bhupendra K. Ahuja , Cary L. Delano , Adya S. Tripathi
发明人： Bhupendra K. Ahuja , Cary L. Delano , Adya S. Tripathi
IPC分类号： H03F136
摘要： A signal processing circuit is described including a frequency selective network in a feedback loop. An analog-to-analog converter in the feedback loop is coupled to the frequency selective network. A continuous-time feedback path provides feedback from the output terminal of the analog-to-analog converter to the frequency selective network.

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