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1. 发明授权

US4442529A Power supply rejection characteristics of CMOS circuits 失效
标题翻译： CMOS电路的电源抑制特性
公开(公告)号：US4442529A
公开(公告)日：1984-04-10
申请号：US231478
申请日：1981-02-04
申请人： Bhupendra K. Ahuja , Mirmira R. Dwarakanath
发明人： Bhupendra K. Ahuja , Mirmira R. Dwarakanath
IPC分类号： H01L27/092 , G05F1/46 , H01L21/8238 , H01L27/02 , H01L29/78 , H01L27/04 , H04L3/00
CPC分类号： H01L27/0218 , G05F1/467
摘要： In a conventional CMOS integrated circuit such as a switched capacitor filter, power supply noise signals are coupled from the substrate to high impedance nodes via various parasitic capacitances. To minimize these noise signals and thereby improve the power supply rejection ratio of the circuit, only N-channel transistors are coupled to the nodes. Additionally, the P-tubs of these transistors are connected to an on-chip regulated power supply. Moreover, for certain metallic runners and capacitors of the circuit that are connected to the specified nodes and parasitically coupled to the substrate, grounded P-tubs are formed directly under the runners and capacitors.
摘要翻译：在诸如开关电容滤波器的常规CMOS集成电路中，电源噪声信号通过各种寄生电容从衬底耦合到高阻抗节点。为了最小化这些噪声信号，从而提高电路的电源抑制比，只有N沟道晶体管耦合到节点。此外，这些晶体管的P型桶连接到片上稳压电源。此外，对于连接到指定节点并寄生耦合到基板的电路的某些金属流道和电容器，接地的P型桶形成在流道和电容器的正下方。

2. 发明授权

US4322687A Operational amplifier with improved offset correction 失效
标题翻译：具有改进的偏移校正的运算放大器
公开(公告)号：US4322687A
公开(公告)日：1982-03-30
申请号：US151534
申请日：1980-05-19
申请人： Mirmira R. Dwarakanath , Douglas G. Marsh
发明人： Mirmira R. Dwarakanath , Douglas G. Marsh
IPC分类号： H03F1/30 , H03F1/34
CPC分类号： H03F1/303
摘要： Improved input offset voltage compensation of an amplifier (12) is achieved through the use of a servo loop which is added to electronic switch and capacitor offset compensation circuitry disposed in the input (14) and feedback (20) paths of the amplifier. A voltage approximately equal to the offset voltage is stored on a feedback capacitor (24) by operation of input reset (34), feedback shunt (22) and feedback reset (26) switches. An error correction voltage is then generated within the servo loop (40) to adjust for the residual offset produced by the operation of the input reset and feedback shunt switches as well as the finite gain of the amplifier.
摘要翻译：放大器（12）的改进的输入失调电压补偿通过使用一个伺服回路来实现，伺服回路被加到设置在放大器的输入（14）和反馈（20）路径中的电子开关和电容器偏移补偿电路上。通过输入复位（34），反馈分路（22）和反馈复位（26）开关的操作，大约等于偏移电压的电压被存储在反馈电容器（24）上。然后在伺服环路（40）内产生误差校正电压，以调整由输入复位和反馈分流开关的操作产生的残余偏移以及放大器的有限增益。

3. 发明授权

US4306196A Operational amplifier with offset compensation 失效
标题翻译：带补偿补偿的运算放大器
公开(公告)号：US4306196A
公开(公告)日：1981-12-15
申请号：US111997
申请日：1980-01-14
申请人： Mirmira R. Dwarakanath , Douglas G. Marsh
发明人： Mirmira R. Dwarakanath , Douglas G. Marsh
IPC分类号： H03F3/34 , H03F1/30 , H03F3/347 , H03M1/10 , H03F1/02
CPC分类号： H03F1/303
摘要： Offset voltage compensation is provided by a feedback capacitor (24) in a feedback loop (20). For periodically resetting the compensation, the signal input terminal (14) is grounded by an electronic MOSFET switch (34). Other such switches (22, 26) close the feedback loop (20) in front of the capacitor (24) and connect the output side of the capacitor (24) to ground for recharging. An input capacitor (30) for compensating the switching feed-through charge of the feedback loop switch (22) is connected between the input signal source (32) and the signal input terminal (14). The ratio of the inherent capacitances of the switches (22, 34) is equal to the capacitance ratio of their respective capacitors (24, 30). Also disclosed is a particularly advantageous method for operating the switches. For switching from the reset condition back to the transmit condition, first the feedback loop switch (22) is opened. Thereafter, the other switches (26, 31, 34) are operated.
摘要翻译：偏置电压补偿由反馈回路（20）中的反馈电容器（24）提供。为了周期性地复位补偿，信号输入端子（14）由电子MOSFET开关（34）接地。其他这样的开关（22,26）关闭电容器（24）前面的反馈回路（20），并将电容器（24）的输出侧连接到地面以进行再充电。用于补偿反馈环路开关（22）的开关馈通电荷的输入电容器（30）连接在输入信号源（32）和信号输入端子（14）之间。开关（22,34）的固有电容的比例等于它们各自的电容器（24,30）的电容比。还公开了用于操作开关的特别有利的方法。为了从复位状态切换回发送状态，首先打开反馈回路开关（22）。此后，其他开关（26,31,34）被操作。

4. 发明授权

US4495472A Stable fast-settling voltage reference buffer amplifier 失效
标题翻译：稳定的快速稳定电压基准缓冲放大器
公开(公告)号：US4495472A
公开(公告)日：1985-01-22
申请号：US443194
申请日：1982-11-22
申请人： Mirmira R. Dwarakanath
发明人： Mirmira R. Dwarakanath
IPC分类号： H03F3/345 , H03F3/16
CPC分类号： H03F3/345
摘要： In a feedback-type buffer amplifier designed to be interposed between a reference voltage source and a capacitive load, the output of the amplifier is applied to each of two precisely matched or scaled source follower circuits. The voltages appearing at respective output nodes of the source follower circuits are designed to be identical to each other. But, significantly, the nodes are decoupled from each other. One output node is included in the feedback path of the buffer amplifier, whereas the other node constitutes the output terminal of the composite arrangement. Perturbations or phase shifts due to the load are thus effectively decoupled from the feedback path of the amplifier. A fast-settling stable overall configuration is thereby provided.
摘要翻译：在设计为插入参考电压源和电容性负载之间的反馈型缓冲放大器中，放大器的输出被施加到两个精确匹配或定标的源极跟随器电路中的每一个。出现在源极跟随器电路的各个输出节点处的电压被设计为彼此相同。但是，显着地说，这些节点是相互分离的。一个输出节点包括在缓冲放大器的反馈路径中，而另一个节点构成复合布置的输出端。因此，由于负载引起的扰动或相移有效地与放大器的反馈路径去耦合。从而提供快速稳定的整体结构。

5. 发明授权

US4404544A .mu.-Law/A-law PCM CODEC 失效
标题翻译： mu -Law / A-law PCM编解码器
公开(公告)号：US4404544A
公开(公告)日：1983-09-13
申请号：US252600
申请日：1981-04-09
申请人： Mirmira R. Dwarakanath
发明人： Mirmira R. Dwarakanath
IPC分类号： H03M1/74 , H03M1/00 , H04B14/04 , H03K13/02 , H03K13/08
CPC分类号： H03M1/02
摘要： In a PCM CODEC, a binary-weighted charge redistribution capacitor array is designed to be configured for either .mu.-law or A-law coding. Selection of one or the other coding configuration is achieved by controlling a single gate circuit. A unique cascaded switch arrangement ensures that when selected capacitors representative of a specified coding segment are connected to a reference voltage source, the next successive capacitor of the array is automatically connected to a variable source that provides a voltage representative of a step within the specified segment.
摘要翻译：在PCM编解码器中，二进制加权电荷再分配电容器阵列被设计为配置为μ-或A律编码。通过控制单个门电路来实现一个或另一个编码配置的选择。唯一的级联开关布置确保当代表指定编码段的选定电容器连接到参考电压源时，阵列的下一个连续电容器自动连接到可提供表示指定段内的步长的电压的可变源。

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