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1. 发明申请

US20100148277A1 ISOLATED METAL PLUG PROCESS FOR USE IN FABRICATING CARBON NANOTUBE MEMORY CELLS 失效
标题翻译：用于制备碳纳米管存储器细胞的隔离金属压片方法
公开(公告)号：US20100148277A1
公开(公告)日：2010-06-17
申请号：US12710477
申请日：2010-02-23
申请人： Richard J. Carter , Peter A. Burke , Verne C. Hornback , Thomas Rueckes , Claude L. Bertin
发明人： Richard J. Carter , Peter A. Burke , Verne C. Hornback , Thomas Rueckes , Claude L. Bertin
IPC分类号： H01L27/112
CPC分类号： H01H1/0094 , Y10S977/724 , Y10S977/732 , Y10S977/943
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.
摘要翻译：本发明涉及制造具有纳米管横杆元件的机电存储器单元的结构和方法。这种存储单元包括具有与晶体管电接触的接触的晶体管的衬底。第一支撑层形成在衬底上，其开口限定了电触点上方的下腔室。纳米管横杆元件布置成跨越下室。第二支撑层形成有开口，所述开口限定在所述下腔室上方的顶部腔室，所述顶部腔室包括延伸超出所述下部腔室的边缘以暴露所述第一支撑层的顶部表面的一部分的延伸区域。屋顶层覆盖顶部室的顶部，并且包括露出顶部室的延伸区域的一部分并且包括延伸到顶部层中的孔中以密封顶部和底部室的插塞的孔。存储单元还包括覆盖在横杆元件上的电极，使得电信号可以激活电极以吸引或排斥交叉开关元件以设置晶体管的存储状态。

2. 发明授权

US07884430B2 Isolated metal plug process for use in fabricating carbon nanotube memory cells 失效
标题翻译：用于制造碳纳米管记忆单元的隔离金属塞工艺
公开(公告)号：US07884430B2
公开(公告)日：2011-02-08
申请号：US12710477
申请日：2010-02-23
申请人： Richard J. Carter , Peter A. Burke , Verne C. Hornback , Thomas Rueckes , Claude L. Bertin
发明人： Richard J. Carter , Peter A. Burke , Verne C. Hornback , Thomas Rueckes , Claude L. Bertin
IPC分类号： H01L29/84
CPC分类号： H01H1/0094 , Y10S977/724 , Y10S977/732 , Y10S977/943
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.
摘要翻译：本发明涉及制造具有纳米管横杆元件的机电存储器单元的结构和方法。这种存储单元包括具有与晶体管电接触的接触的晶体管的衬底。第一支撑层形成在衬底上，其开口限定了电触点上方的下腔室。纳米管横杆元件布置成跨越下室。第二支撑层形成有开口，所述开口限定在所述下腔室上方的顶部腔室，所述顶部腔室包括延伸超出所述下部腔室的边缘以暴露所述第一支撑层的顶部表面的一部分的延伸区域。屋顶层覆盖顶部室的顶部，并且包括露出顶部室的延伸区域的一部分并且包括延伸到顶部层中的孔中以密封顶部和底部室的插塞的孔。存储单元还包括覆盖在横杆元件上的电极，使得电信号可以激活电极以吸引或排斥交叉开关元件以设置晶体管的存储状态。

3. 发明授权

US07824946B1 Isolated metal plug process for use in fabricating carbon nanotube memory cells 有权
标题翻译：用于制造碳纳米管记忆单元的隔离金属塞工艺
公开(公告)号：US07824946B1
公开(公告)日：2010-11-02
申请号：US11429069
申请日：2006-05-05
申请人： Richard J. Carter , Peter A. Burke , Verne C. Hornback , Claude L. Bertin , Thomas Rueckes
发明人： Richard J. Carter , Peter A. Burke , Verne C. Hornback , Claude L. Bertin , Thomas Rueckes
IPC分类号： H01L21/00 , H01L21/64
CPC分类号： H01H1/0094 , Y10S977/724 , Y10S977/732 , Y10S977/943
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.
摘要翻译：本发明涉及制造具有纳米管横杆元件的机电存储器单元的结构和方法。这种存储单元包括具有与晶体管电接触的接触的晶体管的衬底。第一支撑层形成在衬底上，其开口限定了电触点上方的下腔室。纳米管横杆元件布置成跨越下室。第二支撑层形成有开口，所述开口限定在所述下腔室上方的顶部腔室，所述顶部腔室包括延伸超出所述下部腔室的边缘以暴露所述第一支撑层的顶部表面的一部分的延伸区域。屋顶层覆盖顶部室的顶部，并且包括露出顶部室的延伸区域的一部分并且包括延伸到顶部层中的孔中以密封顶部和底部室的插塞的孔。存储单元还包括覆盖在横杆元件上的电极，使得电信号可以激活电极以吸引或排斥交叉开关元件以设置晶体管的存储状态。

4. 发明授权

US07666701B1 Isolated metal plug process for use in fabricating carbon nanotube memory cells 有权
公开(公告)号：US07666701B1
公开(公告)日：2010-02-23
申请号：US11429069
申请日：2006-05-05
申请人： Richard J. Carter , Peter A. Burke , Verne C. Hornback
发明人： Richard J. Carter , Peter A. Burke , Verne C. Hornback
IPC分类号： H01L21/00 , H01L21/64
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.

5. 发明授权

US07928521B1 Non-tensioned carbon nanotube switch design and process for making same 有权
标题翻译：非张力碳纳米管开关的设计与制造过程
公开(公告)号：US07928521B1
公开(公告)日：2011-04-19
申请号：US11142725
申请日：2005-05-31
申请人： Peter A. Burke , Thomas Rueckes , Claude L. Bertin
发明人： Peter A. Burke , Thomas Rueckes , Claude L. Bertin
IPC分类号： H01L29/82
CPC分类号： H01H1/0094 , B82Y10/00 , H01H59/0009 , H01H2001/0042 , H01H2059/0045 , H01L51/0048 , H01L51/0591 , Y10S977/932
摘要： The invention comprises a carbon nanotube switch suitable for use in an integrated circuit structure and capable of being moved from a first position in a first plane in the switch to a second position in a second plane in the switch using approximately the same energy as required to move the switch from the second position back to the first position. The switch comprises a flexible carbon nanotube strip secured clamped at one end in a first plane in a switching chamber, and secured or clamped, at the opposite end of the carbon nanotube, in a second plane in the switching chamber, which is parallel to the first plane but spaced therefrom, to permit the central portion of the carbon nanotube strip to move in the chamber between a first position in the first plane and in electrical contact with one or more first electrodes and a second position in the second plane and in electrical contact with one or more second electrodes.
摘要翻译：本发明包括一种适用于集成电路结构的碳纳米管开关，其能够使用开关中的第一平面中的第一位置移动到开关中的第二平面中的第二位置，使用大约相同的能量将开关从第二个位置移回到第一个位置。开关包括柔性碳纳米管条，其固定在切换室中的第一平面中的一端处夹持，并且在碳纳米管的相对端处固定或夹紧在开关室中的平行于第二平面的第二平面中第一平面但与其间隔开，以允许碳纳米管条的中心部分在室中在第一平面中的第一位置和与一个或多个第一电极电连接并且在第二平面中的第二位置和电气与一个或多个第二电极接触。

6. 发明授权

US07915122B2 Self-aligned cell integration scheme 失效
标题翻译：自对准单元集成方案
公开(公告)号：US07915122B2
公开(公告)日：2011-03-29
申请号：US11312849
申请日：2005-12-20
申请人： Richard J. Carter , Hemanshu D. Bhatt , Shiqun Gu , Peter A. Burke , James R. B. Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
发明人： Richard J. Carter , Hemanshu D. Bhatt , Shiqun Gu , Peter A. Burke , James R. B. Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
IPC分类号： H01L21/336
CPC分类号： H01L51/0018 , B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0545 , Y10S977/742
摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.
摘要翻译：一种形成自对准逻辑单元的方法。在底部电极上形成纳米管层。在纳米管层上形成夹层。夹层覆盖纳米管层，从而保护纳米管层。在钳位层上形成电介质层。蚀刻介电层。钳位层提供蚀刻停止并保护纳米管层。用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。在纳米管层上形成间隔层。除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层，和纳米管层。

7. 发明授权

US07402770B2 Nano structure electrode design 有权
标题翻译：纳米结构电极设计
公开(公告)号：US07402770B2
公开(公告)日：2008-07-22
申请号：US11270104
申请日：2005-11-09
申请人： Sey-Shing Sun , Hemanshu D. Bhatt , Peter A. Burke , Richard J. Carter
发明人： Sey-Shing Sun , Hemanshu D. Bhatt , Peter A. Burke , Richard J. Carter
IPC分类号： H01H9/00 , G11C11/50 , H01L21/00 , H01L23/58
CPC分类号： G11C13/025 , B82Y10/00 , H01L51/0048 , H01L51/0595 , Y10S977/724
摘要： A microelectronic switch having a substrate layer, an electrically conductive switching layer formed on the substrate layer, an electrically conductive cavity layer formed on the switching layer, an electrically conductive cap layer formed on the cavity layer, the cap layer forming a first electrode and a second electrode that are physically and electrically separated one from another, and which both at least partially overlie the switching layer, and a cavity disposed between the switching layer and the second electrode, where the switching is layer is flexible to make electrical contact with the second electrode by flexing through the cavity upon selective application of an electrical bias.
摘要翻译：具有衬底层的微电子开关，形成在衬底层上的导电开关层，形成在开关层上的导电腔层，形成在腔层上的导电帽层，形成第一电极的帽层和第二电极在物理上和电气上彼此分离，并且至少部分地覆盖在开关层上，并且设置在开关层和第二电极之间的空腔，其中开关层是柔性的，以与第二电极电接触电极通过在选择性地施加电偏压时通过空腔弯曲。

8. 发明授权

US08552535B2 Trench shielding structure for semiconductor device and method 有权
标题翻译：半导体器件的沟槽屏蔽结构及方法
公开(公告)号：US08552535B2
公开(公告)日：2013-10-08
申请号：US12271068
申请日：2008-11-14
申请人： Peter A. Burke , Brian Pratt , Prasad Venkatraman
发明人： Peter A. Burke , Brian Pratt , Prasad Venkatraman
IPC分类号： H01L29/66
CPC分类号： H01L29/4236 , H01L29/0696 , H01L29/401 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4925 , H01L29/4933 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner.
摘要翻译：用于半导体器件的屏蔽结构包括多个沟槽。沟槽包括形成在其中的钝化衬垫和屏蔽电极。在一个实施例中，屏蔽结构位于控制板下方。在另一个实施例中，屏蔽结构放置在控制转轮下方。

9. 发明授权

US08410578B2 Method of manufacturing a semiconductor component and structure 有权
标题翻译：制造半导体元件和结构的方法
公开(公告)号：US08410578B2
公开(公告)日：2013-04-02
申请号：US12962579
申请日：2010-12-07
申请人： Sallie Hose , Peter A. Burke , Li Jiang , Sudhama C. Shastri
发明人： Sallie Hose , Peter A. Burke , Li Jiang , Sudhama C. Shastri
IPC分类号： H01L29/94 , H01L21/02 , H01L21/768
CPC分类号： H01L23/5227 , H01L23/5223 , H01L23/5228 , H01L23/53238 , H01L24/05 , H01L27/0629 , H01L28/10 , H01L28/24 , H01L28/40 , H01L2224/05624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/12035 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/19041 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor component and methods for manufacturing the semiconductor component that includes a monolithically integrated passive device. In accordance with embodiments, the monolithically integrated passive device includes an inductor formed from damascene structures.
摘要翻译：一种半导体元件及其制造方法，该半导体元件包括单片集成无源器件。根据实施例，单片集成无源器件包括由镶嵌结构形成的电感器。

10. 发明申请

US20120326227A1 METHOD OF MAKING AN INSULATED GATE SEMICONDUCTOR DEVICE AND STRUCTURE 有权
标题翻译：制造绝缘栅半导体器件和结构的方法
公开(公告)号：US20120326227A1
公开(公告)日：2012-12-27
申请号：US13170033
申请日：2011-06-27
申请人： Peter A. Burke , Gordon M. Grivna , Balaji Padmanabhan , Prasad Venkatraman
发明人： Peter A. Burke , Gordon M. Grivna , Balaji Padmanabhan , Prasad Venkatraman
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/4933 , H01L29/66348 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7827
摘要： In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers. Before the shield electrode is formed, spacer layers can be used form shield insulating layers along portions of the trench structure. The shield insulating layers are thicker than the gate insulating layers. In another embodiment, the shield insulating layers have variable thickness.
摘要翻译：在一个实施例中，垂直绝缘栅场效应晶体管包括形成在半导体材料内的沟槽结构中的屏蔽电极。栅电极使用栅极绝缘层与半导体材料隔离。在形成屏蔽电极之前，间隔层可以沿沟槽结构的部分形成屏蔽绝缘层。屏蔽绝缘层比栅极绝缘层厚。在另一个实施例中，屏蔽绝缘层具有可变的厚度。

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