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1. 发明授权

US09048214B2 Bidirectional field effect transistor and method 有权
标题翻译：双向场效应晶体管及方法
公开(公告)号：US09048214B2
公开(公告)日：2015-06-02
申请号：US13590947
申请日：2012-08-21
申请人： Balaji Padmanabhan , Prasad Venkatraman
发明人： Balaji Padmanabhan , Prasad Venkatraman
IPC分类号： H01L29/66 , H01L29/40 , H01L29/78 , H01L29/423
CPC分类号： H01L29/7813 , H01L29/404 , H01L29/407 , H01L29/42368 , H01L29/66734
摘要： In one embodiment, a structure for a semiconductor device has trench shield electrodes formed above and below a gate electrode. The structure can be configured to function as a bidirectional power field effect transistor.
摘要翻译：在一个实施例中，半导体器件的结构具有形成在栅极电极上方和下方的沟槽屏蔽电极。该结构可以被配置为用作双向功率场效应晶体管。

2. 发明申请

US20140084363A1 MOS TRANSISTOR STRUCTURE 有权
标题翻译： MOS晶体管结构
公开(公告)号：US20140084363A1
公开(公告)日：2014-03-27
申请号：US13627912
申请日：2012-09-26
申请人： Jeffrey Pearse , Prasad Venkatraman , James Sellers , Hemanshu D. Bhatt
发明人： Jeffrey Pearse , Prasad Venkatraman , James Sellers , Hemanshu D. Bhatt
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42372 , H01L29/4238 , H01L29/4933 , H01L29/66734 , H01L29/7811
摘要： In one embodiment, an MOS transistor is formed to have an active region and a termination region. Within the termination region a plurality of conductors are formed to make electrical contact to conductors that are within a plurality of trenches. The plurality of conductors in the termination region are formed to be substantially coplanar.
摘要翻译：在一个实施例中，MOS晶体管形成为具有有源区和端接区。在终止区域内，形成多个导体以与多个沟槽内的导体电接触。终端区域中的多个导体形成为基本共面。

3. 发明授权

US08647970B2 Electronic device comprising conductive structures and an insulating layer between the conductive structures and within a trench 有权
标题翻译：电子器件包括导电结构和在导电结构之间和沟槽内的绝缘层
公开(公告)号：US08647970B2
公开(公告)日：2014-02-11
申请号：US13327390
申请日：2011-12-15
申请人： Gary H. Loechelt , Prasad Venkatraman
发明人： Gary H. Loechelt , Prasad Venkatraman
IPC分类号： H01L21/425
CPC分类号： H01L29/41741 , H01L29/1095 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/42376 , H01L29/456 , H01L29/4933 , H01L29/66659 , H01L29/66689 , H01L29/66696 , H01L29/7816 , H01L29/7827 , H01L29/7835
摘要： An electronic device can include a substrate including an underlying doped region and a semiconductor layer overlying the substrate. A trench can have a sidewall and extend at least partly through the semiconductor layer. The electronic device can further include a first conductive structure adjacent to the underlying doped region, an insulating layer, and a second conductive structure within the trench. The insulating layer can be disposed between the first and second conductive structures, and the first conductive structure can be disposed between the insulating layer and the underlying doped region. Processes of forming the electronic device may be performed such that the first conductive structure includes a conductive fill material or a doped region within the semiconductor layer. The first conductive structure can allow the underlying doped region to be farther from the channel region and allow RDSON to be lower for a given BVDSS.
摘要翻译：电子器件可以包括包括下面的掺杂区域和覆盖衬底的半导体层的衬底。沟槽可以具有侧壁并且至少部分地延伸穿过半导体层。电子器件还可以包括邻近下面的掺杂区域的第一导电结构，绝缘层和沟槽内的第二导电结构。绝缘层可以设置在第一和第二导电结构之间，并且第一导电结构可以设置在绝缘层和下面的掺杂区域之间。可以执行形成电子器件的工艺，使得第一导电结构包括导电填充材料或半导体层内的掺杂区域。第一导电结构可以允许下面的掺杂区域离沟道区域更远，并允许给定BVDSS的RDSON较低。

4. 发明申请

US20130221428A1 PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN 有权
标题翻译：形成电子装置的方法，包括TRENCH和导电结构
公开(公告)号：US20130221428A1
公开(公告)日：2013-08-29
申请号：US13404855
申请日：2012-02-24
申请人： Prasad Venkatraman , Balaji Padmanabhan
发明人： Prasad Venkatraman , Balaji Padmanabhan
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336
CPC分类号： H01L29/7827 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L29/7813
摘要： An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface, wherein the patterned semiconductor layer defines a first trench and a second trench that extend from the primary surface towards the substrate. The electronic device can further include a first conductive electrode and a gate electrode within the first trench. The electronic device can still further include a second conductive electrode within the second trench. The electronic device can include a source region within the patterned semiconductor layer and disposed between the first and second trenches. The electronic device can further include a body contact region within the patterned semiconductor layer and between the first and second trenches, wherein the body contact region is spaced apart from the primary surface. Processes of forming the electronic device can take advantage of forming all trenches during processing sequence.
摘要翻译：电子器件可以包括晶体管结构，其包括覆盖在衬底上并具有主表面的图案化半导体层，其中图案化的半导体层限定从主表面朝向衬底延伸的第一沟槽和第二沟槽。电子器件还可以包括在第一沟槽内的第一导电电极和栅电极。电子器件还可以在第二沟槽内进一步包括第二导电电极。电子器件可以包括图案化半导体层内的源极区域，并且设置在第一和第二沟槽之间。电子器件还可以包括在图案化的半导体层内以及在第一和第二沟槽之间的体接触区域，其中主体接触区域与主表面间隔开。形成电子器件的过程可以利用在处理序列期间形成所有沟槽的优点。

5. 发明申请

US20130153987A1 ELECTRONIC DEVICE COMPRISING A CONDUCTIVE STRUCTURE AND AN INSULATING LAYER WITHIN A TRENCH AND A PROCESS OF FORMING THE SAME 有权
标题翻译：包含导电结构的导体结构的电子器件和在其中的绝缘层及其形成方法
公开(公告)号：US20130153987A1
公开(公告)日：2013-06-20
申请号：US13327361
申请日：2011-12-15
申请人： Prasad Venkatraman , Gordon M. Grivna , Gary H. Loechelt
发明人： Prasad Venkatraman , Gordon M. Grivna , Gary H. Loechelt
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L21/2815 , H01L29/0634 , H01L29/407 , H01L29/41766 , H01L29/42376 , H01L29/66659 , H01L29/66689 , H01L29/66696 , H01L29/7816 , H01L29/7835
摘要： An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the thickness of semiconductor layer to a depth. The electronic device can further include a conductive structure within the trench, wherein the conductive structure extends at least approximately 50% of the depth of the trench. The electronic device can still further include a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the conductive structure; and an insulating layer disposed between the vertically-oriented doped region and the conductive structure. A process of forming an electronic device can include patterning a semiconductor layer to define a trench extending through at least approximately 50% of the thickness of the semiconductor layer and forming a vertically-oriented doped region after patterning the semiconductor layer to define the trench.
摘要翻译：电子器件可以包括覆盖衬底并具有主表面和厚度的半导体层，其中沟槽延伸穿过半导体层厚度的至少大约50％的深度。电子器件还可以包括在沟槽内的导电结构，其中导电结构延伸至沟槽深度的至少约50％。电子器件还可以进一步包括在半导体层内的垂直取向的掺杂区域，该掺杂区域与导电结构相邻并与导电结构电绝缘; 以及设置在垂直取向的掺杂区域和导电结构之间的绝缘层。形成电子器件的过程可以包括图案化半导体层以限定延伸穿过至少大约50％的半导体层的厚度的沟槽，并且在图案化半导体层以形成沟槽之后形成垂直取向的掺杂区域。

6. 发明授权

US08415739B2 Semiconductor component and method of manufacture 有权
标题翻译：半导体元件及制造方法
公开(公告)号：US08415739B2
公开(公告)日：2013-04-09
申请号：US12271106
申请日：2008-11-14
申请人： Prasad Venkatraman , Zia Hossain
发明人： Prasad Venkatraman , Zia Hossain
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0638 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/456 , H01L29/4933 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor component that includes an edge termination structure and a method of manufacturing the semiconductor component. A semiconductor material has a semiconductor device region and an edge termination region. One or more device trenches may be formed in the semiconductor device region and one or more termination trenches is formed in the edge termination region. A source electrode is formed in a portion of a termination trench adjacent its floor and a floating electrode termination structure is formed in the portion of the termination trench adjacent its mouth. A second termination trench may be formed in the edge termination region and a non-floating electrode may be formed in the second termination trench. Alternatively, the second termination trench may be omitted and a trench-less non-floating electrode may be formed in the edge termination region.
摘要翻译：一种包括边缘终端结构的半导体部件和制造半导体部件的方法。半导体材料具有半导体器件区域和边缘终止区域。一个或多个器件沟槽可以形成在半导体器件区域中，并且在边缘终止区域中形成一个或多个端接沟槽。源极电极形成在靠近其底板的终端沟槽的一部分中，并且在靠近其端口的端接沟槽的部分中形成浮动电极端接结构。可以在边缘终止区域中形成第二终止沟槽，并且可以在第二终端沟槽中形成非浮置电极。或者，可以省略第二终端沟槽，并且可以在边缘终止区域中形成无沟槽非浮动电极。

7. 发明授权

US08207035B2 Method of forming an integrated power device and structure 有权
标题翻译：形成集成电力装置和结构的方法
公开(公告)号：US08207035B2
公开(公告)日：2012-06-26
申请号：US12696816
申请日：2010-01-29
申请人： Francine Y. Robb , Stephen P. Robb , Prasad Venkatraman , Zia Hossain
发明人： Francine Y. Robb , Stephen P. Robb , Prasad Venkatraman , Zia Hossain
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/823487 , H01L21/823885 , H01L27/088 , H01L27/0922 , H01L29/0878 , H01L29/66734
摘要： In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.
摘要翻译：在一个实施例中，在具有其它晶体管的半导体衬底上形成垂直功率晶体管。垂直功率晶体管下面的半导体层的一部分被掺杂以为垂直功率晶体管提供低导通电阻。

8. 发明授权

US07939897B2 Method of forming a low resistance semiconductor contact and structure therefor 有权
标题翻译：形成低电阻半导体触点及其结构的方法
公开(公告)号：US07939897B2
公开(公告)日：2011-05-10
申请号：US12766601
申请日：2010-04-23
申请人： Gordon M. Grivna , Prasad Venkatraman
发明人： Gordon M. Grivna , Prasad Venkatraman
IPC分类号： H01L21/02
CPC分类号： H01L29/7802 , H01L21/2815 , H01L29/0615 , H01L29/086 , H01L29/0869 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727
摘要： In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides.
摘要翻译：在一个实施例中，硅化物层形成在两个相对掺杂的相邻半导体区域上。电导体材料与两个硅化物电接触地形成。

9. 发明申请

US20100237409A1 SEMICONDUCTOR COMPONENT 有权
标题翻译：半导体元件
公开(公告)号：US20100237409A1
公开(公告)日：2010-09-23
申请号：US12790987
申请日：2010-06-01
申请人： Prasad Venkatraman , Gordon M. Grivna , Francine Y. Robb , George Chang , Carroll Casteel
发明人： Prasad Venkatraman , Gordon M. Grivna , Francine Y. Robb , George Chang , Carroll Casteel
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.
摘要翻译：能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。提供具有P型导电性区域的N型导电性的半导体材料。在P型导电性区域形成N型导电性的掺杂区域。沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。场氧化物在源区的形成中用作注入掩模。主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。形成与半导体材料的背面接触的电导体。

10. 发明授权

US07736984B2 Method of forming a low resistance semiconductor contact and structure therefor 有权
标题翻译：形成低电阻半导体触点及其结构的方法
公开(公告)号：US07736984B2
公开(公告)日：2010-06-15
申请号：US11232757
申请日：2005-09-23
申请人： Gordon M. Grivna , Prasad Venkatraman
发明人： Gordon M. Grivna , Prasad Venkatraman
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L21/2815 , H01L29/0615 , H01L29/086 , H01L29/0869 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727
摘要： In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides.
摘要翻译：在一个实施例中，硅化物层形成在两个相对掺杂的相邻半导体区域上。电导体材料与两个硅化物电接触地形成。

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