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1. 发明授权

US07345507B1 Multi-product die configurable as two or more programmable integrated circuits of different logic capacities 有权
标题翻译：多产品管芯可配置为具有不同逻辑容量的两个或多个可编程集成电路
公开(公告)号：US07345507B1
公开(公告)日：2008-03-18
申请号：US11333991
申请日：2006-01-17
申请人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
发明人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
IPC分类号： H01L25/00
CPC分类号： H03K19/177
摘要： A multi-product integrated circuit die includes at least two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A selection code storage circuit stores a product selection code. A first value of the product selection code selects the option where both the first and second portions of the first die are operational. A second value of the product selection code selects the option where only the first portion of the first die is operational. The selection code storage circuit can include non-volatile memory or a fuse structure, or the product selection code can be configured as a package bonding option. The product selection code can also enable boundary scan for the operational portion of the die, and omit from the boundary scan chain any portions of the die that are deliberately rendered non-operational.
摘要翻译：多产品集成电路管芯包括至少两个不同的部分，其中至少一个部分可以以某种方式（例如，非功能的，不可访问的和/或不可编程的）被故意地变为不可操作的。选择码存储电路存储产品选择码。产品选择代码的第一个值选择第一模具的第一和第二部分都可操作的选项。产品选择代码的第二个值选择仅第一个模具的第一部分可操作的选项。选择代码存储电路可以包括非易失性存储器或熔丝结构，或者可以将产品选择代码配置为封装绑定选项。产品选择代码还可以为模具的操作部分启用边界扫描，并且从边界扫描链中省略故意使其不可操作的模具的任何部分。

2. 发明授权

US07491576B1 Yield-enhancing methods of providing a family of scaled integrated circuits 有权
标题翻译：提供一系列缩放集成电路的产量增强方法
公开(公告)号：US07491576B1
公开(公告)日：2009-02-17
申请号：US11333990
申请日：2006-01-17
申请人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
发明人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
IPC分类号： H01L21/66 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L22/22 , H01L23/544 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit die (e.g., a programmable logic device (PLD) die) is manufactured that has the capability of being configured as at least two differently-sized family members. The IC die is tested prior to packaging. If a first portion of the IC die is fully functional, but a second portion includes a localized defect, then the IC die is packaged with a product selection code that configures the IC die to operate as only the first portion of the die. The second portion of the die is deliberately rendered non-operational. Therefore, the IC die can still be sold as a fully functional packaged IC.
摘要翻译：制造集成电路管芯（例如，可编程逻辑器件（PLD）管芯），其具有被配置为至少两个不同尺寸的家庭部件的能力。在封装之前测试IC芯片。如果IC芯片的第一部分是完全功能的，但是第二部分包括局部缺陷，则IC芯片被封装成产品选择代码，所述产品选择代码构成IC裸片仅作为芯片的第一部分进行操作。死亡的第二部分故意使其不能运作。因此，IC芯片仍然可以作为全功能封装IC出售。

3. 发明授权

US07498192B1 Methods of providing a family of related integrated circuits of different sizes 有权
标题翻译：提供不同尺寸的相关集成电路系列的方法
公开(公告)号：US07498192B1
公开(公告)日：2009-03-03
申请号：US11334341
申请日：2006-01-17
申请人： F. Erich Goetting , Trevor J. Bauer , Patrick J. McGuire , Bruce E. Talley , Paul Ying-Fung Wu , Steven P. Young
发明人： F. Erich Goetting , Trevor J. Bauer , Patrick J. McGuire , Bruce E. Talley , Paul Ying-Fung Wu , Steven P. Young
IPC分类号： H01L21/44
CPC分类号： H01L23/00 , H01L2924/0002 , H01L2924/00
摘要： Methods of manufacturing a family of packaged integrated circuits (ICs) having at least two different logic capacities. A first IC die includes two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A first set of the first IC dies are packaged such that both portions of the dies are operational. A second set of the first IC dies are packaged such that only the first portion of each die is operational. Once the first and second sets are packaged and the second set of ICs has been evaluated, a decision is made whether or not to manufacture a second IC die that includes the first portion of the first die, while excluding the second portion.
摘要翻译：制造具有至少两个不同逻辑容量的封装集成电路（IC）系列的方法。第一IC芯片包括两个不同的部分，其中至少一个部分可以以某种方式（例如，非功能的，不可访问的和/或不可编程的）被故意地变为不可操作的。第一组第一IC芯片被封装成使得模具的两个部分都可操作。封装第一组IC芯片，使得只有每个裸片的第一部分可操作。一旦封装了第一组和第二组，并且已经评估了第二组IC，则决定是否制造包括第一模具的第一部分的第二IC模具，同时排除第二部分。

4. 发明授权

US07402443B1 Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes 有权
标题翻译：使用产品选择代码为集成电路系列提供类似模具的方法部分禁用
公开(公告)号：US07402443B1
公开(公告)日：2008-07-22
申请号：US11333819
申请日：2006-01-17
申请人： Raymond C. Pang , Trevor J. Bauer , F. Erich Goetting , Bruce E. Talley , Steven P. Young
发明人： Raymond C. Pang , Trevor J. Bauer , F. Erich Goetting , Bruce E. Talley , Steven P. Young
IPC分类号： G01R31/26
CPC分类号： H01L27/11807 , H01L27/0207
摘要： A method of providing a family of integrated circuits (ICs) includes applying a first product selection code (PSC) to a first IC die, applying a second PSC to a second IC die, and providing a third packaged IC die. The first IC die includes first and second portions, both of which are operational based on the first PSC. The second IC die is a duplicate of the first die, but the second portion is rendered non-operational by the second PSC. The third IC die is substantially similar to the first portion of the first die. The second and third packages can be the same and the packaged dies can be interchangeable in a system. When the dies are programmable logic device (PLD) dies, the second and third dies use the same configuration bit stream, which may be smaller than the configuration bit stream for the first IC die.
摘要翻译：提供集成电路（IC）系列的方法包括：将第一产品选择代码（PSC）应用于第一IC芯片，将第二PSC应用于第二IC芯片，以及提供第三封装IC芯片。第一IC芯片包括第一和第二部分，它们都基于第一PSC而可操作。第二IC芯片是第一裸片的副本，但是第二部分由第二PSC不可操作。第三IC管芯基本上类似于第一管芯的第一部分。第二和第三包可以是相同的，并且包装的模具可以在系统中互换。当管芯是可编程逻辑器件（PLD）管芯时，第二和第三管芯使用与第一IC管芯的配置位流相同的配置位流。

5. 发明授权

US08001511B1 Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies 有权
标题翻译：在多产品可编程IC芯片的可选边界实现和建模互连线路的方法
公开(公告)号：US08001511B1
公开(公告)日：2011-08-16
申请号：US12245858
申请日：2008-10-06
申请人： Trevor J. Bauer , Jeffrey V. Lindholm , F. Erich Goetting , Bruce E. Talley , Ramakrishna K. Tanikella , Steven P. Young
发明人： Trevor J. Bauer , Jeffrey V. Lindholm , F. Erich Goetting , Bruce E. Talley , Ramakrishna K. Tanikella , Steven P. Young
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： H03K19/177 , G06F17/5054 , G06F17/5068
摘要： A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second portion non-operational. At a boundary between the two portions, interconnect lines traversing the boundary include a first section in the first portion and a second section in the second portion. The second PLD die includes the first portion of the first PLD die, while omitting the second portion. The interconnect lines extending to the edge of the second die are coupled together in pairs. A software model for both die includes a termination model that omits the pair coupling, adds an RC load compensating for the omitted connection, and (for bidirectional interconnect lines) flags one interconnect line in each pair as being invalid for use by routing software.
摘要翻译：使用相同的软件模型对两个IC芯片建模的方法，尽管两个芯片包括物理差异。第一可编程逻辑器件（PLD）管芯包括第一和第二部分，并被编码以使第一部分可操作，第二部分不可操作。在两部分之间的边界处，穿过边界的互连线包括第一部分中的第一部分和第二部分中的第二部分。第二PLD管芯包括第一PLD管芯的第一部分，同时省略第二部分。延伸到第二管芯边缘的互连线成对连接在一起。两个芯片的软件模型包括一个省略对耦合的终端模型，增加了对省略连接进行补偿的RC负载，以及（对于双向互连线），标记每对中的一条互连线，因为无法使用路由软件。

6. 发明授权

US07451421B1 Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies 有权
标题翻译：在多产品可编程IC芯片的可选边界实现和建模互连线路的方法
公开(公告)号：US07451421B1
公开(公告)日：2008-11-11
申请号：US11333865
申请日：2006-01-17
申请人： Trevor J. Bauer , Jeffrey V. Lindholm , F. Erich Goetting , Bruce E. Talley , Ramakrishna K. Tanikella , Steven P. Young
发明人： Trevor J. Bauer , Jeffrey V. Lindholm , F. Erich Goetting , Bruce E. Talley , Ramakrishna K. Tanikella , Steven P. Young
IPC分类号： G06F9/455 , G06F17/50 , H03K19/173 , H03K19/177
CPC分类号： H03K19/177 , G06F17/5054 , G06F17/5068
摘要： A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second portion non-operational. At a boundary between the two portions, interconnect lines traversing the boundary include a first section in the first portion and a second section in the second portion. The second PLD die includes the first portion of the first PLD die, while omitting the second portion. The interconnect lines extending to the edge of the second die are coupled together in pairs. A software model for both die includes a termination model that omits the pair coupling, adds an RC load compensating for the omitted connection, and (for bidirectional interconnect lines) flags one interconnect line in each pair as being invalid for use by routing software.
摘要翻译：使用相同的软件模型对两个IC芯片建模的方法，尽管两个芯片包括物理差异。第一可编程逻辑器件（PLD）管芯包括第一和第二部分，并被编码以使第一部分可操作，第二部分不可操作。在两部分之间的边界处，穿过边界的互连线包括第一部分中的第一部分和第二部分中的第二部分。第二PLD管芯包括第一PLD管芯的第一部分，同时省略第二部分。延伸到第二管芯边缘的互连线成对连接在一起。两个芯片的软件模型包括一个省略对耦合的终端模型，增加了对省略连接进行补偿的RC负载，以及（对于双向互连线），标记每对中的一条互连线，因为无法使用路由软件。

7. 发明授权

US06817005B2 Modular design method and system for programmable logic devices 有权
标题翻译：可编程逻辑器件的模块化设计方法和系统
公开(公告)号：US06817005B2
公开(公告)日：2004-11-09
申请号：US09839464
申请日：2001-04-20
申请人： Jeffrey M. Mason , Steve E. Lass , Bruce E. Talley , David W. Bennett
发明人： Jeffrey M. Mason , Steve E. Lass , Bruce E. Talley , David W. Bennett
IPC分类号： G06F1750
CPC分类号： G06F17/5054 , G06F17/5072
摘要： In modular design flow, logic designers are able to partition a top-level logic design for a PLD into modules and implement any module independently from other modules. Modules are mapped, placed, and routed using selected information derived at the time the top-level logic design is partitioned. Finally, the modules are integrated into the top-level logic design using a guided process. Specifically, the information generated during the partitioning of the top-level design and the implementation of each module is used to guide the implementation of the associated logic in the top-level design. In this manner, the implementation of all modules can proceed in any order or in parallel and the integration of the modules into the top-level design can be done quickly and in any order.
摘要翻译：在模块化设计流程中，逻辑设计人员可以将PLD的顶级逻辑设计分为模块，并独立于其他模块实现任何模块。使用在顶层逻辑设计分区时导出的所选信息对模块进行映射，放置和布线。最后，使用引导过程将模块集成到顶级逻辑设计中。具体来说，在顶层设计分区和每个模块的实现过程中生成的信息用于指导顶层设计中相关逻辑的实现。以这种方式，所有模块的实现可以以任何顺序或并行进行，并且将模块集成到顶层设计中可以以任何顺序快速完成。

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