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1. 发明授权

US6074903A Method for forming electrical isolation for semiconductor devices 失效
标题翻译：用于形成半导体器件的电隔离的方法
公开(公告)号：US6074903A
公开(公告)日：2000-06-13
申请号：US98203
申请日：1998-06-16
申请人： Rajesh Rengarajan , Hirofumi Inoue , Radhika Srinivasan , Jochen Beintner
发明人： Rajesh Rengarajan , Hirofumi Inoue , Radhika Srinivasan , Jochen Beintner
IPC分类号： H01L21/76 , H01L21/762 , H01L27/08 , H01L21/8238
CPC分类号： H01L21/76237
摘要： A method for forming a electrically isolated semiconductor devices in a silicon body. A trench is formed in a selected region of the body. A barrier material is deposited over sidewalls of the trench. Portions of the barrier material are removed from a first sidewall portion of the trench to expose such first sidewall portion of the trench while leaving portions of such barrier material on a second sidewall portion of the trench to form a barrier layer thereon. A dielectric material is deposited in the trench, a portion of dielectric material being deposited on the exposed first sidewall portion of the trench and another portion of such deposited dielectric material being deposited on the barrier material. The dielectric material is annealed in an oxidizing environment to densify such deposited dielectric material, the barrier layer inhibiting oxidation of the said second sidewall portion of the trench. A plurality of the semiconductor devices is formed in the silicon body with such devices being electrically isolated by the dielectric material in the trench.
摘要翻译：一种用于在硅体中形成电绝缘的半导体器件的方法。在身体的选定区域中形成沟槽。阻挡材料沉积在沟槽的侧壁上。阻挡材料的一部分从沟槽的第一侧壁部分被去除以暴露沟槽的这种第一侧壁部分，同时将这种阻挡材料的一部分留在沟槽的第二侧壁部分上以在其上形成阻挡层。电介质材料沉积在沟槽中，介电材料的一部分沉积在暴露的沟槽的第一侧壁部分上，另一部分沉积的介电材料沉积在阻挡材料上。电介质材料在氧化环境中退火以致密化这种淀积的介电材料，阻挡层阻止沟槽的所述第二侧壁部分的氧化。在硅体中形成多个半导体器件，这些器件通过沟槽中的电介质材料电隔离。

2. 发明授权

US06323103B1 Method for fabricating transistors 有权
标题翻译：晶体管制造方法
公开(公告)号：US06323103B1
公开(公告)日：2001-11-27
申请号：US09175267
申请日：1998-10-20
申请人： Rajesh Rengarajan , Jochen Beintner , Ulrike Gruening , Hans-Oliver Joachim
发明人： Rajesh Rengarajan , Jochen Beintner , Ulrike Gruening , Hans-Oliver Joachim
IPC分类号： H01L218238
CPC分类号： H01L21/823878 , H01L21/762
摘要： A method is provided for fabricating a first and second MOSFET transistors in different electrically isolated active areas of a semiconductor body, each one of the transistors having a plurality of layers. A first gate oxide layer and a first poly-crystalline silicon layer are deposited over the semiconductor body over the active areas. Trenches are etched in said first gate oxide and poly-crystalline silicon layers and said semiconductor body to delineate the first and second active areas, thereby forming first delineated gate oxide layer and poly-crystalline silicon layers coextensive with the first active area. Material is deposited in said trenches to form the active area isolations, the active area isolations having a top surface above said semiconductor body. A masking layer is then formed over said first and second active areas and selective portions of it are removed to expose said second active area. The masking layer and the active area isolations together form a mask defining an opening coextensive with the second active area with the active area isolations defining said opening. Material through the opening to form a second gate oxide layer and a second poly-crystalline layer, such second layer and second poly-crystalline layer being coextensive with the second active area. The first transistor with the first delineated gate oxide and poly-crystalline layer as a pair of the plurality of layers of the first transistor and the second transistor with the second gate oxide layer and second poly-crystalline layer as a pair of the plurality of layers of the second transistor.
摘要翻译：提供了一种用于在半导体主体的不同电隔离有源区中制造第一和第二MOSFET晶体管的方法，每个晶体管具有多个层。第一栅极氧化物层和第一多晶硅层沉积在半导体主体上方的有源区域上。在所述第一栅极氧化物和多晶硅层和所述半导体本体中蚀刻沟槽以描绘第一和第二有源区，从而形成与第一有源区共同延伸的第一划定的栅极氧化物层和多晶硅层。材料沉积在所述沟槽中以形成有源区隔离，所述有源区隔离在所述半导体本体上方具有顶表面。然后在所述第一和第二有源区上形成掩模层，并且去除其选择性部分以暴露所述第二有源区。屏蔽层和有源区隔离一起形成掩模，其限定与第二有源区域共同延伸的开口，其中限定所述开口的有源区隔离。通过开口的材料形成第二栅氧化层和第二多晶层，这种第二层和第二多晶层与第二有源区共同延伸。第一晶体管，其具有第一划定的栅极氧化物和多晶层作为第一晶体管的多个层和第二晶体管的一对，其中第二栅极氧化物层和第二多晶层作为一对多个层的第二晶体管。

3. 发明授权

US06348394B1 Method and device for array threshold voltage control by trapped charge in trench isolation 失效
标题翻译：用于沟槽隔离中捕获电荷的阵列阈值电压控制的方法和装置
公开(公告)号：US06348394B1
公开(公告)日：2002-02-19
申请号：US09573375
申请日：2000-05-18
申请人： Jack A. Mandelman , Rama Divakaruni , Herbert Ho , Giuseppe La Rosa , Yujun Li , Jochen Beintner , Radhika Srinivasan
发明人： Jack A. Mandelman , Rama Divakaruni , Herbert Ho , Giuseppe La Rosa , Yujun Li , Jochen Beintner , Radhika Srinivasan
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/76224
摘要： A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.
摘要翻译：提供半导体器件及其制造方法。在半导体衬底中形成沟槽。优选在沟槽的表面上形成薄的氧化物衬垫。氮化物衬垫形成在沟槽中。电荷被困在氮化物衬垫中。在优选实施例中，沟槽通过HDP工艺填充氧化物以增加在氮化物衬垫中捕获的电荷量。优选地，氧化物填充物直接形成在氮化物衬垫上。

4. 发明申请

US20080176365A1 Method of making double-gated self-aligned finFET having gates of different lengths 失效
标题翻译：制造具有不同长度的栅极的双门控自对准finFET的方法
公开(公告)号：US20080176365A1
公开(公告)日：2008-07-24
申请号：US12077973
申请日：2008-03-24
申请人： Huilong Zhu , Bruce B. Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip J. Oldiges
发明人： Huilong Zhu , Bruce B. Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip J. Oldiges
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7855 , H01L29/7856
摘要： A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.
摘要翻译：提供了一种制造门控半导体器件的方法。这种方法可以包括图案化衬底的单晶半导体区域，以在与衬底的主表面平行的横向方向上延伸并且沿至少基本上垂直且至少基本垂直于主表面的方向延伸，半导体区域具有第一侧和第二侧，例如远离第一侧。第一栅极可以形成在第一侧上，第一栅极在横向上具有第一栅极长度。第二栅极可以形成在第二侧上，第二栅极在横向上具有与第一栅极长度不同的第二栅极长度。在一个实施例中，第二栅极长度可以比第一栅极长度短。在一个实施例中，第一栅极可以主要由多晶硅锗组成，第二栅极可以由多晶硅组成。

5. 发明授权

US07129564B2 Structure and method of forming a notched gate field effect transistor 有权
标题翻译：形成陷波栅场效应晶体管的结构和方法
公开(公告)号：US07129564B2
公开(公告)日：2006-10-31
申请号：US11059819
申请日：2005-02-17
申请人： Jochen Beintner , Yujun Li , Naim Moumen , Porshia Shane Wrschka
发明人： Jochen Beintner , Yujun Li , Naim Moumen , Porshia Shane Wrschka
IPC分类号： H01L31/117
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/28044 , H01L21/28114 , H01L29/42376 , H01L29/49 , H01L29/665 , Y10S438/933
摘要： The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.
摘要翻译：本文公开的形成缺口栅极MOSFET的结构和方法解决了诸如器件可靠性的问题。栅电介质（例如栅极氧化物）形成在半导体衬底上的有源区的表面上，优选由隔离沟槽区限定。然后在栅极电介质上沉积多晶硅层。该步骤之后是沉积一层硅锗）（SiGe）。然后横向蚀刻多晶硅层的侧壁，对SiGe层有选择性，以产生刻蚀的栅极导体结构，其中SiGe层比下面的多晶硅层宽。侧壁间隔物优选形成在SiGe层和多晶硅层的侧壁上。硅化物层优选从沉积在SiGe层上的多晶硅层形成为自对准硅化物，以降低栅极导体的电阻。优选在完成晶体管时执行一个或多个其它处理步骤（例如源极和漏极注入，延伸注入和袖带轻掺杂漏极（LDD）注入），栅极导体堆叠掺杂和硅化。

6. 发明授权

US07087952B2 Dual function FinFET, finmemory and method of manufacture 有权
标题翻译：双功能FinFET，Finmemory和制造方法
公开(公告)号：US07087952B2
公开(公告)日：2006-08-08
申请号：US10978951
申请日：2004-11-01
申请人： Huilong Zhu , Bruce B. Doris , Jochen Beintner
发明人： Huilong Zhu , Bruce B. Doris , Jochen Beintner
IPC分类号： H01L29/788
CPC分类号： H01L29/78684 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/4908 , H01L29/66795 , H01L29/785 , H01L29/7881
摘要： A non-volatile storage cell in a Fin Field Effect Transistor (FinFET) and a method of forming an Integrated Circuit (IC) chip including the non-volatile storage cell. Each FET includes a control gate along one side of a semiconductor (e.g., silicon) fin, a floating gate along an opposite of the fin and a program gate alongside the floating gate. Control gate device thresholds are adjusted by adjusting charge on the floating gate.
摘要翻译： Fin场效应晶体管（FinFET）中的非易失性存储单元以及形成包括非易失性存储单元的集成电路（IC）芯片的方法。每个FET包括沿着半导体（例如硅）翅片的一侧的控制栅极，沿着鳍片的相对的浮动栅极和沿着浮动栅极的编程栅极。通过调节浮动栅极上的电荷来调节控制栅极器件的阈值。

7. 发明申请

US20060024930A1 Method of implanting using a shadow effect 有权
标题翻译：使用阴影效果进行植入的方法
公开(公告)号：US20060024930A1
公开(公告)日：2006-02-02
申请号：US11235330
申请日：2005-09-26
申请人： Helmut Tews , Jochen Beintner
发明人： Helmut Tews , Jochen Beintner
IPC分类号： H01L21/425
CPC分类号： H01L21/823462 , H01L21/26506 , H01L21/26586 , H01L21/2822 , H01L21/823481 , H01L27/0629 , H01L27/10873 , Y10S438/981
摘要： A semiconductor body has a first portion, a second portion, and an active area located between the first portion and the second portion. The first portion and the second portion are a shallow trench isolation region having an exposed surface extending above the surface of the active area. A first ion implantation is performed at a first angle such that a first shaded area defined by the exposed surface of the first portion and the first angle is exposed to fewer ions than a first unshaded area. A second ion implantation is performed at a second angle such that a second shaded area defined by the exposed surface of the second portion and the second angle is exposed to fewer ions than a second unshaded area.
摘要翻译：半导体本体具有位于第一部分和第二部分之间的第一部分，第二部分和有源区域。第一部分和第二部分是具有在有源区域的表面上方延伸的暴露表面的浅沟槽隔离区域。以第一角度执行第一离子注入，使得由第一部分的暴露表面限定的第一阴影区域和第一角度暴露于比第一未阴影区域更少的离子。以第二角度执行第二离子注入，使得由第二部分的暴露表面限定的第二阴影区域和第二角度暴露于比第二未阴影区域更少的离子。

8. 发明授权

US06987042B2 Method of forming a collar using selective SiGe/Amorphous Si Etch 失效
标题翻译：使用选择性SiGe /无定形Si蚀刻法形成套环的方法
公开(公告)号：US06987042B2
公开(公告)日：2006-01-17
申请号：US10250046
申请日：2003-05-30
申请人： Jochen Beintner , Naim Moumen , Porshia S. Wrschka
发明人： Jochen Beintner , Naim Moumen , Porshia S. Wrschka
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L21/30604 , H01L29/66181 , H01L29/945
摘要： A method of forming collar isolation for a trench storage memory cell structure is provided in which amorphous Si (a:Si) and silicon germanium (SiGe) are first formed into a trench structure. An etching process that is selective to a:Si as compared to SiGe is employed in defining the regions in which the collar isolation will be formed. The selective etching process employed in the present invention is a wet etch process that includes etching with HF, rinsing, etching with NH4OH, rinsing, and drying with a monohydric alcohol such as isopropanol. The sequence of NH4OH etching and rinsing may be repeated any number of times. The conditions used in the selective etching process of the present invention are capable of etching a:Si at a faster rate than SiGe.
摘要翻译：提供了一种形成沟槽存储单元结构的套环隔离的方法，其中首先将非晶硅（a：Si）和硅锗（SiGe）形成沟槽结构。与SiGe相比，对a：Si有选择性的蚀刻工艺用于限定将形成套环隔离的区域。在本发明中采用的选择性蚀刻方法是湿式蚀刻工艺，其包括用HF蚀刻，漂洗，用NH 4 OH蚀刻，漂洗和用一元醇如异丙醇干燥。 NH 4 OH蚀刻和漂洗的顺序可以重复任意次数。在本发明的选择性蚀刻工艺中使用的条件能够以比SiGe更快的速度蚀刻Si。

9. 发明申请

US20050158927A1 Structure and method of forming a notched gate field effect transistor 有权
公开(公告)号：US20050158927A1
公开(公告)日：2005-07-21
申请号：US11059819
申请日：2005-02-17
申请人： Jochen Beintner , Yujun Li , Naim Moumen , Porshia Wrschka
发明人： Jochen Beintner , Yujun Li , Naim Moumen , Porshia Wrschka
IPC分类号： H01L29/423 , H01L21/265 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L29/786 , H01L21/00 , H01L21/8238 , H01L21/84
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/28044 , H01L21/28114 , H01L29/42376 , H01L29/49 , H01L29/665 , Y10S438/933
摘要： The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.

10. 发明授权

US06579768B2 Field effect transistor and method of fabrication 有权
公开(公告)号：US06579768B2
公开(公告)日：2003-06-17
申请号：US10066184
申请日：2002-01-31
申请人： Peter Thwaite , Jochen Beintner
发明人： Peter Thwaite , Jochen Beintner
IPC分类号： H01L21336
CPC分类号： H01L29/1033 , H01L21/76235
摘要： An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge of the channel region. A method of controlling the shape of the edge of the channel region is to limit the supply of oxygen to the region at the edge of the channel region during the oxidation process when the side walls of the silicon island, in which the transistor will be formed, are initially covered with a layer of silicon oxide.

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