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1. 发明授权

US06348394B1 Method and device for array threshold voltage control by trapped charge in trench isolation 失效
标题翻译：用于沟槽隔离中捕获电荷的阵列阈值电压控制的方法和装置
公开(公告)号：US06348394B1
公开(公告)日：2002-02-19
申请号：US09573375
申请日：2000-05-18
申请人： Jack A. Mandelman , Rama Divakaruni , Herbert Ho , Giuseppe La Rosa , Yujun Li , Jochen Beintner , Radhika Srinivasan
发明人： Jack A. Mandelman , Rama Divakaruni , Herbert Ho , Giuseppe La Rosa , Yujun Li , Jochen Beintner , Radhika Srinivasan
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/76224
摘要： A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.
摘要翻译：提供半导体器件及其制造方法。在半导体衬底中形成沟槽。优选在沟槽的表面上形成薄的氧化物衬垫。氮化物衬垫形成在沟槽中。电荷被困在氮化物衬垫中。在优选实施例中，沟槽通过HDP工艺填充氧化物以增加在氮化物衬垫中捕获的电荷量。优选地，氧化物填充物直接形成在氮化物衬垫上。

2. 发明授权

US07129564B2 Structure and method of forming a notched gate field effect transistor 有权
标题翻译：形成陷波栅场效应晶体管的结构和方法
公开(公告)号：US07129564B2
公开(公告)日：2006-10-31
申请号：US11059819
申请日：2005-02-17
申请人： Jochen Beintner , Yujun Li , Naim Moumen , Porshia Shane Wrschka
发明人： Jochen Beintner , Yujun Li , Naim Moumen , Porshia Shane Wrschka
IPC分类号： H01L31/117
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/28044 , H01L21/28114 , H01L29/42376 , H01L29/49 , H01L29/665 , Y10S438/933
摘要： The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.
摘要翻译：本文公开的形成缺口栅极MOSFET的结构和方法解决了诸如器件可靠性的问题。栅电介质（例如栅极氧化物）形成在半导体衬底上的有源区的表面上，优选由隔离沟槽区限定。然后在栅极电介质上沉积多晶硅层。该步骤之后是沉积一层硅锗）（SiGe）。然后横向蚀刻多晶硅层的侧壁，对SiGe层有选择性，以产生刻蚀的栅极导体结构，其中SiGe层比下面的多晶硅层宽。侧壁间隔物优选形成在SiGe层和多晶硅层的侧壁上。硅化物层优选从沉积在SiGe层上的多晶硅层形成为自对准硅化物，以降低栅极导体的电阻。优选在完成晶体管时执行一个或多个其它处理步骤（例如源极和漏极注入，延伸注入和袖带轻掺杂漏极（LDD）注入），栅极导体堆叠掺杂和硅化。

3. 发明申请

US20050158927A1 Structure and method of forming a notched gate field effect transistor 有权
公开(公告)号：US20050158927A1
公开(公告)日：2005-07-21
申请号：US11059819
申请日：2005-02-17
申请人： Jochen Beintner , Yujun Li , Naim Moumen , Porshia Wrschka
发明人： Jochen Beintner , Yujun Li , Naim Moumen , Porshia Wrschka
IPC分类号： H01L29/423 , H01L21/265 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L29/786 , H01L21/00 , H01L21/8238 , H01L21/84
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/28044 , H01L21/28114 , H01L29/42376 , H01L29/49 , H01L29/665 , Y10S438/933
摘要： The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.

4. 发明授权

US07696539B2 Device fabrication by anisotropic wet etch 失效
标题翻译：通过各向异性湿法蚀刻的器件制造
公开(公告)号：US07696539B2
公开(公告)日：2010-04-13
申请号：US12141878
申请日：2008-06-18
申请人： Yujun Li , Kenneth T. Settlemyer, Jr. , Jochen Beintner
发明人： Yujun Li , Kenneth T. Settlemyer, Jr. , Jochen Beintner
IPC分类号： H01L29/80
CPC分类号： H01L21/84 , H01L21/30608 , H01L27/1203 , H01L29/045 , H01L29/66772 , H01L29/66818 , H01L29/785
摘要： A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.
摘要翻译：提出了一种制造方法和场效应器件结构，其减少源/漏电容并允许器件接触。产生基于Si的材料基座，其顶表面和其侧壁的方向定位成与基座和支撑构件的选定结晶平面基本平行。用包含氢氧化铵的各向异性溶液湿式蚀刻基座。基座的侧壁变小，在基座上形成截面减小的部分。选择减小的横截面段中的掺杂剂浓度足够高以使其提供穿过基座的电连续性。

5. 发明授权

US07470570B2 Process for fabrication of FinFETs 有权
标题翻译： FinFET的制造工艺
公开(公告)号：US07470570B2
公开(公告)日：2008-12-30
申请号：US11559460
申请日：2006-11-14
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L21/00
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

6. 发明申请

US20080111184A1 PROCESS FOR FABRICATION OF FINFETs 有权
标题翻译： FINFET制造工艺
公开(公告)号：US20080111184A1
公开(公告)日：2008-05-15
申请号：US11559460
申请日：2006-11-14
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

7. 发明授权

US06905976B2 Structure and method of forming a notched gate field effect transistor 失效
标题翻译：形成陷波栅场效应晶体管的结构和方法
公开(公告)号：US06905976B2
公开(公告)日：2005-06-14
申请号：US10249771
申请日：2003-05-06
申请人： Jochen Beintner , Yujun Li , Naim Moumen , Porshia Shane Wrschka
发明人： Jochen Beintner , Yujun Li , Naim Moumen , Porshia Shane Wrschka
IPC分类号： H01L29/423 , H01L21/265 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L29/786 , H01L21/302
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/28044 , H01L21/28114 , H01L29/42376 , H01L29/49 , H01L29/665 , Y10S438/933
摘要： The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.
摘要翻译：本文公开的形成缺口栅极MOSFET的结构和方法解决了诸如器件可靠性的问题。栅电介质（例如栅极氧化物）形成在半导体衬底上的有源区的表面上，优选由隔离沟槽区限定。然后在栅极电介质上沉积多晶硅层。该步骤之后是沉积一层硅锗）（SiGe）。然后横向蚀刻多晶硅层的侧壁，对SiGe层有选择性，以产生刻蚀的栅极导体结构，其中SiGe层比下面的多晶硅层宽。侧壁间隔物优选形成在SiGe层和多晶硅层的侧壁上。硅化物层优选从沉积在SiGe层上的多晶硅层形成为自对准硅化物，以降低栅极导体的电阻。优选在完成晶体管时执行一个或多个其它处理步骤（例如源极和漏极注入，延伸注入和袖带轻掺杂漏极（LDD）注入），栅极导体堆叠掺杂和硅化。

8. 发明授权

US06297530B1 Self aligned channel implantation 失效
标题翻译：自对准通道植入
公开(公告)号：US06297530B1
公开(公告)日：2001-10-02
申请号：US09418181
申请日：1998-12-28
申请人： Hiroyuki Akatsu , Yujun Li , Jochen Beintner
发明人： Hiroyuki Akatsu , Yujun Li , Jochen Beintner
IPC分类号： H01L2976
CPC分类号： H01L29/66583 , H01L21/823412 , H01L29/105
摘要： A short channel insulated gate field effect transistor has within the semiconductor body that houses the transistor a buried layer of the same conductivity type as the body but of higher impurity concentration. The buried layer is below the channel region and essentially extends only the distance between the drain and source regions of the transistor. The process to form the device provides high concentration in the region under the gate to suppress lateral depletion region expansion, while keeping a gradual junction in the vertical direction.
摘要翻译：短沟道绝缘栅场效应晶体管在半导体本体内部具有与晶体管相同的导电类型的掩埋层，但具有较高的杂质浓度。掩埋层在沟道区下方，并且基本上只延伸晶体管的漏极和源极区之间的距离。形成器件的过程在栅极下方的区域提供高浓度，以抑制横向耗尽区域膨胀，同时保持垂直方向上的逐渐连接。

9. 发明授权

US06433397B1 N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same 失效
标题翻译： N沟道金属氧化物半导体（NMOS）驱动电路及其制造方法
公开(公告)号：US06433397B1
公开(公告)日：2002-08-13
申请号：US09488515
申请日：2000-01-21
申请人： Lawrence A. Clevenger , Rama Divakaruni , Louis Lu-Chen Hsu , Yujun Li
发明人： Lawrence A. Clevenger , Rama Divakaruni , Louis Lu-Chen Hsu , Yujun Li
IPC分类号： H01L27085
CPC分类号： H01L29/6659 , H01L21/2251 , H01L21/76895 , H01L27/088 , Y10S438/969
摘要： An N-channel metal oxide semiconductor (NMOS) driver circuit (and method for making the same), includes a boost gate stack formed on a substrate and having a source and drain formed by a low concentration N-type implantation, and an N-driver coupled to the boost gate stack.
摘要翻译： N沟道金属氧化物半导体（NMOS）驱动电路（及其制造方法）包括形成在基板上的升压栅叠层，具有通过低浓度N型注入形成的源极和漏极，以及N- 驱动器耦合到升压栅极堆叠。

10. 发明授权

US07666741B2 Corner clipping for field effect devices 有权
标题翻译：场效应装置的角剪
公开(公告)号：US07666741B2
公开(公告)日：2010-02-23
申请号：US11333109
申请日：2006-01-17
申请人： Yujun Li , Kenneth T. Settlemyer, Jr. , Jochen Beintner
发明人： Yujun Li , Kenneth T. Settlemyer, Jr. , Jochen Beintner
IPC分类号： H01L21/336
CPC分类号： H01L21/30608 , H01L29/045 , H01L29/66795 , H01L29/7853
摘要： A method is presented for fabricating a non-planar field effect device. The method includes the production of a Si based material Fin structure that has a top surface substantially in parallel with a {111} crystallographic plane of the Si Fin structure, and the etching of the Si Fin structure with a solution which contains ammonium hydroxide (NH4OH). In this manner, due to differing etch rates in ammonium hydroxide of various Si based material crystallographic planes, the corners on the Fin structure become clipped, and angles between the horizontal and vertical planes of the Fin structure increase. A FinFET device with clipped, or rounded, corners is then fabricated to completion. In a typical embodiment the FinFET device is selected to be a silicon-on-insulator (SOI) device.
摘要翻译：提出了一种用于制造非平面场效应器件的方法。该方法包括生产Si基材料Fin结构，其具有与Si Fin结构的{111}晶面基本上平行的顶表面，并且用含有氢氧化铵（NH 4 OH）的溶液蚀刻Si Fin结构）。以这种方式，由于各种Si基材料结晶面的氢氧化铵中的蚀刻速率不同，Fin结构上的拐角被限制，Fin结构的水平和垂直平面之间的角度增加。然后制造具有夹角或圆角的FinFET器件以完成。在典型的实施例中，FinFET器件被选择为绝缘体上硅（SOI）器件。

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