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1. 发明申请

US20050054149A1 METHOD FOR INTEGRATING METALS HAVING DIFFERENT WORK FUNCTIONS TO FOM CMOS GATES HAVING A HIGH-K GATE DIELECTRIC AND RELATED STRUCTURE 有权
标题翻译：具有不同工作功能的金属的方法用于具有高K栅介质和相关结构的FOM CMOS栅
公开(公告)号：US20050054149A1
公开(公告)日：2005-03-10
申请号：US10654689
申请日：2003-09-04
申请人： Qi Xiang , Huicai Zhong , Jung-Suk Goo , Allison Holbrook , Joong Jeon , George Kluth
发明人： Qi Xiang , Huicai Zhong , Jung-Suk Goo , Allison Holbrook , Joong Jeon , George Kluth
IPC分类号： H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L21/336
CPC分类号： H01L21/823857 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518
摘要： According to one exemplary embodiment, a method for integrating first and second metal layers on a substrate to form a dual metal NMOS gate and PMOS gate comprises depositing a dielectric layer over an NMOS region and a PMOS region of the substrate. The method further comprises depositing the first metal layer over dielectric layer. The method further comprises depositing the second metal layer over the first metal layer. The method further comprises implanting nitrogen in the NMOS region of substrate and converting a first portion of the first metal layer into a metal oxide layer and converting a second portion of the first metal layer into metal nitride layer. The method further comprises forming the NMOS gate and the PMOS gate, where the NMOS gate comprises a segment of metal nitride layer and the PMOS gate comprises a segment of the metal oxide layer.
摘要翻译：根据一个示例性实施例，一种用于在衬底上将第一和第二金属层集成以形成双金属NMOS栅极和PMOS栅极的方法包括在衬底的NMOS区域和PMOS区域上沉积介电层。该方法还包括在电介质层上沉积第一金属层。该方法还包括在第一金属层上沉积第二金属层。该方法还包括在衬底的NMOS区域中注入氮气，并将第一金属层的第一部分转变为金属氧化物层，并将第一金属层的第二部分转换为金属氮化物层。该方法还包括形成NMOS栅极和PMOS栅极，其中NMOS栅极包括一段金属氮化物层，PMOS栅极包括金属氧化物层的一段。

2. 发明申请

US20050101147A1 Method for integrating a high-k gate dielectric in a transistor fabrication process 审中-公开
标题翻译：在晶体管制造工艺中集成高k栅极电介质的方法
公开(公告)号：US20050101147A1
公开(公告)日：2005-05-12
申请号：US10705347
申请日：2003-11-08
申请人： Catherine Labelle , Boon-Yong Ang , Joong Jeon , Allison Holbrook , Qi Xiang , Huicai Zhong
发明人： Catherine Labelle , Boon-Yong Ang , Joong Jeon , Allison Holbrook , Qi Xiang , Huicai Zhong
IPC分类号： H01L21/28 , H01L29/51 , H01L21/302 , H01L21/461
CPC分类号： H01L21/28202 , H01L21/28176 , H01L21/28247 , H01L29/517 , H01L29/518
摘要： According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate, where the substrate includes a high-k dielectric layer situated over the substrate and a gate electrode layer situated over the high-k dielectric layer, comprises a step of etching the gate electrode layer and the high-k dielectric layer to form a gate stack, where the gate stack comprises a high-k dielectric segment situated over the substrate and a gate electrode segment situated over the high-k dielectric segment. According to this exemplary embodiment, the method further comprises performing a nitridation process on the gate stack. The nitridation process can be performed by, for example, utilizing a plasma to nitridate sidewalls of the gate stack, where the plasma comprises nitrogen. The nitridation process can cause nitrogen to enter the high-k dielectric segment and form an oxygen diffusion barrier in the high-k dielectric segment, for example.
摘要翻译：根据一个示例性实施例，一种在衬底上形成场效应晶体管的方法，其中衬底包括位于衬底上方的高k电介质层和位于高k电介质层上方的栅电极层，包括步骤蚀刻栅极电极层和高k电介质层以形成栅极叠层，其中栅极堆叠包括位于衬底上方的高k电介质段和位于高k电介质段上方的栅电极段。根据该示例性实施例，该方法还包括在栅极堆叠上执行氮化处理。氮化工艺可以通过例如利用等离子体来氮化栅堆叠的侧壁来进行，其中等离子体包括氮。例如，氮化处理可以使氮进入高k电介质段，并在高k电介质段中形成氧扩散阻挡层。

3. 发明授权

US07033894B1 Method for modulating flatband voltage of devices having high-k gate dielectrics by post-deposition annealing 有权
标题翻译：通过后期沉积退火来调制具有高k栅极电介质的器件的平带电压的方法
公开(公告)号：US07033894B1
公开(公告)日：2006-04-25
申请号：US10633596
申请日：2003-08-05
申请人： Huicai Zhong , Joong Jeon
发明人： Huicai Zhong , Joong Jeon
IPC分类号： H01L21/336
CPC分类号： H01L21/28194 , H01L21/28185
摘要： A method for modulating the flatband voltage of semiconductor devices includes post-deposition annealing of a high-k dielectric film deposited by chemical vapor deposition, for example. The modulation of the flatband voltage, and thus, the threshold voltage of MOSFET devices, is achieved by post-deposition annealing of the high-k dielectric film and control of the annealing parameters. These include annealing gases, annealing temperatures and annealing times.
摘要翻译：用于调制半导体器件的扁平带电压的方法包括例如通过化学气相沉积沉积的高k电介质膜的后沉积退火。通过高k电介质膜的后沉积退火和退火参数的控制来实现平坦带电压的调制，从而实现MOSFET器件的阈值电压。这些包括退火气体，退火温度和退火时间。

4. 发明授权

US06448127B1 Process for formation of ultra-thin base oxide in high k/oxide stack gate dielectrics of mosfets 有权
标题翻译：用于在高k /氧化物堆叠栅极电介质中形成超薄基础氧化物的工艺
公开(公告)号：US06448127B1
公开(公告)日：2002-09-10
申请号：US09740606
申请日：2000-12-19
申请人： Qi Xiang , Joong Jeon , Colman Wong
发明人： Qi Xiang , Joong Jeon , Colman Wong
IPC分类号： H01L218238
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/28238 , H01L21/823857 , H01L29/513 , H01L29/518 , Y10S438/976 , Y10S438/981
摘要： A method and article of manufacture of an ultra-thin base oxide or nitrided oxide layer in a CMOS device. The method and article of manufacture are formed by providing a silicon wafer with an initial oxide layer which is removed from the silicon wafer by a hydrogen baking step. A new oxide layer or nitrided oxide layer is formed by thermal growth on the silicon wafer surface. A portion of the new oxide layer is removed by hydrogen annealing. A MOSFET can be created by forming a gate electrode structure on a high-k dielectric material deposited on the new oxide layer.
摘要翻译：在CMOS器件中的超薄基底氧化物或氮化氧化物层的制造方法和制造方法。该方法和制造方法通过提供硅晶片来形成，该初始氧化物层通过氢焙烧步骤从硅晶片上除去。通过在硅晶片表面上的热生长形成新的氧化物层或氮化氧化物层。通过氢退火除去一部分新的氧化物层。可以通过在沉积在新氧化物层上的高k电介质材料上形成栅电极结构来产生MOSFET。

5. 发明授权

US06187657B1 Dual material gate MOSFET technique 失效
标题翻译：双材料栅极MOSFET技术
公开(公告)号：US06187657B1
公开(公告)日：2001-02-13
申请号：US09275486
申请日：1999-03-24
申请人： Qi Xiang , Joong Jeon
发明人： Qi Xiang , Joong Jeon
IPC分类号： H01L2128
CPC分类号： H01L21/28202 , H01L21/28105 , H01L21/31111 , H01L21/823842 , H01L29/4983 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/6659
摘要： This invention comprises a new technique to realize a dual material gate MOSFET. The inventive technique is base upon an asymmetric oxide spacer formation and a self-aligned silicide formation. The asymmetric oxide spacer on the sidewall of the drain side of the gate is formed by selectively etching the spacer on the source side. The etch selectivity is realized by nitrogen implantation into an oxide spacer on the source side, by utilizing preferably an angled ion implantation technique. An HF solution has been experimentally demonstrated to provide an etch rate of the nitrogen implanted oxide that is much faster than the oxide without the nitrogen implantation.
摘要翻译：本发明包括实现双材料栅极MOSFET的新技术。本发明的技术基于不对称氧化物间隔物形成和自对准硅化物形成。通过选择性地蚀刻源极侧的间隔物来形成栅极的漏极侧的侧壁上的非对称氧化物间隔物。通过优选采用成角度的离子注入技术，通过将氮注入到源极上的氧化物隔离物中来实现蚀刻选择性。实验证明，HF溶液提供氮注入氧化物的蚀刻速率，其比没有氮注入的氧化物要快得多。

6. 发明授权

US06759346B1 Method of forming dielectric layers 有权
标题翻译：形成电介质层的方法
公开(公告)号：US06759346B1
公开(公告)日：2004-07-06
申请号：US10270325
申请日：2002-10-15
申请人： Joong Jeon
发明人： Joong Jeon
IPC分类号： H01L2131
CPC分类号： H01L21/31645 , C23C16/40 , C23C16/401 , C23C16/45531 , H01L21/3142
摘要： A method of forming a dielectric layer includes placing a semiconductor wafer in a reaction chamber. Oxygen, hafnium and silicon sources are separately provided to the reaction chamber to react with the wafer. After each source has reacted, a monolayer or near-monolayer film is produced. Each source may also be provided to the reaction chamber a number of times to achieve a film having the desired thickness.
摘要翻译：形成电介质层的方法包括将半导体晶片放置在反应室中。氧，铪和硅源分别提供给反应室以与晶片反应。在每个源已经反应之后，产生单层或近单层膜。也可以将各个源多次提供到反应室以实现具有所需厚度的膜。

7. 发明申请

US20080150028A1 ZERO INTERFACE POLYSILICON TO POLYSILICON GATE FOR SEMICONDUCTOR DEVICE 审中-公开
标题翻译：零界面多晶硅用于半导体器件的多晶硅栅极
公开(公告)号：US20080150028A1
公开(公告)日：2008-06-26
申请号：US11614774
申请日：2006-12-21
申请人： Robert Bertram Ogle , Joong Jeon , Jon Kluth
发明人： Robert Bertram Ogle , Joong Jeon , Jon Kluth
IPC分类号： H01L29/78 , C23C16/00 , H01L21/4763
CPC分类号： H01L21/02068 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857
摘要： A system and method are disclosed for processing a zero angstrom oxide interface dual poly gate structure for a semiconductor device. An exemplary method can include removing an oxide from a surface of a first poly layer and forming a second poly layer on the first poly layer in a processing chamber. A transfer of the structure is not needed from an oxide removal tool to, for example, a poly layer formation tool, an implant tool, and the like. As a result, impurities containing a silicon oxide caused by exposure of the first poly layer to an oxygen-containing atmosphere do not form at the interface of the first and second poly layers.
摘要翻译：公开了用于处理用于半导体器件的零氧化物界面双重多晶硅结构的系统和方法。示例性的方法可以包括从第一多晶硅层的表面去除氧化物，并在处理室中的第一多晶硅层上形成第二多晶硅层。不需要从氧化物去除工具到例如多层形成工具，植入工具等的结构的转移。结果，在第一和第二多层的界面处不形成含有由第一多晶硅层暴露于含氧气氛的氧化硅的杂质。

8. 发明授权

US07232724B1 Radical oxidation for bitline oxide of SONOS 有权
标题翻译： SONOS的位线氧化物的自由基氧化
公开(公告)号：US07232724B1
公开(公告)日：2007-06-19
申请号：US11113507
申请日：2005-04-25
申请人： Hidehiko Shiraiwa , Joong Jeon , Weidong Qian
发明人： Hidehiko Shiraiwa , Joong Jeon , Weidong Qian
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： Methods are disclosed for fabricating multi-bit SONOS flash memory cells, comprising forming a first dielectric layer and a charge trapping layer over a substrate of a wafer and selectively etching the dielectric and charge trapping layers down to a substrate region to form a bitline opening, then implanting a dopant ion species into the substrate associated with the bitline opening in a bitline region. A radical oxidation process is then used to form a second dielectric layer of a triple layer dielectric-charge trapping-dielectric stack over the charge trapping layer and to fill the bitline opening in the bitline regions of the wafer. Finally, a wordline structure is then formed over the triple layer dielectric-charge trapping-dielectric stack and the bitline regions of the wafer. A multi-bit flash memory array is also disclosed, comprising a bitline region in a substrate, a first dielectric layer overlying the substrate substantially adjacent to and substantially exposing the bitline region, a charge trapping layer overlying the first dielectric layer substantially adjacent to and substantially exposing the bitline region, a bitline oxide isolation structure or layer extending continuously over the bitline region and charge trapping layer, the isolation structure comprising a single dielectric material layer formed by the radical oxidation process, and a conductive wordline overlying the bitline oxide isolation structure or layer.
摘要翻译：公开了用于制造多位SONOS闪速存储器单元的方法，包括在晶片的衬底上形成第一介电层和电荷俘获层，并选择性地蚀刻电介质并将陷阱层电荷捕获到衬底区域以形成位线开口，然后将掺杂剂离子物质注入与位线区域中的位线开口相关联的衬底中。然后使用自由基氧化工艺在电荷俘获层上形成三层介电电荷俘获 - 电介质堆叠的第二介电层，并填充晶片的位线区域中的位线开口。最后，在三层介电 - 电荷俘获 - 电介质堆叠和晶片的位线区域之后形成字线结构。还公开了一种多位闪存阵列，其包括衬底中的位线区域，覆盖衬底的基本上邻近并基本上暴露位线区域的第一电介质层，覆盖第一电介质层的电荷俘获层，其基本上邻近于并且基本上暴露位线区域，位线氧化物隔离结构或层，其在位线区域和电荷捕获层上连续延伸，所述隔离结构包括通过自由基氧化过程形成的单个电介质材料层，以及覆盖位线氧化物隔离结构的导电字线，层。

9. 发明授权

US06621114B1 MOS transistors with high-k dielectric gate insulator for reducing remote scattering 有权
标题翻译：具有高k介质栅极绝缘体的MOS晶体管，用于减少远程散射
公开(公告)号：US06621114B1
公开(公告)日：2003-09-16
申请号：US10151269
申请日：2002-05-20
申请人： Hyeon-Seag Kim , Joong Jeon
发明人： Hyeon-Seag Kim , Joong Jeon
IPC分类号： H01L27108
CPC分类号： H01L21/28194 , H01L29/4916 , H01L29/495 , H01L29/513 , H01L29/517 , Y10S977/881
摘要： The present invention relates to a MOS transistor structure and method of manufacture which provides a high-k dielectric gate insulator for reduced gate current leakage while concurrently reducing remote scattering, thereby improving transistor carrier mobility.
摘要翻译：本发明涉及一种MOS晶体管结构及其制造方法，其提供高k介电栅极绝缘体，以减少栅极电流泄漏，同时减少远程散射，从而提高晶体管载流子迁移率。

10. 发明授权

US06607973B1 Preparation of high-k nitride silicate layers by cyclic molecular layer deposition 有权
标题翻译：通过循环分子层沉积制备高k氮化硅硅酸盐层
公开(公告)号：US06607973B1
公开(公告)日：2003-08-19
申请号：US10244204
申请日：2002-09-16
申请人： Joong Jeon
发明人： Joong Jeon
IPC分类号： H01L213205
CPC分类号： H01L21/28185 , C23C16/308 , C23C16/401 , C23C16/45525 , C23C16/45531 , H01L21/28194 , H01L21/3141 , H01L21/3142 , H01L21/3143 , H01L21/31604 , H01L21/31612 , H01L21/31645 , H01L29/517 , H01L29/518
摘要： One aspect of the invention relates to forming a high-k dielectric layer comprising a Group IVB metal compound, especially HfO2, HfSixOy or HfSixOyNz. According to the invention, these compounds are formed by molecular layer deposition. According to another aspect of the invention, molecular layer deposition is used to add silicon oxynitride to the dielectric. The silicon oxynitride provides a barrier to diffusion of dopants from the gate to the channel region.
摘要翻译：本发明的一个方面涉及形成包含第ⅣB族金属化合物，特别是HfO 2，Hf x Si x O y或Hf x X y N z的高k电介质层。根据本发明，通过分子层沉积形成这些化合物。根据本发明的另一方面，使用分子层沉积将氧氮化硅添加到电介质中。氮氧化硅为掺杂剂从栅极扩散到沟道区提供了阻碍。

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