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1. 发明授权

US07049201B2 Method and apparatus for a heterojunction bipolar transistor using self-aligned epitaxy 有权
标题翻译：使用自对准外延的异质结双极晶体管的方法和装置
公开(公告)号：US07049201B2
公开(公告)日：2006-05-23
申请号：US10703297
申请日：2003-11-06
申请人： Purakh Raj Verma , Shao-Fu Sanford Chu , Lap Chan , Jian Xun Li , Jia Zhen Zheng
发明人： Purakh Raj Verma , Shao-Fu Sanford Chu , Lap Chan , Jian Xun Li , Jia Zhen Zheng
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, a number of insulating layers over the semiconductor substrate, at least one of the number of insulating layers having a base cavity over the collector region, a base structure of a compound semiconductive material in the base cavity, a window in the insulating layer over the base cavity, an emitter structure in the window, an interlevel dielectric layer, and connections through the interlevel dielectric layer to the base structure, the emitter structure, and the collector region. The base structure and the emitter structure preferably are formed in the same processing chamber.
摘要翻译：一种异质结双极晶体管（HBT）及其制造方法，包括具有集电极区域，半导体衬底上的多个绝缘层的半导体衬底，在集电极区域上具有基腔的多个绝缘层中的至少一个，基腔中的复合半导体材料的基底结构，在基底腔上的绝缘层中的窗口，窗口中的发射极结构，层间介电层以及通过层间介电层到基底结构的连接，发射极结构和收集器区域。基底结构和发射极结构优选地形成在相同的处理室中。

2. 发明授权

US06372652B1 Method for forming a thin-film, electrically blowable fuse with a reproducible blowing wattage 有权
标题翻译：用可重现的吹制瓦数形成薄膜可电熔熔断器的方法
公开(公告)号：US06372652B1
公开(公告)日：2002-04-16
申请号：US09494633
申请日：2000-01-31
申请人： Purakh Raj Verma , Zia Alan Shafi , Yu Shan , Zeng Zheng , Manju Sarkar , Shao-Fu Sanford Chu
发明人： Purakh Raj Verma , Zia Alan Shafi , Yu Shan , Zeng Zheng , Manju Sarkar , Shao-Fu Sanford Chu
IPC分类号： H01L21302
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a thin film, electrically blowable fuse with reproducible blowing wattage using a sacrificial metal patch over a fuse dielectric layer and two etch processes; wherein the first etch process is selective to the metal patch and the second etch process is selective to the fuse dielectric layer. A fuse element, having an element width, is formed over a semiconductor structure, and a fuse dielectric layer is formed over the fuse element. A sacrificial metal patch is formed on the fuse dielectric layer; wherein the patch width being greater than the fuse element width. A second dielectric layer is formed on the sacrificial metal patch, and additional metal layers and dielectric layers may be formed over the second dielectric layer, but only the dielectric layers will remain over the fuse element. The second dielectric layer and any overlying dielectric layers are patterned to form a fuse window opening, having a width greater than the sacrificial metal patch, using a first fuse window etch selective to the sacrificial metal patch. Then, the sacrificial metal patch is etched through the fuse window opening using a second fuse window etch selective to the fuse dielectric layer, leaving a reproducible thickness of the fuse dielectric layer overlying the fuse element; thereby providing a reproducible blowing wattage.
摘要翻译：一种用于在熔丝电介质层和两个蚀刻工艺上使用牺牲金属贴片形成具有可再现的吹扫功率的薄膜电可熔电熔丝的方法; 其中所述第一蚀刻工艺对所述金属贴片是选择性的，并且所述第二蚀刻工艺对所述熔丝电介质层是选择性的。在半导体结构上形成具有元件宽度的熔丝元件，并且在保险丝元件上形成熔丝电介质层。在熔丝绝缘层上形成牺牲金属贴片; 其中所述贴片宽度大于所述熔丝元件宽度。在牺牲金属贴片上形成第二电介质层，并且可以在第二电介质层上形成附加的金属层和电介质层，但是只有电介质层将保留在熔丝元件上方。使用对牺牲金属贴片选择性的第一熔丝窗口蚀刻，将第二电介质层和任何上覆电介质层图案化以形成具有大于牺牲金属贴片的宽度的熔丝窗口。然后，使用对熔丝电介质层选择性的第二熔丝窗蚀刻，通过熔丝窗口蚀刻牺牲金属贴片，留下覆于熔丝元件上的熔丝电介质层的可再现厚度; 从而提供可重复的吹制瓦数。

3. 发明授权

US06489191B2 Method for forming self-aligned channel implants using a gate poly reverse mask 失效
标题翻译：使用栅极多反向掩模形成自对准沟道植入物的方法
公开(公告)号：US06489191B2
公开(公告)日：2002-12-03
申请号：US10140571
申请日：2002-05-08
申请人： Kai Shao , Yimin Wang , Jian Xun Li , Shao-Fu Sanford Chu
发明人： Kai Shao , Yimin Wang , Jian Xun Li , Shao-Fu Sanford Chu
IPC分类号： H01L218238
CPC分类号： H01L21/823807 , Y10S977/712
摘要： A method for forming a CMOS transistor gate with a self-aligned. channel implant. A semiconductor structure having a first active area is provided. A first insulating layer is formed on the semiconductor structure, and a second insulating layer is formed on the first insulating layer. The second insulating layer is patterned using a poly reverse mask and an etch selective to the first insulating layer to form a first channel implant opening, and the poly reverse mask is removed. A first channel implant mask is formed exposing the first channel implant opening. Impurity ions are implanted through the first channel implant opening to form a first threshhold adjust region and a first anti-punchthrough region. A gate layer is formed over the semiconductor structure, and the first gate layer is planarized to form a gate electrode. The second insulating layer is removed, and lightly doped source and drain regions, sidewall spacers and source and drain regions can be formed adjacent the gate electrode.
摘要翻译：一种用于形成具有自对准的CMOS晶体管栅极的方法。通道植入。提供具有第一有源区的半导体结构。在半导体结构上形成第一绝缘层，在第一绝缘层上形成第二绝缘层。使用多反向掩模和对第一绝缘层选择性地蚀刻第二绝缘层以形成第一沟道注入开口，并且去除多反向掩模。形成暴露第一通道植入物开口的第一通道植入物掩模。通过第一通道植入物开口注入杂质离子以形成第一阈值调整区域和第一抗穿透区域。在半导体结构上形成栅极层，并且第一栅极层被平坦化以形成栅电极。去除第二绝缘层，并且可以在栅电极附近形成轻掺杂的源极和漏极区域，侧壁间隔物和源极和漏极区域。

4. 发明授权

US06410394B1 Method for forming self-aligned channel implants using a gate poly reverse mask 失效
标题翻译：使用栅极多反向掩模形成自对准沟道植入物的方法
公开(公告)号：US06410394B1
公开(公告)日：2002-06-25
申请号：US09465305
申请日：1999-12-17
申请人： Kai Shao , Yimin Wang , Jian Xun Li , Shao-Fu Sanford Chu
发明人： Kai Shao , Yimin Wang , Jian Xun Li , Shao-Fu Sanford Chu
IPC分类号： H01L21336
CPC分类号： H01L21/823807 , Y10S977/712
摘要： A method for forming a CMOS transistor gate with a self-aligned channel implant. A semiconductor structure having a first active area is provided. A first insulating layer is formed on the semiconductor structure, and a second insulating layer is formed on the first insulating layer. The second insulating layer is patterned using a poly reverse mask and an etch selective to the first insulating layer to form a first channel implant opening, and the poly reverse mask is removed. A first channel implant mask is formed exposing the first channel implant opening. Impurity ions are implanted through the first channel implant opening to form a first threshold adjust region and a first anti-punchthrough region. A gate layer is formed over the semiconductor structure, and the first gate layer is planarized to form a gate electrode. The second insulating layer is removed, and lightly doped source and drain regions, sidewall spacers and source and drain regions can be formed adjacent the gate electrode.
摘要翻译：一种用于形成具有自对准沟道植入物的CMOS晶体管栅极的方法。提供具有第一有源区的半导体结构。在半导体结构上形成第一绝缘层，在第一绝缘层上形成第二绝缘层。使用多反向掩模和对第一绝缘层选择性地蚀刻第二绝缘层以形成第一沟道注入开口，并且去除多反向掩模。形成暴露第一通道植入物开口的第一通道植入物掩模。杂质离子通过第一通道注入开口注入，以形成第一阈值调整区域和第一抗穿通区域。在半导体结构上形成栅极层，并且第一栅极层被平坦化以形成栅电极。去除第二绝缘层，并且可以在栅电极附近形成轻掺杂的源极和漏极区域，侧壁间隔物和源极和漏极区域。

5. 发明授权

US6133079A Method for reducing substrate capacitive coupling of a thin film inductor by reverse P/N junctions 失效
标题翻译：通过反向P / N结减少薄膜电感器的衬底电容耦合的方法
公开(公告)号：US6133079A
公开(公告)日：2000-10-17
申请号：US358985
申请日：1999-07-22
申请人： Min Zhu , Kai Shao , Shao-Fu Sanford Chu
发明人： Min Zhu , Kai Shao , Shao-Fu Sanford Chu
IPC分类号： H01L21/02 , H01L23/522 , H01L27/06 , H01L27/08 , H01L21/8238
CPC分类号： H01L28/10 , H01L23/5227 , H01L27/0688 , H01L27/08 , H01L2924/0002
摘要： A method for reducing the capacitive coupling of an inductor on an integrated circuit chip is described. The method forms the inductor over an accumulation of dielectric layers used elsewhere in the integrated circuit. In addition two back-to-back reversed p/n junctions are formed within the silicon substrate below the inductor. The junctions are serially connected and, along with the capacitance of the dielectric layers, reduce the capacitive coupling of the inductor to the substrate by a factor of between about 2 and 20 over the that of the dielectric layers alone. The decrease in capacitance improves the performance of the inductor at high operating frequencies, for example, above1 GHz. The junctions are easily formed in a twin-well CMOS circuit by the addition of only a single additional processing step. The additional step comprises the deep implantation of phosphorous to form an n-type zone between the p-well and the substrate in the region over which the inductor is formed. The junctions are not externally biased and sustain continuous depletion regions between the inductor and the substrate.
摘要翻译：描述了用于减小集成电路芯片上的电感器的电容耦合的方法。该方法在集成电路中的其他地方使用的介电层的积累形成电感器。此外，在电感器下面的硅衬底内形成两个背靠背的反向p / n结。接头串联连接，并且与电介质层的电容一起，使电感器与衬底的电容耦合比单独的电介质层的耦合减小约2至20倍。电容的减小改善了高工作频率下电感器的性能，例如高于1GHz。通过添加仅一个附加的处理步骤，可以在双阱CMOS电路中容易地形成结。附加步骤包括在形成电感器的区域中深度注入磷以在p阱和衬底之间形成n型区。接点不是外部偏置的，并且在电感器和衬底之间维持连续的耗尽区。

6. 发明授权

US6124194A Method of fabrication of anti-fuse integrated with dual damascene process 有权
标题翻译：与双镶嵌工艺集成的抗熔丝的制造方法
公开(公告)号：US6124194A
公开(公告)日：2000-09-26
申请号：US439365
申请日：1999-11-15
申请人： Kai Shao , Yi Xu , Cerdin Lee , Shao-Fu Sanford Chu
发明人： Kai Shao , Yi Xu , Cerdin Lee , Shao-Fu Sanford Chu
IPC分类号： H01L21/768 , H01L23/525 , H07L29/00
CPC分类号： H01L21/7681 , H01L23/5252 , H01L2924/0002
摘要： A method of fabricating an anti-fuse module and dual damascene interconnect structure comprises the following steps. A semiconductor structure having at least two exposed metal lines covered by a first dielectric layer is provided. A first metal line is within an anti-fuse area and a second metal line is within an interconnect area. A first metal via is formed within the first dielectric layer within the anti-fuse area with the first metal via contacting the first metal line. A SiN layer is deposited over the first dielectric layer and the first metal via. The SiN layer is patterned to form at least two openings. A first opening exposes the first metal via, and a second opening exposes a portion of the first dielectric layer above the second metal line. A fusing element layer is deposited and patterned over the patterned SiN layered structure to form a fusing element over the first metal via. Simultaneously, an anti-fuse metal line is formed over the fusing element to form an anti-fuse module within the anti-fuse area, and a dual damascene interconnect is formed over, and contacting with, the second metal line and within the interconnect area.
摘要翻译：一种制造抗熔丝模块和双镶嵌互连结构的方法包括以下步骤。提供具有被第一介电层覆盖的至少两个暴露的金属线的半导体结构。第一金属线在反熔丝区内，第二金属线在互连区内。第一金属通孔形成在反熔丝区域内的第一电介质层内，第一金属通孔接触第一金属线。在第一介电层和第一金属通孔上沉积SiN层。图案化SiN层以形成至少两个开口。第一开口暴露第一金属通孔，第二开口暴露第二电介质层的第二金属线上方的一部分。在图案化的SiN层状结构上沉积并图案化定影元件层，以在第一金属通孔之上形成定影元件。同时，在熔断元件上方形成抗熔丝金属线，以在反熔丝区域内形成反熔丝模块，并且在第二金属线之间和互连区内形成双面镶嵌互连。

7. 发明授权

US5874764A Modular MOSFETS for high aspect ratio applications 失效
标题翻译：用于高宽高比应用的模块化MOSFET
公开(公告)号：US5874764A
公开(公告)日：1999-02-23
申请号：US685792
申请日：1996-07-24
申请人： Chang-Ming Hsieh , Somnuk Ratanaphanyarat , Shao-Fu Sanford Chu , Louis Lu-chen Hsu
发明人： Chang-Ming Hsieh , Somnuk Ratanaphanyarat , Shao-Fu Sanford Chu , Louis Lu-chen Hsu
IPC分类号： H01L21/8234 , H01L27/02 , H01L27/088 , H01L27/118
CPC分类号： H01L21/823475 , H01L21/823425 , H01L27/0203 , H01L27/088 , Y10S148/055
摘要： An improved design for high aspect ratio MOS devices is capable of 100% yields. The design is suitable for low voltage CMOS devices, such as microprocessors, which use the high aspect ratio MOS devices in embedded applications, and for HEMTs in high frequency applications, such as high power microwave devices. The high yields reduce manufacturing costs. A modular MOS concept is introduced to realize the 100% yield of large channel width devices. The structure of the modular MOS device is a regular MOS device with a unit device channel width. This can be a multi-finger device which has a proper dimension to be able to fit in a given layout area. Therefore, the number of modules which are needed to form a full large width device is not only determined by module size, but also on the manufacturing yield record, allowed chip real estate and performance requirement.
摘要翻译：高纵横比MOS器件的改进设计能够获得100％的产量。该设计适用于诸如微处理器的低电压CMOS器件，其使用嵌入式应用中的高纵横比MOS器件，以及用于诸如高功率微波器件的高频应用中的HEMT。高产量降低了制造成本。引入模块化MOS概念，实现大通道宽度器件的100％产量。模块化MOS器件的结构是具有单位器件沟道宽度的常规MOS器件。这可以是具有适当尺寸以能够适应给定布局区域的多指装置。因此，形成全宽度器件所需的模块数量不仅取决于模块尺寸，还取决于制造产量记录，芯片的可用性和性能要求。

8. 发明授权

US06297132B1 Process to control the lateral doping profile of an implanted channel region 有权
标题翻译：控制植入通道区域的横向掺杂分布的方法
公开(公告)号：US06297132B1
公开(公告)日：2001-10-02
申请号：US09498978
申请日：2000-02-07
申请人： Jiong Zhang , Kai Shao , Shao-Fu Sanford Chu
发明人： Jiong Zhang , Kai Shao , Shao-Fu Sanford Chu
IPC分类号： H01L21425
CPC分类号： H01L29/66537 , H01L29/66553 , H01L29/6659 , H01L29/7833
摘要： A process for fabricating a MOSFET device, featuring a narrow lateral delta doping, or a narrow anti-punchthrough region, located in the center of the MOSFET channel region, has been developed. The process features formation of the narrow, anti-punchthrough region, via use of an ion implantation procedure, performed using an opening, comprised with sidewall spacers, as an implant mask. After formation of the narrow, anti-punchthrough region, the sidewall spacers are removed, and a gate insulator layer, and a polysilicon gate structure, are formed in the spacerless opening, defining a channel region wider than the narrow, anti-punchthrough region.
摘要翻译：已经开发了一种制造MOSFET器件的工艺，其具有窄的侧向delta掺杂或位于MOSFET沟道区域的中心的窄反穿通区域。该方法的特征在于，通过使用离子注入程序，使用包括侧壁间隔件的开口作为植入物掩模来执行窄的抗穿透区域的形成。在形成窄的防穿透区域之后，去除侧壁间隔物，并且在无间隔开口中形成栅极绝缘体层和多晶硅栅极结构，限定比窄的反穿通区域宽的沟道区域。

9. 发明授权

US06284590B1 Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors 有权
标题翻译：用于MIM电容器的底金属图案化期间消除顶部金属角成形的方法
公开(公告)号：US06284590B1
公开(公告)日：2001-09-04
申请号：US09726655
申请日：2000-11-30
申请人： Randall Cher Liang Cha , Cheng Yeow Ng , Shao-Fu Sanford Chu , Tae Jong Lee , Chua Chee Tee
发明人： Randall Cher Liang Cha , Cheng Yeow Ng , Shao-Fu Sanford Chu , Tae Jong Lee , Chua Chee Tee
IPC分类号： H01L218242
CPC分类号： H01L28/40 , H01L21/32139 , H01L28/60 , Y10S438/957
摘要： A method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated is described. An insulating layer is provided overlying a semiconductor substrate. A first metal layer is deposited over the insulating layer. A capacitor dielectric layer is deposited overlying the first metal layer. A second metal layer is deposited overlying the capacitor dielectric layer and patterned to form a top metal electrode. A flowable material layer is deposited overlying the capacitor dielectric and the top metal electrode and anisotropically etched away to leave spacers on sidewalls of the top metal electrode. A photoresist mask is formed overlying the capacitor dielectric and the top metal electrode wherein the spacers provide extra photoresist thickness at the sidewalls of the top metal layer. The capacitor dielectric layer and the first metal layer are patterned wherein the patterned first metal layer forms a bottom metal electrode and wherein the spacers protect the top metal layer from etching during the patterning. The photoresist mask is removed, completing fabrication of a metal-insulator-metal capacitor.
摘要翻译：描述了一种用于制造金属 - 绝缘体 - 金属电容器的方法，其中消除了图案化期间的顶部金属角成形。绝缘层设置在半导体衬底上。第一金属层沉积在绝缘层上。沉积在第一金属层上的电容器电介质层。将第二金属层沉积在电容器介电层上并被图案化以形成顶部金属电极。将可流动材料层沉积在电容器电介质和顶部金属电极上，并各向异性地蚀刻掉，以在顶部金属电极的侧壁上留下间隔物。形成覆盖电容器电介质和顶部金属电极的光致抗蚀剂掩模，其中间隔物在顶部金属层的侧壁处提供额外的光致抗蚀剂厚度。电容器电介质层和第一金属层被图案化，其中图案化的第一金属层形成底部金属电极，并且其中间隔件在图案化期间保护顶部金属层不被蚀刻。去除光致抗蚀剂掩模，完成金属 - 绝缘体 - 金属电容器的制造。

10. 发明授权

US6156602A Self-aligned precise high sheet RHO register for mixed-signal application 失效
标题翻译：自对准精密高片材RHO电阻，用于混合信号应用
公开(公告)号：US6156602A
公开(公告)日：2000-12-05
申请号：US368859
申请日：1999-08-06
申请人： Kai Shao , Shao-Fu Sanford Chu , Cerdin Lee
发明人： Kai Shao , Shao-Fu Sanford Chu , Cerdin Lee
IPC分类号： H01L21/02 , H01L27/06 , H01L21/8234
CPC分类号： H01L27/0629 , H01L28/56
摘要： A new method is provided for the creation of a resistive load in a semiconductor device whereby the semiconductor device further contains gate electrodes and a capacitor. Field isolation regions separate the active areas; a thin layer of gate oxide is created over these active regions. A first layer of poly is deposited, used for the gate electrode, for the bottom plate of the adjacent capacitor and for the resistor of high ohmic value. The gate poly is doped (in the first layer of poly); optionally the bottom plate of the capacitor can be doped. A dielectric layer is deposited for the dielectric of the capacitor; a second layer of poly is deposited, patterned and etched to form the capacitor top plate. The capacitor (dielectric and bottom plate), poly gates and the load resistor are patterned; the LDD regions for the transistors are created. The (gate, capacitor, resistor) spacers are formed, during and as part of the etch of the gate spacers a resistive spacer (called spacer since it serves to space or separate the two contact points of the resistor) is formed. The source/drain implants for the gate electrodes are performed thereby concurrently performing (self-aligned, due to the resistor spacer) implants for the contact regions of the resistor. All contacts (gate poly, source/drain and two contact points on the resistor) are salicided to achieve lower contact resistance.
摘要翻译：提供了一种用于在半导体器件中产生电阻性负载的新方法，由此半导体器件还包含栅电极和电容器。现场隔离区分开活动区域; 在这些活性区域上形成薄层的栅极氧化物。沉积第一层poly，用于栅电极，用于相邻电容器的底板和高欧姆值的电阻。掺杂多晶硅（在第一层聚合物中）; 可选地，可以掺杂电容器的底板。为电容器的电介质沉积电介质层; 沉积第二层多晶硅，进行图案化和蚀刻以形成电容器顶板。电容器（电介质和底板），多晶硅栅极和负载电阻器被图案化; 产生晶体管的LDD区域。形成（栅极，电容器，电阻器）间隔物，在蚀刻栅极隔离物期间和作为蚀刻的一部分期间，形成电阻隔离物（称为间隔物，因为其用于空间或分离电阻器的两个接触点）。执行栅电极的源极/漏极注入，由此同时对电阻器的接触区域进行（由于电阻器隔离物而自对准）植入物。所有触点（栅极多晶硅，源极/漏极和电阻上的两个接触点）都被浸渍以实现较低的接触电阻。

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