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1. 发明申请

US20050059216A1 METHOD OF MAKING DIRECT CONTACT ON GATE BY USING DIELECTRIC STOP LAYER 失效
标题翻译：通过使用介质停止层在门上制造直接接触的方法
公开(公告)号：US20050059216A1
公开(公告)日：2005-03-17
申请号：US10664211
申请日：2003-09-17
申请人： Purakh Verma , Sanford Chu , Lap Chan , Yelehanka Ramachandramurthy Pradeep , Kai Shao , Jia Zheng
发明人： Purakh Verma , Sanford Chu , Lap Chan , Yelehanka Ramachandramurthy Pradeep , Kai Shao , Jia Zheng
IPC分类号： H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/768 , H01L21/84 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76802 , H01L21/76829
摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (f.,), and reduced gate delay.
摘要翻译：描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作时的噪声性能，增加的单位功率增益频率（f。）和减小的栅极延迟。

2. 发明授权

US06861317B1 Method of making direct contact on gate by using dielectric stop layer 失效
标题翻译：通过使用介电阻挡层在栅极上直接接触的方法
公开(公告)号：US06861317B1
公开(公告)日：2005-03-01
申请号：US10664211
申请日：2003-09-17
申请人： Purakh Raj Verma , Sanford Chu , Lap Chan , Yelehanka Pradeep , Kai Shao , Jia Zhen Zheng
发明人： Purakh Raj Verma , Sanford Chu , Lap Chan , Yelehanka Pradeep , Kai Shao , Jia Zhen Zheng
IPC分类号： H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/768 , H01L21/84 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76802 , H01L21/76829
摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.
摘要翻译：描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作时的噪声性能，增加的单位功率增益频率（fmax）和减小的栅极延迟。

3. 发明授权

US06291307B1 Method and structure to make planar analog capacitor on the top of a STI structure 失效
标题翻译：在STI结构顶部制作平面模拟电容的方法和结构
公开(公告)号：US06291307B1
公开(公告)日：2001-09-18
申请号：US09368863
申请日：1999-08-06
申请人： Shao-Fu Sanford Chu , Yang Pan , Wang Yimin , Kai Shao
发明人： Shao-Fu Sanford Chu , Yang Pan , Wang Yimin , Kai Shao
IPC分类号： H01L2120
CPC分类号： H01L28/40 , H01L21/76224 , H01L27/0629
摘要： A new method is provided to create a capacitor over the surface of STI regions. The STI regions are first created in the surface of the substrate, a layer of sacrificial oxide is next blanket deposited over the substrate (thereby including the surface of the created STI regions). A depletion stop region overlying densely spaced STI regions is formed in the surface of the substrate by N+ ion implantation, N-well and P-well regions are formed surrounding the depletion stop region. An insulation layer is deposited. The sacrificial oxide and insulation layers are patterned and etched leaving the sacrificial oxide and the insulation layer in place where the capacitor is to be created. A layer of gate oxide is formed over the surface of the substrate, a layer of poly 2 is deposited for the bottom plate and the gate electrode. The conductivity of the gate electrode and the bottom plate of the capacitor is established by performing a selective N+ implant into the layer of poly 2 where the gate electrode and the bottom plate of the capacitor are to be formed. A layer of dielectric is deposited for the capacitor dielectric, a layer of in-situ doped poly 3 is deposited for the top plate of the capacitor. The layers of poly 3, dielectric and poly 2 are etched forming the capacitor structure and the gate electrode structure.
摘要翻译：提供了一种新的方法来在STI区域的表面上形成电容器。首先在衬底的表面中形成STI区，然后在衬底上沉积一层牺牲氧化物（从而包括所产生的STI区的表面）。通过N +离子注入在衬底的表面中形成覆盖密集间隔的STI区的耗尽阻挡区，在耗尽阻挡区周围形成N阱和P阱区。沉积绝缘层。牺牲氧化物和绝缘层被图案化和蚀刻，留下牺牲氧化物和绝缘层到位于要产生电容器的位置。在衬底的表面上形成栅极氧化层，为了沉积底层和栅电极，淀积一层聚二氧化硅。通过对形成电容器的栅电极和底板的poly 2层进行选择性N +注入来建立电容器的栅电极和底板的导电性。为电容器电介质沉积一层电介质，为电容器的顶板沉积一层原位掺杂的poly 3。蚀刻形成电容器结构和栅极电极结构的聚3，电介质和聚合物2的层。

4. 发明授权

US06284594B1 Formation of an interpoly capacitor structure using a chemical mechanical polishing procedure 失效
标题翻译：使用化学机械抛光程序形成多层电容器结构
公开(公告)号：US06284594B1
公开(公告)日：2001-09-04
申请号：US09580607
申请日：2000-05-30
申请人： Yong Ju , Kai Shao , Yimin Wang , Shao-Fu Sanford Chu
发明人： Yong Ju , Kai Shao , Yimin Wang , Shao-Fu Sanford Chu
IPC分类号： H01L218242
CPC分类号： H01L27/0629 , H01L21/3144 , H01L28/40
摘要： A process for simultaneously forming a polysilicon gate structure, for a transfer gate transistor, and a polysilicon top plate, for a capacitor structure, on an underlying planar surface, has been developed. The process features the formation of a polysilicon bottom plate, for the capacitor structure, embedded in a first opening in composite insulator layer, and the formation of an active device region, for a transfer gate transistor structure, via the selective growth of an epitaxial silicon layer, in a second opening of the composite insulator layer, resulting in a planar top surface topography. The presence of this topography reduces the risk of residual polysilicon, present after patterning of the polysilicon gate structure, and of the capacitor, polysilicon top plate.
摘要翻译：已经开发了用于在底层平面上形成用于电容器结构的传输栅极晶体管和多晶硅顶板的多晶硅栅极结构的工艺。该方法的特征在于形成多晶硅底板，用于电容器结构，嵌入在复合绝缘体层中的第一开口中，并且通过外延硅的选择性生长形成用于传输栅晶体管结构的有源器件区层，在复合绝缘体层的第二开口中，产生平坦的顶表面形貌。这种形貌的存在降低了在多晶硅栅极结构图案化之后存在的残余多晶硅以及电容器，多晶硅顶板的风险。

5. 发明授权

US6159759A Method to form liquid crystal displays using a triple damascene technique 有权
标题翻译：使用三重镶嵌技术形成液晶显示器的方法
公开(公告)号：US6159759A
公开(公告)日：2000-12-12
申请号：US443423
申请日：1999-11-19
申请人： Kai Shao , Cerdin Lee , Yi Xu , Shao-Fu Sanford Chu
发明人： Kai Shao , Cerdin Lee , Yi Xu , Shao-Fu Sanford Chu
IPC分类号： G02F1/1335 , G02F1/1362 , H01L21/00
CPC分类号： G02F1/133553 , G02F1/136277
摘要： A new method of forming liquid crystal displays has been achieved. Metal conductors are provided in an insulating layer overlying a semiconductor substrate. A first isolation layer is deposited. A first silicon nitride layer is deposited. The first silicon nitride layer is patterned to form openings for planned vias overlying the metal conductors. A second isolation layer is deposited. A second silicon nitride layer is deposited. The second silicon nitride layer is patterned to form masks overlying where dummy supports for the metal pixels are planned and to form openings to extend the planned vias. A third isolation layer is deposited. The third isolation layer is patterned to form openings for the planned metal pixels. The second isolation layer and the first isolation layer are etched through to complete the vias and the dummy supports. A metal layer is deposited filling the openings for the metal pixels, the dummy support, and the vias. The metal layer is polished down to the top surface of the third isolation layer to complete the metal pixels. A thin film passivation is deposited. A liquid crystal layer is deposited. A transparent image point electrode is formed to complete the liquid crystal display.
摘要翻译：已经实现了一种形成液晶显示器的新方法。金属导体设置在覆盖半导体衬底的绝缘层中。沉积第一隔离层。沉积第一氮化硅层。图案化第一氮化硅层以形成覆盖金属导体的计划通孔的开口。沉积第二隔离层。沉积第二氮化硅层。图案化第二氮化硅层以形成掩模，覆盖着金属像素的虚拟支撑被设计并形成扩展计划的通孔的开口。沉积第三个隔离层。图案化第三隔离层以形成用于计划的金属像素的开口。蚀刻第二隔离层和第一隔离层以完成通孔和虚拟支撑。沉积金属层，填充用于金属像素，虚拟支撑件和通孔的开口。金属层被抛光到第三隔离层的顶表面以完成金属像素。沉积薄膜钝化。沉积液晶层。形成透明图像点电极以完成液晶显示器。

6. 发明授权

US6117747A Integration of MOM capacitor into dual damascene process 有权
标题翻译：将MOM电容器集成到双镶嵌工艺中
公开(公告)号：US6117747A
公开(公告)日：2000-09-12
申请号：US435436
申请日：1999-11-22
申请人： Kai Shao , Yi Xu , Cerdin Lee , Shao-Fu Sanford Chu
发明人： Kai Shao , Yi Xu , Cerdin Lee , Shao-Fu Sanford Chu
IPC分类号： H01L21/02 , H01L21/768 , H01L21/20
CPC分类号： H01L28/40 , H01L21/76838 , H01L28/60
摘要： A method for fabricating a metal-oxide-metal capacitor using a dual damascene process is described. A dielectric layer is provided overlying a semiconductor substrate. A dual damascene opening in the dielectric layer is filled with copper to form a copper via underlying a copper line. A first metal layer is deposited overlying the copper line and patterned to form a bottom capacitor plate contacting the copper line. A capacitor dielectric layer is deposited overlying the bottom capacitor plate. A second metal layer is deposited overlying the capacitor dielectric layer and patterned to form a top capacitor plate to complete fabrication of a metal-oxide-metal capacitor.
摘要翻译：描述了使用双镶嵌工艺制造金属氧化物 - 金属电容器的方法。提供覆盖在半导体衬底上的电介质层。电介质层中的双镶嵌开口填充有铜，通过铜线下方形成铜。沉积在铜线上的第一金属层被图案化以形成接触铜线的底部电容器板。电容器电介质层沉积在底部电容器板上。将第二金属层沉积在电容器介电层上并被图案化以形成顶部电容器板，以完成金属氧化物 - 金属电容器的制造。

7. 发明申请

US20100307688A1 TAG ABLATION MECHANISM AND TAG-AND-TAPE COMBINATION APPARATUS USING THE SAME 有权
标题翻译：标签排列机制和标签与胶带组合设备
公开(公告)号：US20100307688A1
公开(公告)日：2010-12-09
申请号：US12621690
申请日：2009-11-19
申请人： KUEI-KAI SHAO , Pei-Chun Chen , Chen-Shen Liu , Chin-Lu Huang
发明人： KUEI-KAI SHAO , Pei-Chun Chen , Chen-Shen Liu , Chin-Lu Huang
IPC分类号： B32B38/00 , B32B43/00
CPC分类号： B65C1/025 , B65C11/004 , B65C2009/0003 , Y10T156/1195 , Y10T156/1343 , Y10T156/1707 , Y10T156/1795 , Y10T156/18 , Y10T156/1994
摘要： The present invention provides a tag ablation mechanism and a tag-and-tape combination apparatus using the same, wherein a driving gear is actuated to rotate by a rotating device by way of a lever to drive a driven gear to rotate so as to ablate a tag from a bottom paper extended from a tag roll on the driven gear. In the present invention, an ablated tag is capable of being combined with a tape so that the tag attached to the tape can be adhered to a packaged object. The mechanism and apparatus of the present invention are capable of adjusting a rotating arc length so as to handle various tags with different sizes and lengths and to complete tag ablation and tag-and-tape combination in each driving operation.
摘要翻译：本发明提供了一种标签消融机构和使用该标签消除机构的标签消毒机构和标签 - 带组合装置，其中驱动齿轮由转动装置致动以通过杆旋转以驱动从动齿轮旋转，以便消除标签从底部纸张上，从从动齿轮上的标签卷延伸。在本发明中，烧蚀标签能够与胶带组合，使得附着在胶带上的标签可以粘附到包装物上。本发明的机构和装置能够调节旋转弧长度，以便处理具有不同尺寸和长度的各种标签，并且在每个驱动操作中完成标签消融和标签 - 带组合。

8. 发明授权

US06489191B2 Method for forming self-aligned channel implants using a gate poly reverse mask 失效
标题翻译：使用栅极多反向掩模形成自对准沟道植入物的方法
公开(公告)号：US06489191B2
公开(公告)日：2002-12-03
申请号：US10140571
申请日：2002-05-08
申请人： Kai Shao , Yimin Wang , Jian Xun Li , Shao-Fu Sanford Chu
发明人： Kai Shao , Yimin Wang , Jian Xun Li , Shao-Fu Sanford Chu
IPC分类号： H01L218238
CPC分类号： H01L21/823807 , Y10S977/712
摘要： A method for forming a CMOS transistor gate with a self-aligned. channel implant. A semiconductor structure having a first active area is provided. A first insulating layer is formed on the semiconductor structure, and a second insulating layer is formed on the first insulating layer. The second insulating layer is patterned using a poly reverse mask and an etch selective to the first insulating layer to form a first channel implant opening, and the poly reverse mask is removed. A first channel implant mask is formed exposing the first channel implant opening. Impurity ions are implanted through the first channel implant opening to form a first threshhold adjust region and a first anti-punchthrough region. A gate layer is formed over the semiconductor structure, and the first gate layer is planarized to form a gate electrode. The second insulating layer is removed, and lightly doped source and drain regions, sidewall spacers and source and drain regions can be formed adjacent the gate electrode.
摘要翻译：一种用于形成具有自对准的CMOS晶体管栅极的方法。通道植入。提供具有第一有源区的半导体结构。在半导体结构上形成第一绝缘层，在第一绝缘层上形成第二绝缘层。使用多反向掩模和对第一绝缘层选择性地蚀刻第二绝缘层以形成第一沟道注入开口，并且去除多反向掩模。形成暴露第一通道植入物开口的第一通道植入物掩模。通过第一通道植入物开口注入杂质离子以形成第一阈值调整区域和第一抗穿透区域。在半导体结构上形成栅极层，并且第一栅极层被平坦化以形成栅电极。去除第二绝缘层，并且可以在栅电极附近形成轻掺杂的源极和漏极区域，侧壁间隔物和源极和漏极区域。

9. 发明授权

US08186409B2 Tag ablation mechanism and tag-and-tape combination apparatus using the same 有权
标题翻译：标签消融机构和使用其的标签和磁带组合装置
公开(公告)号：US08186409B2
公开(公告)日：2012-05-29
申请号：US12621690
申请日：2009-11-19
申请人： Kuei-Kai Shao , Pei-Chun Chen , Chen-Shen Liu , Chin-Lu Huang
发明人： Kuei-Kai Shao , Pei-Chun Chen , Chen-Shen Liu , Chin-Lu Huang
IPC分类号： B32B37/22
CPC分类号： B65C1/025 , B65C11/004 , B65C2009/0003 , Y10T156/1195 , Y10T156/1343 , Y10T156/1707 , Y10T156/1795 , Y10T156/18 , Y10T156/1994
摘要： The present invention provides a tag ablation mechanism and a tag-and-tape combination apparatus using the same, wherein a driving gear is actuated to rotate by a rotating device by way of a lever to drive a driven gear to rotate so as to ablate a tag from a bottom paper extended from a tag roll on the driven gear. In the present invention, an ablated tag is capable of being combined with a tape so that the tag attached to the tape can be adhered to a packaged object. The mechanism and apparatus of the present invention are capable of adjusting a rotating arc length so as to handle various tags with different sizes and lengths and to complete tag ablation and tag-and-tape combination in each driving operation.
摘要翻译：本发明提供了一种标签消融机构和使用该标签消除机构的标签消毒机构和标签 - 带组合装置，其中驱动齿轮由转动装置致动以通过杆旋转以驱动从动齿轮旋转，以便消除标签从底部纸张上，从从动齿轮上的标签卷延伸。在本发明中，烧蚀标签能够与胶带组合，使得附着在胶带上的标签可以粘附到包装物上。本发明的机构和装置能够调节旋转弧长度，以便处理具有不同尺寸和长度的各种标签，并且在每个驱动操作中完成标签消融和标签 - 带组合。

10. 发明授权

US06410394B1 Method for forming self-aligned channel implants using a gate poly reverse mask 失效
标题翻译：使用栅极多反向掩模形成自对准沟道植入物的方法
公开(公告)号：US06410394B1
公开(公告)日：2002-06-25
申请号：US09465305
申请日：1999-12-17
申请人： Kai Shao , Yimin Wang , Jian Xun Li , Shao-Fu Sanford Chu
发明人： Kai Shao , Yimin Wang , Jian Xun Li , Shao-Fu Sanford Chu
IPC分类号： H01L21336
CPC分类号： H01L21/823807 , Y10S977/712
摘要： A method for forming a CMOS transistor gate with a self-aligned channel implant. A semiconductor structure having a first active area is provided. A first insulating layer is formed on the semiconductor structure, and a second insulating layer is formed on the first insulating layer. The second insulating layer is patterned using a poly reverse mask and an etch selective to the first insulating layer to form a first channel implant opening, and the poly reverse mask is removed. A first channel implant mask is formed exposing the first channel implant opening. Impurity ions are implanted through the first channel implant opening to form a first threshold adjust region and a first anti-punchthrough region. A gate layer is formed over the semiconductor structure, and the first gate layer is planarized to form a gate electrode. The second insulating layer is removed, and lightly doped source and drain regions, sidewall spacers and source and drain regions can be formed adjacent the gate electrode.
摘要翻译：一种用于形成具有自对准沟道植入物的CMOS晶体管栅极的方法。提供具有第一有源区的半导体结构。在半导体结构上形成第一绝缘层，在第一绝缘层上形成第二绝缘层。使用多反向掩模和对第一绝缘层选择性地蚀刻第二绝缘层以形成第一沟道注入开口，并且去除多反向掩模。形成暴露第一通道植入物开口的第一通道植入物掩模。杂质离子通过第一通道注入开口注入，以形成第一阈值调整区域和第一抗穿通区域。在半导体结构上形成栅极层，并且第一栅极层被平坦化以形成栅电极。去除第二绝缘层，并且可以在栅电极附近形成轻掺杂的源极和漏极区域，侧壁间隔物和源极和漏极区域。

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