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1. 发明申请

US20090108875A1 Structure for a Limited Switch Dynamic Logic Cell Based Register 审中-公开
标题翻译：一种有限开关动态逻辑单元的寄存器结构
公开(公告)号：US20090108875A1
公开(公告)日：2009-04-30
申请号：US12174543
申请日：2008-07-16
申请人： Peter J. Klim , Jethro C. Law , Trong V. Luong , Abraham Mathews
发明人： Peter J. Klim , Jethro C. Law , Trong V. Luong , Abraham Mathews
IPC分类号： H03K19/096 , G06F17/50 , H03K19/00
CPC分类号： H03K19/0963
摘要： A design structure for a circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.
摘要翻译：具有具有前端逻辑电路和锁存器的有限开关动态逻辑门的电路的设计结构。前端逻辑电路的输出连接到锁存器的输入，前端逻辑电路评估施加到前端逻辑电路的一组输入信号以产生输出信号。锁存器接收并保持输出信号。电路还具有逻辑电路，其输出端连接到前端逻辑电路中的时钟输入端。逻辑电路响应于从时钟源接收时钟信号而产生修改的时钟信号，并且修改的时钟信号具有提供最小时间段的持续时间，用于前端逻辑以评估该组输入信号并产生输出信号。

2. 发明申请

US20090108874A1 Limited Switch Dynamic Logic Cell Based Register 失效
标题翻译：限制开关基于动态逻辑单元的寄存器
公开(公告)号：US20090108874A1
公开(公告)日：2009-04-30
申请号：US12172656
申请日：2008-07-14
申请人： Peter J. Klim , Jethro C. Law , Trong V. Luong , Abraham Mathews
发明人： Peter J. Klim , Jethro C. Law , Trong V. Luong , Abraham Mathews
IPC分类号： H03K19/096 , H03K19/00
CPC分类号： H03K19/0963
摘要： A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.
摘要翻译：具有有限开关动态逻辑门的电路，其具有前端逻辑电路和锁存器。前端逻辑电路的输出连接到锁存器的输入，前端逻辑电路评估施加到前端逻辑电路的一组输入信号以产生输出信号。锁存器接收并保持输出信号。电路还具有逻辑电路，其输出端连接到前端逻辑电路中的时钟输入端。逻辑电路响应于从时钟源接收时钟信号而产生修改的时钟信号，并且修改的时钟信号具有提供最小时间段的持续时间，用于前端逻辑以评估该组输入信号并产生输出信号。

3. 发明授权

US07414436B1 Limited switch dynamic logic cell based register 有权
标题翻译：有限开关动态逻辑单元的寄存器
公开(公告)号：US07414436B1
公开(公告)日：2008-08-19
申请号：US11877898
申请日：2007-10-24
申请人： Peter J. Klim , Jethro C. Law , Trong V. Luong , Abraham Mathews
发明人： Peter J. Klim , Jethro C. Law , Trong V. Luong , Abraham Mathews
IPC分类号： H03K19/00
CPC分类号： H03K19/0963
摘要： A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.
摘要翻译：具有有限开关动态逻辑门的电路，其具有前端逻辑电路和锁存器。前端逻辑电路的输出连接到锁存器的输入，前端逻辑电路评估施加到前端逻辑电路的一组输入信号以产生输出信号。锁存器接收并保持输出信号。电路还具有逻辑电路，其输出端连接到前端逻辑电路中的时钟输入端。逻辑电路响应于从时钟源接收时钟信号而产生修改的时钟信号，并且修改的时钟信号具有提供最小时间段的持续时间，用于前端逻辑以评估该组输入信号并产生输出信号。

4. 发明授权

US07587020B2 High performance, low power, dynamically latched up/down counter 失效
标题翻译：高性能，低功耗，动态锁存上/下计数器
公开(公告)号：US07587020B2
公开(公告)日：2009-09-08
申请号：US11739756
申请日：2007-04-25
申请人： Jethro C. Law , Trong V. Luong , Hung C. Ngo , Peter J. Klim
发明人： Jethro C. Law , Trong V. Luong , Hung C. Ngo , Peter J. Klim
IPC分类号： H03K25/00 , H03K23/50
CPC分类号： H03K23/40 , H03K21/026
摘要： A high performance, low power up/down counter is set forth. The counter presented is controlled by two clock pulses, an up pulse and a down pulse, and updates all bits of the counter in parallel. These bits are then latched using a scannable pulsed limited output switching dynamic logic latch. By using a limited switch dynamic logic latch, the counter is able to utilize the speed of dynamic logic without requiring the traditional dynamic logic power. The area saved and speed gained by using a dynamic latch is significant compared to a typical edge-triggered flip-flop. Additionally, by computing all the next count state bits in parallel, the counter reduces an overall count computation delay by eliminating the counter ripple.
摘要翻译：提出了一个高性能，低功耗的上/下计数器。提供的计数器由两个时钟脉冲，上升脉冲和下降脉冲控制，并并行更新计数器的所有位。然后使用可扫描的脉冲限制输出开关动态逻辑锁存器锁存这些位。通过使用有限开关动态逻辑锁存器，计数器能够利用动态逻辑的速度，而不需要传统的动态逻辑电源。与典型的边沿触发触发器相比，通过使用动态锁存器保存的区域和速度是显着的。此外，通过并行计算所有下一个计数状态位，计数器通过消除计数器纹波来减少总计数计算延迟。

5. 发明授权

US07557616B2 Limited switch dynamic logic cell based register 失效
标题翻译：有限开关动态逻辑单元的寄存器
公开(公告)号：US07557616B2
公开(公告)日：2009-07-07
申请号：US12172656
申请日：2008-07-14
申请人： Peter J. Klim , Jethro C. Law , Trong V. Luong , Abraham Matthews
发明人： Peter J. Klim , Jethro C. Law , Trong V. Luong , Abraham Matthews
IPC分类号： H03K19/00
CPC分类号： H03K19/0963
摘要： A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.
摘要翻译：具有有限开关动态逻辑门的电路，其具有前端逻辑电路和锁存器。前端逻辑电路的输出连接到锁存器的输入，前端逻辑电路评估施加到前端逻辑电路的一组输入信号以产生输出信号。锁存器接收并保持输出信号。电路还具有逻辑电路，其输出端连接到前端逻辑电路中的时钟输入端。逻辑电路响应于从时钟源接收时钟信号而产生修改的时钟信号，并且修改的时钟信号具有提供最小时间段的持续时间，用于前端逻辑以评估该组输入信号并产生输出信号。

6. 发明申请

US20080265957A1 Self-Resetting Phase Frequency Detector with Multiple Ranges of Clock Difference 审中-公开
标题翻译：具有多个时钟差范围的自复位相位检波器
公开(公告)号：US20080265957A1
公开(公告)日：2008-10-30
申请号：US11739760
申请日：2007-04-25
申请人： Trong V. Luong , Hung C. Ngo , Jethro C. Law , Peter J. Klim
发明人： Trong V. Luong , Hung C. Ngo , Jethro C. Law , Peter J. Klim
IPC分类号： H03L7/06
CPC分类号： H03L7/089
摘要： A phase detector which provides a dynamic output signal and which automatically resets if a reference clock signal and a feedback clock signal align after an output pulse is generated. With the phase detector in accordance with the present invention, when there is a difference between the positive clock edges of the reference clock signal and the feedback clock signal, the phase detector generates output pulse. The output is used to correct the feedback clock signal. In the next cycle, if the feedback signal is corrected so that both the reference clock signal and feedback clock signal are aligned, then the output signals are reset to zero. The ability to reset advantageously prevents an unexpected correction that can occur in certain phase detector designs.
摘要翻译：相位检测器，其提供动态输出信号，并且如果在产生输出脉冲之后参考时钟信号和反馈时钟信号对准，则自动复位。利用根据本发明的相位检测器，当参考时钟信号的正时钟沿与反馈时钟信号之间存在差异时，相位检测器产生输出脉冲。输出用于校正反馈时钟信号。在下一个周期中，如果反馈信号被校正，使得参考时钟信号和反馈时钟信号都对准，则输出信号被复位为零。复位的能力有利地防止了在某些相位检测器设计中可能出现的意外的校正。

7. 发明申请

US20080267341A1 High Performance, Low Power, Dynamically Latched Up/Down Counter 失效
标题翻译：高性能，低功耗，动态锁定上/下计数器
公开(公告)号：US20080267341A1
公开(公告)日：2008-10-30
申请号：US11739756
申请日：2007-04-25
申请人： Jethro C. Law , Trong V. Luong , Hung C. Ngo , Peter J. Klim
发明人： Jethro C. Law , Trong V. Luong , Hung C. Ngo , Peter J. Klim
IPC分类号： H03K25/00
CPC分类号： H03K23/40 , H03K21/026
摘要： A high performance, low power up/down counter is set forth. The counter presented is controlled by two clock pulses, an up pulse and a down pulse, and updates all bits of the counter in parallel. These bits are then latched using a scannable pulsed limited output switching dynamic logic latch. By using a limited switch dynamic logic latch, the counter is able to utilize the speed of dynamic logic without requiring the traditional dynamic logic power. The area saved and speed gained by using a dynamic latch is significant compared to a typical edge-triggered flip-flop. Additionally, by computing all the next count state bits in parallel, the counter reduces an overall count computation delay by eliminating the counter ripple.
摘要翻译：提出了一个高性能，低功耗的上/下计数器。提供的计数器由两个时钟脉冲，上升脉冲和下降脉冲控制，并并行更新计数器的所有位。然后使用可扫描的脉冲限制输出开关动态逻辑锁存器锁存这些位。通过使用有限开关动态逻辑锁存器，计数器能够利用动态逻辑的速度，而不需要传统的动态逻辑电源。与典型的边沿触发触发器相比，通过使用动态锁存器保存的区域和速度是显着的。此外，通过并行计算所有下一个计数状态位，计数器通过消除计数器纹波来减少总计数计算延迟。

8. 发明申请

US20120262197A1 TEST STRUCTURE AND METHODOLOGY FOR THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES 有权
公开(公告)号：US20120262197A1
公开(公告)日：2012-10-18
申请号：US13533191
申请日：2012-06-26
申请人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
发明人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
IPC分类号： G01R31/3187 , G01R1/067 , G01R31/00 , G01R31/02
CPC分类号： H01L22/32 , H01L21/4846 , H01L21/6835 , H01L21/76898 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/6835 , H01L2224/13005 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079
摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

9. 发明授权

US08010932B2 Structure for automated transistor tuning in an integrated circuit design 有权
标题翻译：用于集成电路设计中自动晶体管调谐的结构
公开(公告)号：US08010932B2
公开(公告)日：2011-08-30
申请号：US12130476
申请日：2008-05-30
申请人： Christopher M. Durham , Peter J. Klim , Robert N. L. Krentler
发明人： Christopher M. Durham , Peter J. Klim , Robert N. L. Krentler
IPC分类号： G06F9/455
CPC分类号： G06F17/5063
摘要： A design structure for tuning an integrated circuit design holds a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant, optimizes transistors forming a register within the integrated circuit design and thereafter optimizes transistors forming one or more clock buffers coupled to the reference clock signal.
摘要翻译：用于调谐集成电路设计的设计结构在集成电路设计中保持参考时钟信号恒定，并且当参考时钟信号保持恒定时，优化在集成电路设计中形成寄存器的晶体管，然后优化形成一个或多个时钟的晶体管耦合到参考时钟信号的缓冲器。

10. 发明申请

US20090106708A1 Structure for Reduced Area Active Above-Ground and Below-Supply Noise Suppression Circuits 失效
标题翻译：减小区域有效地面和低于电源噪声抑制电路的结构
公开(公告)号：US20090106708A1
公开(公告)日：2009-04-23
申请号：US12129532
申请日：2008-05-29
申请人： Rafik F. Dagher , Christopher M. Durham , Peter J. Klim
发明人： Rafik F. Dagher , Christopher M. Durham , Peter J. Klim
IPC分类号： G06F17/50 , H03K17/16
CPC分类号： H03K19/00361
摘要： A design structure for noise suppression. A design structure has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.
摘要翻译：噪声抑制的设计结构。设计结构具有噪声检测单元，噪声抑制单元和控制单元。噪声抑制单元具有输入和输出，其中噪声检测单元的输入连接到信号，并且如果检测到信号的变化则在输出端产生信号变化。噪声抑制单元具有输入和输出，其中噪声抑制单元的输入连接到噪声检测单元的输出，并且响应于检测到噪声检测的输出处的信号变化而产生对该信号的校正单元。控制单元具有输入和输出，其中控制单元的输入连接到信号，并且如果在信号中检测到状态改变则关闭噪声抑制单元。

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