专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08010932B2 Structure for automated transistor tuning in an integrated circuit design 有权
标题翻译：用于集成电路设计中自动晶体管调谐的结构
公开(公告)号：US08010932B2
公开(公告)日：2011-08-30
申请号：US12130476
申请日：2008-05-30
申请人： Christopher M. Durham , Peter J. Klim , Robert N. L. Krentler
发明人： Christopher M. Durham , Peter J. Klim , Robert N. L. Krentler
IPC分类号： G06F9/455
CPC分类号： G06F17/5063
摘要： A design structure for tuning an integrated circuit design holds a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant, optimizes transistors forming a register within the integrated circuit design and thereafter optimizes transistors forming one or more clock buffers coupled to the reference clock signal.
摘要翻译：用于调谐集成电路设计的设计结构在集成电路设计中保持参考时钟信号恒定，并且当参考时钟信号保持恒定时，优化在集成电路设计中形成寄存器的晶体管，然后优化形成一个或多个时钟的晶体管耦合到参考时钟信号的缓冲器。

2. 发明申请

US20080016475A1 Method, System and Program Product for Automated Transistor Tuning in an Integrated Circuit Design 审中-公开
标题翻译：集成电路设计中自动晶体管调谐的方法，系统和程序产品
公开(公告)号：US20080016475A1
公开(公告)日：2008-01-17
申请号：US11457332
申请日：2006-07-13
申请人： Christopher M. Durham , Peter J. Klim , Robert N. L. Krentler
发明人： Christopher M. Durham , Peter J. Klim , Robert N. L. Krentler
IPC分类号： G06F17/50
CPC分类号： G06F17/5063
摘要： A method of tuning an integrated circuit design includes holding a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant, optimizing transistors forming a register within the integrated circuit design and thereafter optimizing transistors forming one or more clock buffers coupled to the reference clock signal.
摘要翻译：调整集成电路设计的方法包括在集成电路设计中保持参考时钟信号恒定，并且当参考时钟信号保持不变时，优化在集成电路设计内形成寄存器的晶体管，然后优化形成一个或多个时钟的晶体管耦合到参考时钟信号的缓冲器。

3. 发明申请

US20120262197A1 TEST STRUCTURE AND METHODOLOGY FOR THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES 有权
公开(公告)号：US20120262197A1
公开(公告)日：2012-10-18
申请号：US13533191
申请日：2012-06-26
申请人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
发明人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
IPC分类号： G01R31/3187 , G01R1/067 , G01R31/00 , G01R31/02
CPC分类号： H01L22/32 , H01L21/4846 , H01L21/6835 , H01L21/76898 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/6835 , H01L2224/13005 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079
摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

4. 发明申请

US20090106708A1 Structure for Reduced Area Active Above-Ground and Below-Supply Noise Suppression Circuits 失效
标题翻译：减小区域有效地面和低于电源噪声抑制电路的结构
公开(公告)号：US20090106708A1
公开(公告)日：2009-04-23
申请号：US12129532
申请日：2008-05-29
申请人： Rafik F. Dagher , Christopher M. Durham , Peter J. Klim
发明人： Rafik F. Dagher , Christopher M. Durham , Peter J. Klim
IPC分类号： G06F17/50 , H03K17/16
CPC分类号： H03K19/00361
摘要： A design structure for noise suppression. A design structure has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.
摘要翻译：噪声抑制的设计结构。设计结构具有噪声检测单元，噪声抑制单元和控制单元。噪声抑制单元具有输入和输出，其中噪声检测单元的输入连接到信号，并且如果检测到信号的变化则在输出端产生信号变化。噪声抑制单元具有输入和输出，其中噪声抑制单元的输入连接到噪声检测单元的输出，并且响应于检测到噪声检测的输出处的信号变化而产生对该信号的校正单元。控制单元具有输入和输出，其中控制单元的输入连接到信号，并且如果在信号中检测到状态改变则关闭噪声抑制单元。

5. 发明申请

US20090102509A1 REDUCED AREA ACTIVE ABOVE-GROUND AND BELOW-SUPPLY NOISE SUPPRESSION CIRCUITS 失效
标题翻译：减少区域上下地下和低电压噪声抑制电路
公开(公告)号：US20090102509A1
公开(公告)日：2009-04-23
申请号：US11877219
申请日：2007-10-23
申请人： Rafik Dagher , Christopher M. Durham , Peter J. Klim
发明人： Rafik Dagher , Christopher M. Durham , Peter J. Klim
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00361
摘要： A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.
摘要翻译：一种用于噪声抑制的方法和装置。电路具有噪声检测单元，噪声抑制单元和控制单元。噪声抑制单元具有输入和输出，其中噪声检测单元的输入连接到信号，并且如果检测到信号的变化则在输出端产生信号变化。噪声抑制单元具有输入和输出，其中噪声抑制单元的输入连接到噪声检测单元的输出，并且响应于检测到噪声检测的输出处的信号变化而产生对该信号的校正单元。控制单元具有输入和输出，其中控制单元的输入连接到信号，并且如果在信号中检测到状态改变则关闭噪声抑制单元。

6. 发明申请

US20120264241A1 TEST STRUCTURE AND METHODOLOGY FOR THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES 审中-公开
标题翻译：三维半导体结构的测试结构和方法
公开(公告)号：US20120264241A1
公开(公告)日：2012-10-18
申请号：US13533188
申请日：2012-06-26
申请人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
发明人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
IPC分类号： H01L21/66
CPC分类号： H01L22/32 , H01L21/4846 , H01L21/6835 , H01L21/76898 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/6835 , H01L2224/13005 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079
摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.
摘要翻译：在外围测试结构衬底内形成通孔的多个外围测试结构衬底（PTSS）。周边测试结构层和至少一个功能层通过通孔形成在多个PTSS的一侧上。多个PTSS通孔中的另一侧在外围测试结构层和至少一个功能层的制造过程中暴露出来，以提供用于在整个制造顺序中测试各个层的功能性的接入点。可以在完成所有至少一个功能层的所有制造之后执行C4键合。不需要3D组装载体或C4载体衬底，因为外围测试结构衬底具有足够的机械强度以支撑外围测试结构层和至少一个功能层。

7. 发明申请

US20090114913A1 TEST STRUCTURE AND METHODOLOGY FOR THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES 有权
标题翻译：三维半导体结构的测试结构和方法
公开(公告)号：US20090114913A1
公开(公告)日：2009-05-07
申请号：US11935724
申请日：2007-11-06
申请人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
发明人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L22/32 , H01L21/4846 , H01L21/6835 , H01L21/76898 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/6835 , H01L2224/13005 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079
摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.
摘要翻译：在外围测试结构衬底内形成通孔的多个外围测试结构衬底（PTSS）。周边测试结构层和至少一个功能层通过通孔形成在多个PTSS的一侧上。多个PTSS通孔中的另一侧在外围测试结构层和至少一个功能层的制造过程中暴露出来，以提供用于在整个制造顺序中测试各个层的功能性的接入点。可以在完成所有至少一个功能层的所有制造之后执行C4键合。不需要3D组装载体或C4载体衬底，因为外围测试结构衬底具有足够的机械强度以支撑外围测试结构层和至少一个功能层。

8. 发明申请

US20090072863A1 Transmission Gate Multiplexer 失效
标题翻译：传输门复用器
公开(公告)号：US20090072863A1
公开(公告)日：2009-03-19
申请号：US12256582
申请日：2008-10-23
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
IPC分类号： H03K19/20 , G06F9/305
CPC分类号： H03K17/002
摘要： A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.
摘要翻译：用于操作多路复用器的技术包括从多个传输门组选择传输门组。从选择的传输门组中选择传输门。最后，在多路复用器的输出处提供与选择的传输门相关联的数据信号。

9. 发明申请

US20080303553A1 METHOD AND APPARATUS FOR A CONFIGURABLE LOW POWER HIGH FAN-IN MULTIPLEXER 有权
标题翻译：一种可配置低功率高风扇多路复用器的方法和装置
公开(公告)号：US20080303553A1
公开(公告)日：2008-12-11
申请号：US11759426
申请日：2007-06-07
申请人： OWEN CHIANG , Christopher M. Durham , Peter J. Klim , James D. Warnock
发明人： OWEN CHIANG , Christopher M. Durham , Peter J. Klim , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K19/0008 , H03K17/005
摘要： A configurable, low power high fan-in multiplexer (MUX) is disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.
摘要翻译：公开了一种可配置的低功率高风扇多路复用器（MUX）。 MUX电路包括多个电流控制元件，每个电流控制元件包括耦合到传输门的多个反相器。每个电流控制元件接收对应于数据信号的数据信号和选择信号。如果选择信号超过阈值（例如，逻辑“1”），则选择信号去激活上拉晶体管（例如，p型场效应晶体管），并且传输门使得相应的数据信号能够提供输入到与MUX的输出耦合的逻辑门（例如，NAND门）。如果选择信号不超过阈值，则选择信号激活上拉晶体管，并且传输门禁止相应的数据信号向逻辑门提供输入。

10. 发明申请

US20080215941A1 Double-edge triggered scannable pulsed flip-flop for high frequency and/or low power applications 审中-公开
标题翻译：用于高频和/或低功率应用的双边沿触发可扫描脉冲触发器
公开(公告)号：US20080215941A1
公开(公告)日：2008-09-04
申请号：US12123107
申请日：2008-05-19
申请人： Christopher M. Durham , Jenny Fan , Peter J. Klim , Robert N. Krentler
发明人： Christopher M. Durham , Jenny Fan , Peter J. Klim , Robert N. Krentler
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318502 , G01R31/318575 , G01R31/318591
摘要： A design structure embodied in a machine readable medium used in a design process, includes a circuit for data storage. The circuit includes a double edge clock generation circuit for generating a pulse clock signal having first and second clock pulses for each clock cycle of a system clock; a scan clock generation circuit for generating first and second scan clock signals; a scannable pulse flip-flop circuit having a data input and a data output that are connected with an internal storage node, the scannable pulse flip-flop circuit including a scan input and a scan output connected with the internal storage node, and receptive to the pulse clock signal and the scan clock signals. The scannable pulse flip-flop circuit is configured to be operable in a function mode of operation and a scan mode of operation.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括用于数据存储的电路。该电路包括一个双边沿时钟产生电路，用于产生具有用于系统时钟的每个时钟周期的第一和第二时钟脉冲的脉冲时钟信号; 扫描时钟产生电路，用于产生第一和第二扫描时钟信号; 具有与内部存储节点连接的数据输入和数据输出的可扫描脉冲触发器电路，所述可扫描脉冲触发器电路包括与内部存储节点连接的扫描输入和扫描输出，并且可接受脉冲时钟信号和扫描时钟信号。可扫描脉冲触发器电路被配置为在操作的功能模式和扫描操作模式下可操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式