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1. 发明授权

US06830382B1 Miniature form-factor connecter for fiber optic modules 有权
标题翻译：用于光纤模块的微型外形连接器
公开(公告)号：US06830382B1
公开(公告)日：2004-12-14
申请号：US10194586
申请日：2002-07-12
申请人： Peter Deane , Luu T. Nguyen , William P. Mazotti , Bruce C. Roberts , Christopher J. Smith , Janet E. Townsend , John P. Briant , Michael R. Nelson , Stephen Jacob
发明人： Peter Deane , Luu T. Nguyen , William P. Mazotti , Bruce C. Roberts , Christopher J. Smith , Janet E. Townsend , John P. Briant , Michael R. Nelson , Stephen Jacob
IPC分类号： G02B626
CPC分类号： G02B6/4292 , G02B6/3881 , G02B6/4249
摘要： An embodiment includes a connector element that comprises a connector body and a fiber optic ferrule slidably positioned inside the connector body. The ferrule holds at least one optical fiber. The connector element carries an optical sub-assembly including a photonic device and a spacer and includes a connector sleeve for receiving the connector element. The sleeve includes a ridge that operates as a first stop for the connector body and includes an alignment projection that coarsely aligns the fiber optic ferrule. The ferrule includes a pair of openings configured to receive a pair of alignment pins to provide fine alignment of optical fibers with corresponding photonic devices. The connector element is engaged with the connector sleeve to position the ferrule with respect to the optical sub-assembly such that the optical fiber is correctly positioned relative to a corresponding photonic device. Also, the invention teaches a method of using the described apparatus to position optical fibers relative to corresponding photonic devices of an optical sub-assembly.
摘要翻译：一个实施例包括连接器元件，其包括连接器主体和可滑动地定位在连接器主体内部的光纤套圈。套管保持至少一根光纤。连接器元件携带包括光子器件和间隔物的光学子组件，并且包括用于接收连接器元件的连接器套筒。套筒包括作为连接器主体的第一止动件的脊，并且包括使光纤套圈粗略对准的对准突起。套圈包括一对开口，其构造成接收一对对准销以提供光纤与对应的光子器件的精细对准。连接器元件与连接器套筒接合以相对于光学子组件定位套圈，使得光纤相对于相应的光子器件被正确定位。而且，本发明还教导了使用所描述的设备相对于光学子组件的相应光子器件定位光纤的方法。

2. 发明授权

US06802654B1 Electrical connector for opto-electronic modules 有权
标题翻译：光电模块用电接头
公开(公告)号：US06802654B1
公开(公告)日：2004-10-12
申请号：US10119619
申请日：2002-04-09
申请人： Bruce C. Roberts , Stephen A. Gee , William P. Mazotti , Luu T. Nguyen , Jia Liu , Peter Deane , Ken Pham
发明人： Bruce C. Roberts , Stephen A. Gee , William P. Mazotti , Luu T. Nguyen , Jia Liu , Peter Deane , Ken Pham
IPC分类号： G02B636
CPC分类号： H05K1/0219 , G02B6/4245 , G02B6/4261 , G02B6/4284 , H05K1/189 , H05K3/403 , H05K2201/0715 , H05K2201/09236 , H05K2201/10121
摘要： The invention comprises a connector apparatus for electrically interconnecting a chip sub-assembly to an optical sub-assembly. The apparatus includes a connector sleeve with a chip sub-assembly having at least one electrical connection arranged thereon. The connector sleeve is suitable for receiving a connector plug that includes an optical fiber optically coupled to the photonic devices of an optical sub-assembly that includes electrical connectors. The connector plug is engaged with the connector sleeve, thereby electrically interconnecting the electrical connections of the chip sub-assembly to the electrical connectors of the optical sub-assembly such that electrical signals can pass between the chip sub-assembly and a photonic device of the optical sub-assembly.
摘要翻译：本发明包括用于将芯片子组件电连接到光学子组件的连接器装置。该装置包括具有芯片子组件的连接器套筒，其具有布置在其上的至少一个电连接。连接器套筒适于接收连接器插头，该连接器插头包括光学耦合到包括电连接器的光学子组件的光子器件的光纤。连接器插头与连接器套筒接合，由此将芯片子组件的电连接电连接到光学子组件的电连接器，使得电信号可以在芯片子组件和光子装置的光子器件之间通过光学子组件。

3. 发明申请

US20090152683A1 ROUNDED DIE CONFIGURATION FOR STRESS MINIMIZATION AND ENHANCED THERMO-MECHANICAL RELIABILITY 审中-公开
标题翻译：用于应力最小化和增强的机械可靠性的圆形配置
公开(公告)号：US20090152683A1
公开(公告)日：2009-06-18
申请号：US11959422
申请日：2007-12-18
申请人： Luu T. Nguyen , Vijaylaxmi Gumaste
发明人： Luu T. Nguyen , Vijaylaxmi Gumaste
IPC分类号： H01L29/06 , H01L21/304 , H01L23/495
CPC分类号： H01L29/0657 , H01L24/32 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/73265 , H01L2224/83051 , H01L2224/83365 , H01L2224/83385 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/10155 , H01L2924/10158 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2924/3512
摘要： One aspect of the invention pertains to a semiconductor die with rounded sidewall junction edge corners. Such rounding reduces stress accumulations at those corners. In other embodiments of the invention, the sharpness of other corners and edges in the die are reduced. For example, reducing the sharpness of the bottom edge corners formed by the intersection of a sidewall and the back surface of a die can further diminish stress accumulations. One embodiment pertains to a wafer carried on a wafer support, where the wafer includes a multiplicity of such dice. Another embodiment involves a semiconductor package containing such dice. Methods of fabricating the dice are also described.
摘要翻译：本发明的一个方面涉及具有圆形侧壁连接边缘拐角的半导体管芯。这种倒圆减少了这些角落处的压力积聚。在本发明的其它实施例中，模具中其他角部和边缘的清晰度降低。例如，降低由侧壁与模具的背面相交形成的底部边角的锐度可进一步减小应力积聚。一个实施例涉及承载在晶片支撑件上的晶片，其中晶片包括多个这样的骰子。另一实施例涉及包含这种骰子的半导体封装。还描述了制造骰子的方法。

4. 发明授权

US5437095A Method of making plastic encapsulated integrated circuit package 失效
标题翻译：塑料封装集成电路封装方法
公开(公告)号：US5437095A
公开(公告)日：1995-08-01
申请号：US171713
申请日：1993-12-21
申请人： Luu T. Nguyen , Hem P. Takiar
发明人： Luu T. Nguyen , Hem P. Takiar
IPC分类号： H01L23/50 , H01L21/56 , H01L23/495 , H01R43/00
CPC分类号： H01L23/49541 , H01L21/565 , H01L24/49 , H01L2224/05554 , H01L2224/48 , H01L2224/49171 , H01L2224/49175 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01076 , H01L2924/01082 , H01L2924/14 , Y10T29/49121
摘要： A method of making an integrated circuit package is disclosed herein along with the package itself, which package is encapsulated by plastic that is caused to flow in a given direction during the package's formation. The package itself includes an IC chip having an army of chip output/input terminals, and means for supporting the chip including an array of electrically conductive leads, all of which are provided for connection with the output/input terminals of the IC chip. In addition, the overall package includes bonding wires connecting the chip output/input terminals with respective ones of the leads such that each bonding wire extends in a direction that defines an acute angle of less than 45 degrees with the given flow direction of the plastic material used to encapsulate the IC chip, support means and bonding wires. In a preferred embodiment, at least a portion and most preferably substantially all of the bonding wires are substantially parallel with the given flow direction of the plastic material.
摘要翻译：本文公开了制造集成电路封装的方法以及封装本身，该封装本身由塑料封装，在封装的形成过程中，封装件被塑料封装，使其沿给定的方向流动。封装本身包括具有芯片输出/输入端子的一部分的IC芯片，以及用于支持包括导电引线阵列的芯片的装置，所有这些芯片都设置用于与IC芯片的输出/输入端子连接。此外，整体封装包括将芯片输出/输入端子与相应的引线相连的接合线，使得每个接合线沿塑料材料的给定流动方向沿着限定小于45度的锐角的方向延伸用于封装IC芯片，支撑装置和接合线。在优选实施例中，至少一部分，最优选基本上所有的接合线基本上与塑料材料的给定流动方向平行。

5. 发明授权

US08716830B2 Thermally efficient integrated circuit package 有权
标题翻译：高效集成电路封装
公开(公告)号：US08716830B2
公开(公告)日：2014-05-06
申请号：US13304167
申请日：2011-11-23
申请人： Anindya Poddar , Luu T. Nguyen
发明人： Anindya Poddar , Luu T. Nguyen
IPC分类号： H01L21/70
CPC分类号： H01L23/3121 , H01L21/561 , H01L23/3735 , H01L23/4334 , H01L23/49575 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/81 , H01L24/83 , H01L24/84 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/291 , H01L2224/2919 , H01L2224/32227 , H01L2224/32245 , H01L2224/371 , H01L2224/4005 , H01L2224/40106 , H01L2224/40108 , H01L2224/40225 , H01L2224/40245 , H01L2224/40479 , H01L2224/48091 , H01L2224/48245 , H01L2224/48247 , H01L2224/81191 , H01L2224/81815 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2224/92225 , H01L2224/92226 , H01L2924/00014 , H01L2924/014 , H01L2924/12042 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In one aspect of the present invention, an integrated circuit package will be described. The integrated circuit package includes at least two integrated circuits that are attached with a substrate. The integrated circuits and the substrates are at least partially encapsulated in a molding material. There is a groove or air gap that extends partially through the molding material and that is arranged to form a thermal barrier between the integrated circuits.
摘要翻译：在本发明的一个方面中，将描述集成电路封装。集成电路封装包括至少两个与基板连接的集成电路。集成电路和基板至少部分地封装在模制材料中。存在部分延伸穿过模制材料并且被布置成在集成电路之间形成热障碍物的凹槽或气隙。

6. 发明授权

US07667304B2 Inkjet printed leadframes 有权
标题翻译：喷墨打印引线框
公开(公告)号：US07667304B2
公开(公告)日：2010-02-23
申请号：US12110991
申请日：2008-04-28
申请人： Randall L. Walberg , Luu T. Nguyen , Anindya Poddar
发明人： Randall L. Walberg , Luu T. Nguyen , Anindya Poddar
IPC分类号： H01L23/495 , H01L21/44
CPC分类号： H01L21/4821 , H01L21/6835 , H01L23/49579 , H01L24/97 , H01L2221/68345 , H01L2924/14 , H01L2924/00
摘要： Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate adapted for high temperature processing, and an attach pad and contact regions that are inkjet printed to the thin substrate using a metallic nanoink. The nanoink is then cured to remove liquid content. The residual metallic leadframe or electrical interconnect pattern has a substantially consistent thickness of about 10 to 50 microns or less. An associated panel assembly includes a conductive substrate panel having multiple separate device arrays comprising numerous electrical interconnect patterns each, a plurality of integrated circuit devices mounted on the conductive substrate panel, and a molded cap that encapsulates the integrated circuit devices and associated electrical interconnect patterns. The molded cap is of substantially uniform thickness over each separate device array, and extends into the space between separate device arrays.
摘要翻译：公开了用于集成电路装置的用于喷墨印刷电互连图案的引线框架的装置和方法。一种用于包装的装置包括适于高温处理的薄基板，以及使用金属纳米接头喷墨印刷到薄基板上的连接焊盘和接触区域。然后将nanoink固化以除去液体内容物。剩余的金属引线框架或电互连图案具有约10至50微米或更小的基本一致的厚度。相关联的面板组件包括导电衬底面板，该导电衬底面板具有多个单独的器件阵列，每个单独的器件阵列包括多个电互连图案，每个均包括安装在导电衬底面板上的多个集成电路器件，以及封装集成电路器件和相关联的电互连图案的模制帽。模制帽在每个分离的装置阵列上具有基本均匀的厚度，并且延伸到分离的装置阵列之间的空间中。

7. 发明申请

US20090267216A1 INKJET PRINTED LEADFRAMES 有权
公开(公告)号：US20090267216A1
公开(公告)日：2009-10-29
申请号：US12110991
申请日：2008-04-28
申请人： Randall L. Walberg , Luu T. Nguyen , Anindya Poddar
发明人： Randall L. Walberg , Luu T. Nguyen , Anindya Poddar
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/4821 , H01L21/6835 , H01L23/49579 , H01L24/97 , H01L2221/68345 , H01L2924/14 , H01L2924/00
摘要： Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate adapted for high temperature processing, and an attach pad and contact regions that are inkjet printed to the thin substrate using a metallic nanoink. The nanoink is then cured to remove liquid content. The residual metallic leadframe or electrical interconnect pattern has a substantially consistent thickness of about 10 to 50 microns or less. An associated panel assembly includes a conductive substrate panel having multiple separate device arrays comprising numerous electrical interconnect patterns each, a plurality of integrated circuit devices mounted on the conductive substrate panel, and a molded cap that encapsulates the integrated circuit devices and associated electrical interconnect patterns. The molded cap is of substantially uniform thickness over each separate device array, and extends into the space between separate device arrays.
摘要翻译：公开了用于集成电路装置的用于喷墨印刷电互连图案的引线框架的装置和方法。一种用于包装的装置包括适于高温处理的薄基板，以及使用金属纳米接头喷墨印刷到薄基板上的连接焊盘和接触区域。然后将nanoink固化以除去液体内容物。剩余的金属引线框架或电互连图案具有约10至50微米或更小的基本一致的厚度。相关联的面板组件包括导电衬底面板，该导电衬底面板具有多个单独的器件阵列，每个器件阵列包括多个电互连图案，每个电连接图案，安装在导电衬底面板上的多个集成电路器件，以及封装集成电路器件和相关电气互连图案的模制帽。模制帽在每个分离的装置阵列上具有基本均匀的厚度，并且延伸到分离的装置阵列之间的空间中。

8. 发明授权

US06822315B2 Apparatus and method for scribing semiconductor wafers using vision recognition 有权
标题翻译：使用视觉识别刻划半导体晶片的装置和方法
公开(公告)号：US06822315B2
公开(公告)日：2004-11-23
申请号：US10076818
申请日：2002-02-14
申请人： Nikhil V. Kelkar , Luu T. Nguyen
发明人： Nikhil V. Kelkar , Luu T. Nguyen
IPC分类号： H01L23544
CPC分类号： H01L21/3043 , H01L21/67092 , H01L21/681
摘要： An apparatus and method for scribing a semiconductor wafer coated with a substantially opaque material using vision recognition is disclosed. The apparatus includes a stage configured to hold a wafer, an imaging unit configured to generate an image of the wafer, and a computer configured to identify the coordinates of the scribe lines on the wafer from the image. During operation, the wafer is imaged using the imaging unit. The computer then identifies the coordinates of the scribe lines on the wafer from the image. Thereafter the coordinates are provided to a dicing machine which performs the dicing of the wafer. Accuracy is therefore improved since the dicing machine relies on the coordinates of the scribe lines as opposed to attempting to recognize the scribe lines through the opaque material. According to various embodiments of the invention, the imaging unit may use infrared, X-ray or ultrasound waves to generate the image of the wafer.
摘要翻译：公开了一种用于使用视觉识别来划刻涂有基本不透明材料的半导体晶片的装置和方法。该装置包括配置成保持晶片的台，被配置为产生晶片的图像的成像单元和被配置为从图像识别晶片上的划线的坐标的计算机。在操作期间，使用成像单元对晶片进行成像。然后，计算机从图像中识别晶片上划线的坐标。此后，将坐标提供给执行晶片切割的切割机。因此，由于切割机依赖于划痕线的坐标，而是试图通过不透明材料识别划线，因此精度得到改善。根据本发明的各种实施例，成像单元可以使用红外，X射线或超声波来产生晶片的图像。

9. 发明授权

US5130781A Dam for lead encapsulation 失效
标题翻译：大坝铅封装
公开(公告)号：US5130781A
公开(公告)日：1992-07-14
申请号：US593374
申请日：1990-10-01
申请人： Caroline A. Kovac , Peter G. Ledermann , Luu T. Nguyen
发明人： Caroline A. Kovac , Peter G. Ledermann , Luu T. Nguyen
IPC分类号： H01L21/56
CPC分类号： H01L21/56 , H01L2224/50
摘要： A method and apparatus to encapsulate a device and joints coupled to conductive leads with an encapsulating material. A fixture has a recess to hold via a vacuum the device in place. Conduits in the fixture supply air around the device to form an air dam that flows outward around the device and the leads. A nozzle supplies a metered amount of material to the surface of the device. By controlling the temperature of the fixture and/or the air forming the air dam, the flow of material can be confined to the surface of the device and the joints as it cures. The method can also provide encapsulant edge capping to reduce device stresses.
摘要翻译：一种用封装材料封装耦合到导电引线的器件和接头的方法和装置。固定装置具有通过真空将装置保持在适当位置的凹部。设备中的管道供应设备周围的空气，以形成围绕设备和引线向外流动的空气坝。喷嘴向设备的表面提供计量的材料。通过控制固定装置的温度和/或形成空气坝的空气，材料的流动可以在其固化时被限制在装置和接头的表面上。该方法还可以提供封装边缘封盖以减少器件应力。

10. 发明授权

US5049201A Method of inhibiting corrosion in an electronic package 失效
标题翻译：抑制电子封装中的腐蚀的方法
公开(公告)号：US5049201A
公开(公告)日：1991-09-17
申请号：US370355
申请日：1989-06-22
申请人： Shirley Cheng , Constance J. Araps , Allen J. Arnold , Jeffrey T. Coffin , Luu T. Nguyen
发明人： Shirley Cheng , Constance J. Araps , Allen J. Arnold , Jeffrey T. Coffin , Luu T. Nguyen
IPC分类号： C11D7/50 , C23F11/12 , C23F11/14 , C23F15/00 , H01L21/304 , H01L21/306 , H05K3/26
CPC分类号： H01L21/02052 , C23F11/12 , C23F11/14 , C23F15/00
摘要： Disclosed is a method of inhibiting corrosion on an electronic component. The method includes the steps of obtaining an electronic component and then cleaning the electronic component in a solution consisting of a complexing agent and a solvent in which the complexing agent is soluble. The complexing agent is a crown compound.

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