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1. 发明授权

US5874363A Polycide etching with HCL and chlorine 失效
标题翻译：用HCL和氯气蚀刻多晶硅
公开(公告)号：US5874363A
公开(公告)日：1999-02-23
申请号：US645458
申请日：1996-05-13
申请人： Peter D. Hoh , Tokuhisa Ohiwa , Virinder Grewal , Bruno Spuler , Waldemar Kocon , Guadalupe Wiltshire
发明人： Peter D. Hoh , Tokuhisa Ohiwa , Virinder Grewal , Bruno Spuler , Waldemar Kocon , Guadalupe Wiltshire
IPC分类号： C23F4/00 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L49/00
CPC分类号： H01L21/32137
摘要： Metal silicide is removed at a faster rate than polysilicon in dry etching of metal silicide/polysilicon composites with an etching gas made from HCl and Cl.sub.2 at a volumetric flowrate ratio of HCl:Cl.sub.2 within the range of 3:1 to 5:1.
摘要翻译：在金属硅化物/多晶硅复合材料的干法蚀刻中，用HCl和Cl 2以HCl:Cl2的体积流量比在3:1至5:1的范围内制备的蚀刻气体，以比多晶硅更快的速度去除金属硅化物。

2. 发明授权

US5846884A Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing 失效
标题翻译：在集成电路制造过程中，减少侧壁积聚的金属蚀刻方法
公开(公告)号：US5846884A
公开(公告)日：1998-12-08
申请号：US879727
申请日：1997-06-20
申请人： Munir D. Naeem , Stuart M. Burns , Nancy Greco , Steve Greco , Virinder Grewal , Ernest Levine , Masaki Narita , Bruno Spuler
发明人： Munir D. Naeem , Stuart M. Burns , Nancy Greco , Steve Greco , Virinder Grewal , Ernest Levine , Masaki Narita , Bruno Spuler
IPC分类号： C23F4/00 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L21/00
CPC分类号： H01L21/32136
摘要： A method in a plasma processing chamber for etching through a selected portion of a layer stack. The layer stack comprises a metallization layer, a first barrier layer disposed adjacent to the metallization layer, and a photoresist layer disposed above the metallization layer. The method includes etching at least partially through the first barrier layer using a high sputter component etch. The method further includes etching at least partially through the metallization layer using a low sputter component etch. The low sputter component etch has a sputter component lower than a sputter component of the high sputter component etch.
摘要翻译：一种等离子体处理室中用于蚀刻通过层堆叠的选定部分的方法。层叠包括金属化层，邻近金属化层设置的第一阻挡层和设置在金属化层上方的光致抗蚀剂层。该方法包括使用高溅射元件蚀刻至少部分地蚀刻第一阻挡层。该方法还包括使用低溅射元件蚀刻至少部分地蚀刻金属化层。低溅射元件蚀刻具有低于高溅射元件蚀刻的溅射元件的溅射元件。

3. 发明授权

US5976986A Low pressure and low power C1.sub.2 /HC1 process for sub-micron metal etching 失效
标题翻译：低压和低功率C12 / HC1工艺用于亚微米金属蚀刻
公开(公告)号：US5976986A
公开(公告)日：1999-11-02
申请号：US689174
申请日：1996-08-06
申请人： Munir D. Naeem , Stuart M. Burns , Rosemary Christie , Virinder Grewal , Walter W. Kocon , Masaki Narita , Bruno Spuler , Chi-Hua Yang
发明人： Munir D. Naeem , Stuart M. Burns , Rosemary Christie , Virinder Grewal , Walter W. Kocon , Masaki Narita , Bruno Spuler , Chi-Hua Yang
IPC分类号： C23F4/00 , H01L21/302 , H01L21/3065 , H01L21/3213
CPC分类号： H01L21/32136 , C23F4/00
摘要： RIE of metallization is achieved at low power and low pressure using Cl.sub.2 and HCl as reactant species by creating a transformer coupled plasma with power applied to electrodes positioned both above and below a substrate with metallization thereon to be etched. Three layer metallizations which include bulk aluminum or aluminum alloy sandwiched between barrier layers made from, for example, Ti/TiN, are etched in a three step process wherein relatively lower quantities of Cl.sub.2 are used in the plasma during etching of the barrier layers and relatively higher quantities of Cl.sub.2 are used during etching of the bulk aluminum or aluminum alloy layer. The ratio of etchants Cl.sub.2 and HCl and an inert gas, such as N.sub.2 are controlled in a manner such that a very thin side wall layer (10-100 .ANG.) of reaction byproducts created during RIE are deposited on the side walls of trenches formed in the metallization during etching. The side wall layer improves the isotropic nature of the etch such that submicron metallization lines with defect free side walls are formed. Hydrogen (H.sub.2) can be added to the plasma and will act to reduce corrosion.
摘要翻译：通过使用Cl2和HCl作为反应物种来实现金属化的RIE，通过产生变压器耦合的等离子体，其功率施加到位于要蚀刻的金属化的衬底上方和下方的电极上。夹在由例如Ti / TiN制成的阻挡层之间的主体铝或铝合金的三层金属化被蚀刻在三步法中，其中在蚀刻阻挡层期间在等离子体中使用相对较少量的Cl 2，并且相对在大量铝或铝合金层的蚀刻期间使用较高量的Cl 2。蚀刻剂Cl2和HCl以及惰性气体（例如N 2）的比例被控制为使得在RIE期间产生的反应副产物的非常薄的侧壁层（10-100）沉积在形成的沟槽的侧壁上蚀刻期间的金属化。侧壁层改善了蚀刻的各向同性，从而形成具有无缺陷侧壁的亚微米金属化线。可以将氢（H2）加入到等离子体中，并且起作用以减少腐蚀。

4. 发明授权

US06071820A Method for patterning integrated circuit conductors 失效
标题翻译：图案化集成电路导体的方法
公开(公告)号：US06071820A
公开(公告)日：2000-06-06
申请号：US940892
申请日：1997-09-30
申请人： Virinder Grewal , Bruno Spuler
发明人： Virinder Grewal , Bruno Spuler
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L21/00
CPC分类号： H01L21/32136
摘要： A method for forming integrated circuit conductors. The method includes the steps of placing in a reactive ion etching chamber a semiconductor body having disposed over a surface thereof: a metalization layer comprising an aluminum layer disposed between a pair of barrier metal layers; and, a photoresist layer disposed on a selected portion of a surface of an upper one of the pair of barrier layers. Radio frequency energy is inductively coupled into the chamber while silicon tetrachloride and chlorine are introduced into the chamber at rates selected to etch portions of the metalization layer exposed by the photoresist with aluminum having substantially vertical sidewalls. The silicon tetrachloride is introduced into the chamber at a rate in the range of 4 to 8 sccm. The rate of the chlorine is in the range of 50 sccm to 150 sccm. The chamber is at a pressure of about 12 milliTorr during the etching of the metalization layer. The chamber operates with an RF power of about 125 watts while the semiconductor is disposed on a platform in the chamber having an RF bias power level of about 250 watts during the etching.
摘要翻译：一种用于形成集成电路导体的方法。该方法包括以下步骤：在反应离子蚀刻室中放置半导体本体，该半导体本体具有设置在其表面上的半导体本体;金属化层，包括设置在一对势垒金属层之间的铝层; 以及设置在所述一对势垒层中的上部的表面的选定部分上的光致抗蚀剂层。射频能量感应耦合到腔室中，而四氯化硅和氯气以被选择用于蚀刻由具有基本垂直侧壁的铝的光致抗蚀剂暴露的金属化层的部分的速率引入室中。四氯化硅以4至8sccm的范围内引入室中。氯的速率在50sccm至150sccm的范围内。在蚀刻金属化层期间，室的压力约为12毫乇。该室以大约125瓦特的RF功率工作，同时在蚀刻期间半导体被布置在具有大约250瓦特的RF偏压功率水平的腔室中的平台上。

5. 发明授权

US06379869B1 Method of improving the etch resistance of chemically amplified photoresists by introducing silicon after patterning 有权
标题翻译：通过在图案化之后引入硅来提高化学放大光致抗蚀剂的耐蚀刻性的方法
公开(公告)号：US06379869B1
公开(公告)日：2002-04-30
申请号：US09282745
申请日：1999-03-31
申请人： Uwe Paul Schroeder , Gerhard Kunkel , Alois Gutmann , Bruno Spuler
发明人： Uwe Paul Schroeder , Gerhard Kunkel , Alois Gutmann , Bruno Spuler
IPC分类号： G03F700
CPC分类号： G03F7/405
摘要： A photoresist system is provided that is easily structurable and is suitable for deep ultraviolet range patterning. An increased etching resistance to oxygen-containing plasma is produced in a lithographically generated photoresist structure by treatment with an etch protectant. The etch protectant includes a silylating agent for chemical reaction with reactive groups of the photoresist. In an embodiment, the photoresist includes a base resin initially containing no aromatic groups. Silylating agents include silicon tetrachloride, silicon tetrafluoride, trichlorosilane, dimethylchlorosilane and hexamethyldisilazane.
摘要翻译：提供光致抗蚀剂系统，其易于结构化并且适用于深紫外范围图案化。通过用蚀刻保护剂处理，在光刻产生的光致抗蚀剂结构中产生对含氧等离子体的增加的耐蚀刻性。蚀刻保护剂包括用于与光致抗蚀剂的反应性基团进行化学反应的甲硅烷化剂。在一个实施方案中，光致抗蚀剂包括最初不含芳族基团的基础树脂。硅烷化剂包括四氯化硅，四氟化硅，三氯硅烷，二甲基氯硅烷和六甲基二硅氮烷。

6. 发明授权

US5935873A Deposition of carbon into nitride layer for improved selectivity of oxide to nitride etchrate for self aligned contact etching 失效
标题翻译：将碳沉积到氮化物层中，以提高氧化物对氮化物蚀刻的选择性，用于自对准接触蚀刻
公开(公告)号：US5935873A
公开(公告)日：1999-08-10
申请号：US939148
申请日：1997-09-29
申请人： Bruno Spuler , Juergen Wittmann , Martin Gutsche , Wolfgang Bergner , Matthias Ilg
发明人： Bruno Spuler , Juergen Wittmann , Martin Gutsche , Wolfgang Bergner , Matthias Ilg
IPC分类号： H01L21/28 , H01L21/265 , H01L21/302 , H01L21/318 , H01L21/3213 , H01L21/60 , C23C14/00 , C23C14/48
CPC分类号： H01L21/76897 , H01L21/3185
摘要： A method for forming a Self Aligned Contact in a semiconductor device includes incorporating carbon into a nitride layer during or following the formation of the nitride layer on a semiconductor substrate.
摘要翻译：在半导体器件中形成自对准接触的方法包括在半导体衬底上形成氮化物层期间或之后将碳结合到氮化物层中。

7. 发明授权

US06593254B2 Method for clamping a semiconductor device in a manufacturing process 有权
公开(公告)号：US06593254B2
公开(公告)日：2003-07-15
申请号：US10112271
申请日：2002-03-28
申请人： Manfred Kraxenberger , Ines Thümmel , Bruno Spuler , Thorsten Schedel , Karl Mautz
发明人： Manfred Kraxenberger , Ines Thümmel , Bruno Spuler , Thorsten Schedel , Karl Mautz
IPC分类号： H01L2144
CPC分类号： H01L21/302 , Y10S438/928
摘要： There is disclosed a method for clamping a semiconductor wafer, preferably suitable for a wafer with a diameter of 300 mm or larger. After depositing at least one encapsulating material layer over the front side and backside of the wafer, the material layer over the front side of the wafer is etched selectively to form a predetermined structure in following process steps. Wafer warpage is caused as a result of unequal wafer bowing stress of the material layer. By removing the material layer over the backside of the wafer partially or completely in accordance with the desired reduction of the bowing stress wafer warpage is reduced. In a further course of the manufacturing process, the semiconductor device is clamped electrostatically, physically or by use of vacuum.

8. 发明授权

US06177353B1 Metallization etching techniques for reducing post-etch corrosion of metal lines 有权
标题翻译：用于减少金属线蚀刻后腐蚀的金属化蚀刻技术
公开(公告)号：US06177353B1
公开(公告)日：2001-01-23
申请号：US09153390
申请日：1998-09-15
申请人： Martin Gutsche , Peter Strobl , Stephan Wege , Eike Lueken , Georg Stojakovic , Bruno Spuler
发明人： Martin Gutsche , Peter Strobl , Stephan Wege , Eike Lueken , Georg Stojakovic , Bruno Spuler
IPC分类号： H01L21027
CPC分类号： H01L21/02071 , H01L21/32136 , H01L21/32139
摘要： A method for reducing polymer deposition on vertical surfaces of metal lines etched from a metallization layer disposed above a substrate. The method includes forming a hard mask layer above the metallization layer and providing a photoresist mask above the hard mask layer. The method further includes employing the photoresist mask to form a hard mask from the hard mask layer. The hard mask has patterns therein configured to form the metal lines in a subsequent plasma-enhanced metallization etch. There is also included removing the photoresist mask. Additionally, there is included performing the plasma-enhanced metallization etch employing the hard mask and an etchant source gas that includes Cl2 and at least one passivation-forming chemical, wherein the plasma-enhanced metallization etch is performed without employing photoresist to reduce the polymer deposition during the plasma-enhanced metallization etch.
摘要翻译：一种用于减少从设置在基板上方的金属化层蚀刻的金属线的垂直表面上的聚合物沉积的方法。该方法包括在金属化层之上形成硬掩模层，并在硬掩模层之上提供光刻胶掩模。该方法还包括使用光致抗蚀剂掩模从硬掩模层形成硬掩模。硬掩模具有其中的图案，其配置成在随后的等离子体增强金属化蚀刻中形成金属线。还包括去除光刻胶掩模。另外，包括使用硬掩模和包括Cl 2和至少一种钝化形成化学品的蚀刻剂源气体进行等离子体增强的金属化蚀刻，其中在不使用光致抗蚀剂的情况下执行等离子体增强金属化蚀刻以减少聚合物沉积在等离子体增强的金属化蚀刻期间。

9. 发明授权

US06984556B2 Method of forming an isolation layer and method of manufacturing a trench capacitor 失效
标题翻译：形成隔离层的方法和制造沟槽电容器的方法
公开(公告)号：US06984556B2
公开(公告)日：2006-01-10
申请号：US10483423
申请日：2002-06-24
申请人： Christian Drabe , Jana Haensel , Anke Krasemann , Barbara Lorenz , Thomas Morgenstern , Torsten Schneider , Bruno Spuler
发明人： Christian Drabe , Jana Haensel , Anke Krasemann , Barbara Lorenz , Thomas Morgenstern , Torsten Schneider , Bruno Spuler
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861 , H01L21/31116
摘要： A two-step etch process is used to form a vertical collar oxide within the upper portion of a trench capacitor. The first step uses CF4/SiF4/O2 chemistry and ends when the bottom of the collar within the trench is opened although a thin oxide layer still remains on the surface of the PAD-nitride. The second etch step uses C4F8 chemistry to completely remove the remaining silicon oxide layer. The process provides a good uniformity in thickness of the PAD-nitride layer and sufficient collar oxide thickness in the very top section of the collar oxide. The process is applicable for manufacturing deep trench capacitors for DRAM devices.
摘要翻译：使用两步蚀刻工艺在沟槽电容器的上部形成垂直环形氧化物。第一步使用CF 4 / SiF 4 / O 2化学物质，并且当沟槽内的套环的底部打开时结束，尽管薄氧化物层仍然保留在PAD氮化物的表面上。第二蚀刻步骤使用C 4 S 8 N 8化学物质完全除去剩余的氧化硅层。该方法在环氧化物的最上部提供了PAD-氮化物层的厚度均匀性和足够的环氧化物厚度。该工艺适用于制造用于DRAM器件的深沟槽电容器。

10. 发明授权

US06521542B1 Method for forming dual damascene structure 有权
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US06521542B1
公开(公告)日：2003-02-18
申请号：US09593739
申请日：2000-06-14
申请人： Mike Armacost , Bruno Spuler , Gabriela Brase , Alois Gutmann
发明人： Mike Armacost , Bruno Spuler , Gabriela Brase , Alois Gutmann
IPC分类号： H01L21302
CPC分类号： H01L21/76808
摘要： A method is provided for forming a step in a layer of material. The method includes forming the layer over a substrate. A cavity is formed in a portion of an upper surface of the layer. The formed cavity is filled with a filler material to provide a substantially planar surface over the substrate. A photoresist layer is formed over the substantially planar surface over the substrate. An aperture is formed in the photoresist layer in registration with the formed cavity. The aperture exposes a portion of the filler material. The exposed portion of the filler material is removed along with a contiguous portion of the layer to form the step in the indentation. The cavity may be either a trench or a via. A “Trench First” approach and a “Via First” approach are described.
摘要翻译：提供了一种用于在材料层中形成台阶的方法。该方法包括在衬底上形成该层。在该层的上表面的一部分中形成空腔。形成的空腔填充有填充材料，以在基底上提供基本平坦的表面。光致抗蚀剂层形成在衬底上的基本平坦的表面上。光致抗蚀剂层中形成有与形成的空腔对准的孔。孔径暴露了填充材料的一部分。填充材料的暴露部分与层的连续部分一起被去除以形成凹陷中的台阶。空腔可以是沟槽或通孔。描述了“首先采取沟通”方式和“首选”方式。

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