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1. 发明授权

US5874363A Polycide etching with HCL and chlorine 失效
标题翻译：用HCL和氯气蚀刻多晶硅
公开(公告)号：US5874363A
公开(公告)日：1999-02-23
申请号：US645458
申请日：1996-05-13
申请人： Peter D. Hoh , Tokuhisa Ohiwa , Virinder Grewal , Bruno Spuler , Waldemar Kocon , Guadalupe Wiltshire
发明人： Peter D. Hoh , Tokuhisa Ohiwa , Virinder Grewal , Bruno Spuler , Waldemar Kocon , Guadalupe Wiltshire
IPC分类号： C23F4/00 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L49/00
CPC分类号： H01L21/32137
摘要： Metal silicide is removed at a faster rate than polysilicon in dry etching of metal silicide/polysilicon composites with an etching gas made from HCl and Cl.sub.2 at a volumetric flowrate ratio of HCl:Cl.sub.2 within the range of 3:1 to 5:1.
摘要翻译：在金属硅化物/多晶硅复合材料的干法蚀刻中，用HCl和Cl 2以HCl:Cl2的体积流量比在3:1至5:1的范围内制备的蚀刻气体，以比多晶硅更快的速度去除金属硅化物。

2. 发明授权

US5846884A Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing 失效
标题翻译：在集成电路制造过程中，减少侧壁积聚的金属蚀刻方法
公开(公告)号：US5846884A
公开(公告)日：1998-12-08
申请号：US879727
申请日：1997-06-20
申请人： Munir D. Naeem , Stuart M. Burns , Nancy Greco , Steve Greco , Virinder Grewal , Ernest Levine , Masaki Narita , Bruno Spuler
发明人： Munir D. Naeem , Stuart M. Burns , Nancy Greco , Steve Greco , Virinder Grewal , Ernest Levine , Masaki Narita , Bruno Spuler
IPC分类号： C23F4/00 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L21/00
CPC分类号： H01L21/32136
摘要： A method in a plasma processing chamber for etching through a selected portion of a layer stack. The layer stack comprises a metallization layer, a first barrier layer disposed adjacent to the metallization layer, and a photoresist layer disposed above the metallization layer. The method includes etching at least partially through the first barrier layer using a high sputter component etch. The method further includes etching at least partially through the metallization layer using a low sputter component etch. The low sputter component etch has a sputter component lower than a sputter component of the high sputter component etch.
摘要翻译：一种等离子体处理室中用于蚀刻通过层堆叠的选定部分的方法。层叠包括金属化层，邻近金属化层设置的第一阻挡层和设置在金属化层上方的光致抗蚀剂层。该方法包括使用高溅射元件蚀刻至少部分地蚀刻第一阻挡层。该方法还包括使用低溅射元件蚀刻至少部分地蚀刻金属化层。低溅射元件蚀刻具有低于高溅射元件蚀刻的溅射元件的溅射元件。

3. 发明授权

US5976986A Low pressure and low power C1.sub.2 /HC1 process for sub-micron metal etching 失效
标题翻译：低压和低功率C12 / HC1工艺用于亚微米金属蚀刻
公开(公告)号：US5976986A
公开(公告)日：1999-11-02
申请号：US689174
申请日：1996-08-06
申请人： Munir D. Naeem , Stuart M. Burns , Rosemary Christie , Virinder Grewal , Walter W. Kocon , Masaki Narita , Bruno Spuler , Chi-Hua Yang
发明人： Munir D. Naeem , Stuart M. Burns , Rosemary Christie , Virinder Grewal , Walter W. Kocon , Masaki Narita , Bruno Spuler , Chi-Hua Yang
IPC分类号： C23F4/00 , H01L21/302 , H01L21/3065 , H01L21/3213
CPC分类号： H01L21/32136 , C23F4/00
摘要： RIE of metallization is achieved at low power and low pressure using Cl.sub.2 and HCl as reactant species by creating a transformer coupled plasma with power applied to electrodes positioned both above and below a substrate with metallization thereon to be etched. Three layer metallizations which include bulk aluminum or aluminum alloy sandwiched between barrier layers made from, for example, Ti/TiN, are etched in a three step process wherein relatively lower quantities of Cl.sub.2 are used in the plasma during etching of the barrier layers and relatively higher quantities of Cl.sub.2 are used during etching of the bulk aluminum or aluminum alloy layer. The ratio of etchants Cl.sub.2 and HCl and an inert gas, such as N.sub.2 are controlled in a manner such that a very thin side wall layer (10-100 .ANG.) of reaction byproducts created during RIE are deposited on the side walls of trenches formed in the metallization during etching. The side wall layer improves the isotropic nature of the etch such that submicron metallization lines with defect free side walls are formed. Hydrogen (H.sub.2) can be added to the plasma and will act to reduce corrosion.
摘要翻译：通过使用Cl2和HCl作为反应物种来实现金属化的RIE，通过产生变压器耦合的等离子体，其功率施加到位于要蚀刻的金属化的衬底上方和下方的电极上。夹在由例如Ti / TiN制成的阻挡层之间的主体铝或铝合金的三层金属化被蚀刻在三步法中，其中在蚀刻阻挡层期间在等离子体中使用相对较少量的Cl 2，并且相对在大量铝或铝合金层的蚀刻期间使用较高量的Cl 2。蚀刻剂Cl2和HCl以及惰性气体（例如N 2）的比例被控制为使得在RIE期间产生的反应副产物的非常薄的侧壁层（10-100）沉积在形成的沟槽的侧壁上蚀刻期间的金属化。侧壁层改善了蚀刻的各向同性，从而形成具有无缺陷侧壁的亚微米金属化线。可以将氢（H2）加入到等离子体中，并且起作用以减少腐蚀。

4. 发明授权

US06071820A Method for patterning integrated circuit conductors 失效
标题翻译：图案化集成电路导体的方法
公开(公告)号：US06071820A
公开(公告)日：2000-06-06
申请号：US940892
申请日：1997-09-30
申请人： Virinder Grewal , Bruno Spuler
发明人： Virinder Grewal , Bruno Spuler
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L21/00
CPC分类号： H01L21/32136
摘要： A method for forming integrated circuit conductors. The method includes the steps of placing in a reactive ion etching chamber a semiconductor body having disposed over a surface thereof: a metalization layer comprising an aluminum layer disposed between a pair of barrier metal layers; and, a photoresist layer disposed on a selected portion of a surface of an upper one of the pair of barrier layers. Radio frequency energy is inductively coupled into the chamber while silicon tetrachloride and chlorine are introduced into the chamber at rates selected to etch portions of the metalization layer exposed by the photoresist with aluminum having substantially vertical sidewalls. The silicon tetrachloride is introduced into the chamber at a rate in the range of 4 to 8 sccm. The rate of the chlorine is in the range of 50 sccm to 150 sccm. The chamber is at a pressure of about 12 milliTorr during the etching of the metalization layer. The chamber operates with an RF power of about 125 watts while the semiconductor is disposed on a platform in the chamber having an RF bias power level of about 250 watts during the etching.
摘要翻译：一种用于形成集成电路导体的方法。该方法包括以下步骤：在反应离子蚀刻室中放置半导体本体，该半导体本体具有设置在其表面上的半导体本体;金属化层，包括设置在一对势垒金属层之间的铝层; 以及设置在所述一对势垒层中的上部的表面的选定部分上的光致抗蚀剂层。射频能量感应耦合到腔室中，而四氯化硅和氯气以被选择用于蚀刻由具有基本垂直侧壁的铝的光致抗蚀剂暴露的金属化层的部分的速率引入室中。四氯化硅以4至8sccm的范围内引入室中。氯的速率在50sccm至150sccm的范围内。在蚀刻金属化层期间，室的压力约为12毫乇。该室以大约125瓦特的RF功率工作，同时在蚀刻期间半导体被布置在具有大约250瓦特的RF偏压功率水平的腔室中的平台上。

5. 发明授权

US5723381A Formation of self-aligned overlapping bitline contacts with sacrificial polysilicon fill-in stud 失效
标题翻译：用牺牲多晶硅填充螺柱形成自对准的重叠位线接触
公开(公告)号：US5723381A
公开(公告)日：1998-03-03
申请号：US534776
申请日：1995-09-27
申请人： Virinder Grewal , Bernhard Poschenrieder
发明人： Virinder Grewal , Bernhard Poschenrieder
IPC分类号： H01L21/768 , H01L21/28 , H01L21/306 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/78 , H01L21/4763
CPC分类号： H01L21/28
摘要： A method of forming a self-aligned overlapping bitline contact, includes steps of first depositing a sacrificial polysilicon on a spacer dielectric film, and thereafter patterning the polysilicon. The polysilicon film is a sacrificial fill-in for a bitline contact stud. The method further includes depositing a middle-of-line (MOL) oxide on the polysilicon, and planarizing the MOL oxide by chemical-mechanical polishing (CMP). Thereafter, the polysilicon is etched and the spacer dielectric film is etched to form a self-aligned bitline contact.
摘要翻译：形成自对准重叠位线接触的方法包括以下步骤：首先在间隔电介质膜上沉积牺牲多晶硅，然后对多晶硅进行构图。多晶硅膜是位线接触柱的牺牲填充物。该方法还包括在多晶硅上沉积中间线（MOL），并通过化学机械抛光（CMP）平坦化MOL氧化物。此后，蚀刻多晶硅并蚀刻间隔绝缘膜以形成自对准的位线接触。

6. 发明授权

US06897155B2 Method for etching high-aspect-ratio features 失效
标题翻译：蚀刻高纵横比特征的方法
公开(公告)号：US06897155B2
公开(公告)日：2005-05-24
申请号：US10219885
申请日：2002-08-14
申请人： Ajay Kumar , Anisul H. Khan , Dragan Podlesnik , Sharma V. Pamarthy , Axel Henke , Stephan Wege , Virinder Grewal
发明人： Ajay Kumar , Anisul H. Khan , Dragan Podlesnik , Sharma V. Pamarthy , Axel Henke , Stephan Wege , Virinder Grewal
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/461
CPC分类号： H01J37/32082 , H01J2237/3347 , H01L21/3065 , H01L21/30655
摘要： A method for operating a plasma reactor to etch high-aspect-ratio features on a workpiece in a vacuum chamber. The method comprises the performance of an etch process followed by a flash process. During the etch process, a first gas is supplied into the vacuum chamber, and a plasma of the first gas is maintained for a first period of time. The plasma of the first gas comprises etchant and passivant species. During the flash process, a second gas comprising a deposit removal gas is supplied into the vacuum chamber, and a plasma of the second gas is maintained for a second period of time. The DC voltage between the workpiece and the plasma of the second gas during the second period of time is significantly less than the DC voltage between the workpiece and the plasma of the first gas during the first period of time.
摘要翻译：一种用于操作等离子体反应器以蚀刻真空室中的工件上的高纵横比特征的方法。该方法包括执行闪光处理之后的蚀刻工艺。在蚀刻工艺期间，将第一气体供应到真空室中，并且第一气体的等离子体保持第一时间段。第一气体的等离子体包括蚀刻剂和钝化物质。在闪蒸过程中，将包含沉积物去除气体的第二气体供应到真空室中，并且将第二气体的等离子体保持第二时间段。在第二时间段期间，工件与第二气体的等离子体之间的直流电压明显小于在第一时间段内第一气体的工件和等离子体之间的直流电压。

7. 发明授权

US4372809A Method for manufacturing solderable, temperable, thin film tracks which do not contain precious metal 失效
标题翻译：用于制造不含贵金属的可焊接，可回火的薄膜轨道的方法
公开(公告)号：US4372809A
公开(公告)日：1983-02-08
申请号：US346100
申请日：1982-02-05
申请人： Virinder Grewal , Werner Reindl
发明人： Virinder Grewal , Werner Reindl
IPC分类号： H05K3/34 , H01L27/01 , H05K1/16 , H05K3/06 , H05K3/24 , C23F1/02 , B05D5/12
CPC分类号： H05K3/244 , H01L27/016
摘要： A method for manufacturing solderable, temperable thin film tracks which do not contain precious metal on an electrically non-conductive substrate serving as a carrier employs the steps of applying an adhesive or resistance layer to the substrate, which serves as an intermediate layer, applying a conductive layer over the intermediate layer, and applying a protective anti-corrosion layer over the conductive layer. The protective layer may consist of aluminum or an aluminum alloy, or may be comprised of a combination of a layer of aluminum and a layer of chrome. An aluminum layer may also be applied between the intermediate layer and the conductive layer.
摘要翻译：在用作载体的不导电基材上不含有贵金属的可焊性，可回火的薄膜轨道的制造方法采用以下步骤：将粘合剂或电阻层施加到作为中间层的基底上，导电层，并在导电层上施加保护性防腐蚀层。保护层可以由铝或铝合金组成，或者可以由铝层和铬层的组合构成。也可以在中间层和导电层之间施加铝层。

8. 发明授权

US07658969B2 Chemical vapor deposition chamber with dual frequency bias and method for manufacturing a photomask using the same 失效
标题翻译：具有双频偏压的化学气相沉积室和使用其制造光掩模的方法
公开(公告)号：US07658969B2
公开(公告)日：2010-02-09
申请号：US11564354
申请日：2006-11-29
申请人： Ajay Kumar , Virinder Grewal , Wai-Fan Yau
发明人： Ajay Kumar , Virinder Grewal , Wai-Fan Yau
IPC分类号： C23C16/00
CPC分类号： C23C16/509 , C23C16/56 , H01J37/32082 , H01J37/321 , H01J37/32357 , H01J37/32706 , H01L21/67069 , H01L21/67207
摘要： A method and apparatus for process integration in manufacture of a ask are disclosed. In one embodiment, a cluster tool suitable for process integration in manufacture of a photomask including a vacuum transfer chamber having coupled thereto at least one hard mask deposition chamber and at least one plasma chamber configured for etching chromium. In another embodiment, a method for process integration in manufacture of a photomask includes depositing a hard mask on a substrate in a first processing chamber, depositing a resist layer on the substrate, patterning the resist layer, etching the hard mask through apertures formed in the patterned resist layer in a second chamber; and etching a chromium layer through apertures formed in the hard mask in a third chamber.
摘要翻译：公开了一种用于制造光掩模中的工艺集成的方法和装置。在一个实施例中，适用于制造光掩模中的工艺集成的集群工具，该光掩模包括与至少一个硬掩模沉积室耦合的真空传送室和被配置用于蚀刻铬的至少一个等离子体室。在另一个实施例中，用于制造光掩模中的工艺集成的方法包括在第一处理室中的基板上沉积硬掩模，在衬底上沉积抗蚀剂层，图案化抗蚀剂层，通过形成在图案化的抗蚀剂层在第二室中; 以及通过在第三室中形成在硬掩模中的孔蚀刻铬层。

9. 发明申请

US20070119373A1 CHEMICAL VAPOR DEPOSITION CHAMBER WITH DUAL FREQUENCY BIAS AND METHOD FOR MANUFACTURING A PHOTOMASK USING THE SAME 失效
标题翻译：具有双倍频率的化学气相沉积室和使用其制造光电子的方法
公开(公告)号：US20070119373A1
公开(公告)日：2007-05-31
申请号：US11564354
申请日：2006-11-29
申请人： Ajay Kumar , Virinder Grewal , Wai-Fan Yau
发明人： Ajay Kumar , Virinder Grewal , Wai-Fan Yau
IPC分类号： C23C16/00
CPC分类号： C23C16/509 , C23C16/56 , H01J37/32082 , H01J37/321 , H01J37/32357 , H01J37/32706 , H01L21/67069 , H01L21/67207
摘要： A method and apparatus for process integration in manufacture of a ask are disclosed. In one embodiment, a cluster tool suitable for process integration in manufacture of a photomask including a vacuum transfer chamber having coupled thereto at least one hard mask deposition chamber and at least one plasma chamber configured for etching chromium. In another embodiment, a method for process integration in manufacture of a photomask includes depositing a hard mask on a substrate in a first processing chamber, depositing a resist layer on the substrate, patterning the resist layer, etching the hard mask through apertures formed in the patterned resist layer in a second chamber; and etching a chromium layer through apertures formed in the hard mask in a third chamber.
摘要翻译：公开了一种用于制造光掩模中的工艺集成的方法和装置。在一个实施例中，适用于制造光掩模中的工艺集成的集群工具，该光掩模包括与至少一个硬掩模沉积室耦合的真空传送室和被配置用于蚀刻铬的至少一个等离子体室。在另一个实施例中，用于制造光掩模中的工艺集成的方法包括在第一处理室中的基板上沉积硬掩模，在衬底上沉积抗蚀剂层，图案化抗蚀剂层，通过形成在图案化的抗蚀剂层在第二室中; 以及通过在第三室中形成在硬掩模中的孔蚀刻铬层。

10. 发明申请

US20070031609A1 Chemical vapor deposition chamber with dual frequency bias and method for manufacturing a photomask using the same 审中-公开
标题翻译：具有双频偏压的化学气相沉积室和使用其制造光掩模的方法
公开(公告)号：US20070031609A1
公开(公告)日：2007-02-08
申请号：US11192997
申请日：2005-07-29
申请人： Ajay Kumar , Virinder Grewal , Wai-Fan Yau
发明人： Ajay Kumar , Virinder Grewal , Wai-Fan Yau
IPC分类号： C23C16/00 , C23C14/00 , B05C5/00 , B05D3/00
CPC分类号： C23C16/509 , C23C16/56 , H01J37/32082 , H01J37/321 , H01J37/32357 , H01J37/32706 , H01L21/67069 , H01L21/67207
摘要： A method and apparatus for process integration in manufacture of a photomask are disclosed. In one embodiment, a cluster tool suitable for process integration in manufacture of a photomask including a vacuum transfer chamber having coupled thereto at least one hard mask deposition chamber and at least one plasma chamber configured for etching chromium. In another embodiment, a method for process integration in manufacture of a photomask includes depositing a hard mask on a substrate in a first processing chamber, depositing a resist layer on the substrate, patterning the resist layer, etching the hard mask through apertures formed in the patterned resist layer in a second chamber; and etching a chromium layer through apertures formed in the hard mask in a third chamber.
摘要翻译：公开了一种用于制造光掩模中的工艺集成的方法和装置。在一个实施例中，适用于制造光掩模中的工艺集成的集群工具，该光掩模包括与至少一个硬掩模沉积室耦合的真空传送室和被配置用于蚀刻铬的至少一个等离子体室。在另一个实施例中，用于制造光掩模中的工艺集成的方法包括在第一处理室中的基板上沉积硬掩模，在衬底上沉积抗蚀剂层，图案化抗蚀剂层，通过形成在图案化的抗蚀剂层在第二室中; 以及通过在第三室中形成在硬掩模中的孔蚀刻铬层。

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