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1. 发明授权

US06642590B1 Metal gate with PVD amorphous silicon layer and barrier layer for CMOS devices and method of making with a replacement gate process 有权
标题翻译：具有PVD非晶硅层的金属栅极和用于CMOS器件的阻挡层以及用替代栅极工艺制造的方法
公开(公告)号：US06642590B1
公开(公告)日：2003-11-04
申请号：US09691227
申请日：2000-10-19
申请人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
发明人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
IPC分类号： H01L2976
CPC分类号： H01L29/4941 , H01L21/2807
摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. A barrier layer is deposited on the PVD amorphous silicon layer. The metal is then formed on the barrier layer. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer. The barrier layer prevents interaction between the PVD amorphous silicon layer and the metal, thereby allowing higher temperature subsequent processing while preserving the work function of the gate.
摘要翻译：半导体结构及其制造方法在硅衬底上提供金属栅极。栅极在衬底上包括高介电常数，以及在高k栅极电介质上的非晶硅的物理气相沉积（PVD）层。阻挡层沉积在PVD非晶硅层上。然后在阻挡层上形成金属。由于PVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。阻挡层防止PVD非晶硅层和金属之间的相互作用，从而允许更高温度的后续处理，同时保持栅极的功函数。

2. 发明授权

US06528362B1 Metal gate with CVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process 有权
标题翻译：具有用于CMOS器件的CVD非晶硅层的金属栅极和用替代栅极工艺制造的方法
公开(公告)号：US06528362B1
公开(公告)日：2003-03-04
申请号：US09691181
申请日：2000-10-19
申请人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
发明人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L21/28061 , H01L29/4925 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the CVD amorphous silicon layer. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer.
摘要翻译：半导体结构及其制造方法在硅衬底上提供金属栅极。该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。然后在CVD非晶硅层上形成金属。由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。

3. 发明授权

US06518154B1 Method of forming semiconductor devices with differently composed metal-based gate electrodes 有权
标题翻译：用不同组合的金属基栅极形成半导体器件的方法
公开(公告)号：US06518154B1
公开(公告)日：2003-02-11
申请号：US09813310
申请日：2001-03-21
申请人： Matthew S. Buynoski , Qi Xiang , Paul R. Besser
发明人： Matthew S. Buynoski , Qi Xiang , Paul R. Besser
IPC分类号： H01L213205
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/28097 , H01L21/823842 , H01L29/4975
摘要： MOS transistors and CMOS devices comprising a plurality of transistors including metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal on a thin gate insulator layer extending over first and second active device (e.g., a MOS transistor) precursor regions of a semiconductor substrate; selectively forming at least one masking layer segment on the first blanket layer overlying selective ones of the MOS transistor precursor regions; depositing a second blanket layer of a second metal or semi-metal, or silicon, over the thus-formed structure; effecting alloying or silicidation reaction between contacting portions of the first and second blanket layers overlying the other ones of the transistor precursor regions; exposing and selectively removing the masking layer segment; and simultaneously patterning the alloyed and unalloyed/unsilicided portions of the first blanket layer to form metal-based gate electrodes of different composition. The invention also includes MOS and CMOS devices comprising differently composed metal-based gate electrodes.
摘要翻译：包括多个晶体管的MOS晶体管和CMOS器件包括不同组成的金属基栅极，其方法包括：在第一和第二有源器件上延伸的薄栅极绝缘层上沉积第一金属的第一覆盖层（例如，，MOS晶体管）前驱体区域; 选择性地形成覆盖所述MOS晶体管前体区域中的选择性掩模层的所述第一覆盖层上的至少一个掩模层段; 在如此形成的结构上沉积第二金属或半金属或硅的第二覆盖层; 在覆盖晶体管前体区域中的另一层的第一和第二覆盖层的接触部分之间发生合金化或硅化反应; 曝光和选择性地去除掩模层段; 并且同时对第一覆盖层的合金化和非合金化/未硅化部分进行构图，以形成不同组成的金属基栅电极。本发明还包括包含不同组合的金属基栅极的MOS和CMOS器件。

4. 发明授权

US06368950B1 Silicide gate transistors 有权
标题翻译：硅化物栅极晶体管
公开(公告)号：US06368950B1
公开(公告)日：2002-04-09
申请号：US09734186
申请日：2000-12-12
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L213205
CPC分类号： H01L29/66545 , H01L21/28097
摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying metal to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The silicon is removed except for the portion of the silicon in the recess. The remaining portions of the metal are removed by manipulating the etch selectivity between the metal and the self-aligned metal silicide gate.
摘要翻译：实现自对准金属硅化物栅极的方法是通过将非晶硅限制在覆盖沟道的凹槽中并退火以使非晶硅与其上覆金属相互作用以形成自对准金属硅化物栅极来实现的。在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。除了凹部中硅的部分之外，除去硅。通过操纵金属和自对准金属硅化物栅之间的蚀刻选择性来去除金属的剩余部分。

5. 发明授权

US06342414B1 Damascene NiSi metal gate high-k transistor 有权
标题翻译：大马士革NiSi金属栅极高k晶体管
公开(公告)号：US06342414B1
公开(公告)日：2002-01-29
申请号：US09734189
申请日：2000-12-12
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L218238
CPC分类号： H01L21/28194 , H01L21/28097 , H01L21/28114 , H01L29/495 , H01L29/4975 , H01L29/51 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining a low temperature silicidation metal within a recess overlying a channel and annealing to cause the low temperature silicidation metal and its overlying silicon to interact to form the self-aligned low temperature metal silicide gate. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.
摘要翻译：实现自对准低温金属硅化物栅极的方法是通过将低温硅化金属限制在覆盖沟道的凹槽内并进行退火以使低温硅化金属及其上覆的硅相互作用以形成自对准低温度金属硅化物门。进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。

6. 发明授权

US06562718B1 Process for forming fully silicided gates 有权
标题翻译：完全硅化物门的制作工艺
公开(公告)号：US06562718B1
公开(公告)日：2003-05-13
申请号：US09729700
申请日：2000-12-06
申请人： Qi Xiang , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , George J. Kluth , Minh V. Ngo , Eric N. Paton , Christy Mei-Chu Woo
发明人： Qi Xiang , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , George J. Kluth , Minh V. Ngo , Eric N. Paton , Christy Mei-Chu Woo
IPC分类号： H01L2144
CPC分类号： H01L29/66507 , H01L21/28097
摘要： A method of forming a fully silicidized gate of a semiconductor device includes forming silicide in active regions and a portion of a gate. A shield layer is blanket deposited over the device. The top surface of the gate electrode is then exposed. A refractory metal layer is deposited and annealing is performed to cause the metal to react with the gate and fully silicidize the gate, with the shield layer protecting the active regions of the device from further silicidization to thereby prevent spiking and current leakage in the active regions.
摘要翻译：形成半导体器件的完全硅化栅极的方法包括在有源区和门的一部分中形成硅化物。屏蔽层被覆盖在该器件上。然后露出栅电极的顶表面。沉积难熔金属层并进行退火以使金属与栅极反应并使栅极完全硅化，屏蔽层保护器件的有源区不受另外的硅化，从而防止有源区中的峰值和电流泄漏。

7. 发明授权

US06475874B2 Damascene NiSi metal gate high-k transistor 有权
标题翻译：大马士革NiSi金属栅极高k晶体管
公开(公告)号：US06475874B2
公开(公告)日：2002-11-05
申请号：US09731031
申请日：2000-12-07
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L2120
CPC分类号： H01L21/28194 , H01L21/28097 , H01L29/495 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying low temperature silicidation metal to interact to form the self-aligned low temperature metal silicide gate. A precursor having a temporary gate is used to form the self-aligned low temperature silicide gate. The remaining portions of the low temperature silicidation metal is removed by manipulating the etch selectivity between the low temperature silicidation metal and the self-aligned low temperature metal silicide gate.
摘要翻译：实现自对准低温金属硅化物栅极的方法是通过将非晶硅限制在覆盖沟道的凹槽中并退火以使非晶硅与其上覆的低温硅化金属相互作用以形成自对准的低温金属来实现的硅化物门使用具有临时栅极的前体形成自对准低温硅化物栅极。通过操纵低温硅化金属和自对准的低温金属硅化物栅极之间的蚀刻选择性来除去低温硅化金属的剩余部分。

8. 发明授权

US06465334B1 Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors 有权
标题翻译：用于嵌入栅极MOS晶体管的电介质前体材料的增强的无电沉积
公开(公告)号：US06465334B1
公开(公告)日：2002-10-15
申请号：US09679369
申请日：2000-10-05
申请人： Matthew S. Buynoski , Paul R. Besser , Paul L. King , Eric N. Paton , Qi Xiang
发明人： Matthew S. Buynoski , Paul R. Besser , Paul L. King , Eric N. Paton , Qi Xiang
IPC分类号： H01L214763
CPC分类号： H01L21/28194 , H01L21/288 , H01L21/31683 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/66583
摘要： High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are fabricated by forming an ultra-thin catalytic metal layer, e.g., a monolayer thick layer of Pd or Pd, on a Si-based semiconductor substrate, electrolessly plating on the catalytic layer comprising at least one refractory or lanthanum series transition metal or metal-based dielectric precursor layer, such as of Zr and/or Hf, and then reacting the precursor layer with oxygen or with oxygen and the semiconductor substrate to form the at least one high-k metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.
摘要翻译：通过形成高质量的电介质层，例如由至少一种难熔或镧系列过渡金属氧化物或硅酸盐构成的高k电介质层，用作在叠层金属栅极MOS晶体管和CMOS器件中用作栅极绝缘体层超薄催化金属层，例如在Si基半导体衬底上的单层厚的Pd或Pd层，在包含至少一种难熔或镧系过渡金属或金属基电介质前体层的催化剂层上无电镀，例如Zr和/或Hf，然后使前体层与氧或与氧和半导体衬底反应以形成至少一种高k金属氧化物或硅酸盐。本发明的方法在至少形成栅极绝缘体层的初始阶段期间防止或至少基本上减少氧接触到衬底表面，从而最小化半导体衬底/栅极处的氧诱导表面状态的有害形成绝缘子接口。

9. 发明授权

US06458679B1 Method of making silicide stop layer in a damascene semiconductor structure 有权
标题翻译：在大马士革半导体结构中制造硅化物阻挡层的方法
公开(公告)号：US06458679B1
公开(公告)日：2002-10-01
申请号：US09780454
申请日：2001-02-12
申请人： Eric N. Paton , Paul R. Besser , Matthew S. Buynoski , Qi Xiang , Paul L. King , John Clayton Foster
发明人： Eric N. Paton , Paul R. Besser , Matthew S. Buynoski , Qi Xiang , Paul L. King , John Clayton Foster
IPC分类号： H01L213205
CPC分类号： H01L29/66583 , H01L21/28052 , H01L29/4941
摘要： A damascene gate semiconductor structure that is formed utilizing a silicide stop layer. Initially, a gate opening is provided in an insulating layer on a substrate. A first dielectric layer is deposited in the gate opening over the substrate. A silicide stop layer is then deposited in the gate opening over the first silicon layer. A second silicon layer is then deposited in the gate opening over the silicide stop layer. A metal or alloy layer is then deposited over the insulating and the second silicon layer. The damascene semiconductor structure is then temperature treated to react the metal or alloy layer with the second silicon layer to form a silicide layer. Any unreated metal or alloy is then removed from the metal or alloy layer.
摘要翻译：利用硅化物停止层形成的镶嵌栅极半导体结构。首先，在基板上的绝缘层中设置栅极开口。第一介电层沉积在衬底上的栅极开口中。然后在第一硅层上的栅极开口中沉积硅化物阻挡层。然后在硅化物停止层上的栅极开口中沉积第二硅层。然后在绝缘层和第二硅层上沉积金属或合金层。然后对镶嵌半导体结构进行温度处理以使金属或合金层与第二硅层反应形成硅化物层。然后从金属或合金层中除去任何未反应的金属或合金。

10. 发明授权

US06440867B1 Metal gate with PVD amorphous silicon and silicide for CMOS devices and method of making the same with a replacement gate process 失效
标题翻译：具有用于CMOS器件的PVD非晶硅和硅化物的金属栅极以及用替换栅极工艺制造相同的方法
公开(公告)号：US06440867B1
公开(公告)日：2002-08-27
申请号：US09691180
申请日：2000-10-19
申请人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
发明人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
IPC分类号： H01L21302
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/28097 , H01L29/517
摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the PVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer.
摘要翻译：半导体结构及其制造方法在硅衬底上提供金属栅极。栅极在衬底上包括高介电常数，以及在高k栅极电介质上的非晶硅的物理气相沉积（PVD）层。然后在PVD非晶硅层上形成金属。退火工艺在栅极中形成硅化物，其中一层硅残留未反应。由于PVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。

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