专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06627504B1 Stacked double sidewall spacer oxide over nitride 失效
标题翻译：堆叠的双侧壁间隔氧化物在氮化物上
公开(公告)号：US06627504B1
公开(公告)日：2003-09-30
申请号：US09778114
申请日：2001-02-07
申请人： Jacques J. Bertrand , George J. Kluth
发明人： Jacques J. Bertrand , George J. Kluth
IPC分类号： H01L21336
CPC分类号： H01L29/66553 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by recessing the silicon nitride spacers and forming barrier spacers on top of the silicon nitride spacers. The barrier spacers prevent silicon migration and hence the formation of bridging silicide on the silicon nitride sidewall spacers.
摘要翻译：通过在氮化硅间隔物的顶部凹入氮化硅间隔物并形成阻挡隔离物来防止在栅电极上的硅化镍层与沿着氮化硅侧壁间隔物的源极/漏极区之间的桥接。阻挡间隔物防止硅迁移，从而在氮化硅侧壁间隔物上形成桥接硅化物。

2. 发明授权

US07998832B2 Semiconductor device with isolation trench liner, and related fabrication methods 有权
标题翻译：具有隔离沟槽衬垫的半导体器件及相关制造方法
公开(公告)号：US07998832B2
公开(公告)日：2011-08-16
申请号：US12199616
申请日：2008-08-27
申请人： Richard J. Carter , George J. Kluth , Michael J. Hargrove
发明人： Richard J. Carter , George J. Kluth , Michael J. Hargrove
IPC分类号： H01L29/00
CPC分类号： H01L21/76232
摘要： A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.
摘要翻译：这里提供一种制造半导体器件的方法，其中所得半导体器件中的宽度效应降低。该方法包括提供具有半导体材料的衬底，在半导体材料中形成隔离沟槽，并用衬垫材料衬里隔离沟槽，衬垫材料基本上抑制其上形成高k材料。然后用绝缘材料填充衬里的沟槽。此后，在绝缘材料的至少一部分上以及半导体材料的至少一部分上形成一层高k栅极材料。衬垫材料分隔高k栅极材料层，其阻止氧在半导体材料的有源区上迁移。

3. 发明授权

US06841449B1 Two-step process for nickel deposition 失效
标题翻译：镍沉积两步法
公开(公告)号：US06841449B1
公开(公告)日：2005-01-11
申请号：US10061345
申请日：2002-02-04
申请人： Jacques J. Bertrand , George J. Kluth
发明人： Jacques J. Bertrand , George J. Kluth
IPC分类号： H01L21/285 , H01L21/336 , H01L21/44
CPC分类号： H01L29/665 , H01L21/28518
摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices are formed by a salicide process wherein a blanket nickel layer is formed in contact with the exposed portions of the substrate surface adjacent the sidewall spacers, the top surface of the gate electrode, and the sidewall spacers. Embodiments include forming the blanket layer of nickel is formed by the sequential steps of: (i) forming a layer of nickel by sputtering with oxygen gas; and, (ii) forming a layer of nickel by sputtering with argon gas. The two step process for forming the blanket layer of nickel advantageously prevents the formation of nickel silicide on the outer surfaces of the insulative sidewall spacers.
摘要翻译：亚微米尺寸的超浅结MOS和/或CMOS晶体管器件通过自对准硅化物工艺形成，其中覆盖镍层形成为与邻近侧壁间隔物的衬底表面的暴露部分接触，栅极的顶表面电极和侧壁间隔物。实施例包括通过以下顺序的步骤形成镍覆盖层：（i）通过用氧气溅射形成镍层; 和（ii）用氩气溅射形成镍层。用于形成镍覆盖层的两步工艺有利于防止在绝缘侧壁间隔物的外表面上形成硅化镍。

4. 发明授权

US06562718B1 Process for forming fully silicided gates 有权
标题翻译：完全硅化物门的制作工艺
公开(公告)号：US06562718B1
公开(公告)日：2003-05-13
申请号：US09729700
申请日：2000-12-06
申请人： Qi Xiang , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , George J. Kluth , Minh V. Ngo , Eric N. Paton , Christy Mei-Chu Woo
发明人： Qi Xiang , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , George J. Kluth , Minh V. Ngo , Eric N. Paton , Christy Mei-Chu Woo
IPC分类号： H01L2144
CPC分类号： H01L29/66507 , H01L21/28097
摘要： A method of forming a fully silicidized gate of a semiconductor device includes forming silicide in active regions and a portion of a gate. A shield layer is blanket deposited over the device. The top surface of the gate electrode is then exposed. A refractory metal layer is deposited and annealing is performed to cause the metal to react with the gate and fully silicidize the gate, with the shield layer protecting the active regions of the device from further silicidization to thereby prevent spiking and current leakage in the active regions.
摘要翻译：形成半导体器件的完全硅化栅极的方法包括在有源区和门的一部分中形成硅化物。屏蔽层被覆盖在该器件上。然后露出栅电极的顶表面。沉积难熔金属层并进行退火以使金属与栅极反应并使栅极完全硅化，屏蔽层保护器件的有源区不受另外的硅化，从而防止有源区中的峰值和电流泄漏。

5. 发明授权

US06391730B1 Process for fabricating shallow pocket regions in a non-volatile semiconductor device 有权
标题翻译：在非易失性半导体器件中制造浅口袋区域的方法
公开(公告)号：US06391730B1
公开(公告)日：2002-05-21
申请号：US09670229
申请日：2000-09-25
申请人： George J. Kluth , Arvind Halliyal
发明人： George J. Kluth , Arvind Halliyal
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/26586 , H01L21/76213 , H01L27/115 , H01L29/66492 , H01L29/66833
摘要： A process for fabricating shallow pocket regions in a non-volatile semiconductor device includes providing a semiconductor substrate having a principal surface. A masking pattern is formed to overlie the principal surface that includes an opening therein. An angled, molecular ion implantation process is carried out to form first and second shallow pocket regions in the semiconductor substrate. The first and second pocket regions at least partially underlie the first and second sidewalls, respectively, of the opening in the patterned layer. Further processing steps are then carried out to form a bit-line region in a non-volatile semiconductor device.
摘要翻译：在非易失性半导体器件中制造浅口袋区域的方法包括提供具有主表面的半导体衬底。形成掩模图案以覆盖其中包括开口的主表面。进行成角度的分子离子注入工艺以在半导体衬底中形成第一和第二浅槽区域。第一和第二袋区域分别至少部分地位于图案化层中的开口的第一和第二侧壁的下面。然后执行进一步的处理步骤以在非易失性半导体器件中形成位线区域。

6. 发明授权

US06376341B1 Optimization of thermal cycle for the formation of pocket implants 有权
标题翻译：优化热循环形成口袋种植体
公开(公告)号：US06376341B1
公开(公告)日：2002-04-23
申请号：US09627584
申请日：2000-07-28
申请人： George J. Kluth , Arvind Halliyal
发明人： George J. Kluth , Arvind Halliyal
IPC分类号： H01L2104
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/112
摘要： A process for fabricating a memory cell, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a masking layer overlying the ONO layer, patterning the masking layer into a resist mask, implanting the semiconductor substrate with a p-type dopant to create a p-type region, and laterally diffusing the p-type region. In one preferred embodiment, the lateral diffusing of the p-type region includes exposing the semiconductor substrate to a thermal cycle. Preferably, the thermal cycle is a rapid thermal anneal or a furnace anneal.
摘要翻译：一种制造存储单元的方法，该方法包括形成覆盖在半导体衬底上的ONO层，沉积覆盖ONO层的掩模层，将掩模层图案化成抗蚀剂掩模，用p型掺杂剂注入半导体衬底以产生 p型区域，并且横向扩散p型区域。在一个优选实施例中，p型区域的横向扩散包括将半导体衬底暴露于热循环。优选地，热循环是快速热退火或炉退火。

7. 发明申请

US20110260263A1 SEMICONDUCTOR DEVICE WITH ISOLATION TRENCH LINER 有权
标题翻译：具有隔离斜面衬里的半导体器件
公开(公告)号：US20110260263A1
公开(公告)日：2011-10-27
申请号：US13178362
申请日：2011-07-07
申请人： Richard J. CARTER , George J. KLUTH , Michael J. HARGROVE
发明人： Richard J. CARTER , George J. KLUTH , Michael J. HARGROVE
IPC分类号： H01L29/772
CPC分类号： H01L21/76232
摘要： A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.
摘要翻译：这里提供一种制造半导体器件的方法，其中所得半导体器件中的宽度效应降低。该方法包括提供具有半导体材料的衬底，在半导体材料中形成隔离沟槽，并用衬垫材料衬里隔离沟槽，衬垫材料基本上抑制其上形成高k材料。然后用绝缘材料填充衬里的沟槽。此后，在绝缘材料的至少一部分上以及半导体材料的至少一部分上形成一层高k栅极材料。衬垫材料分隔高k栅极材料层，其阻止氧在半导体材料的有源区上迁移。

8. 发明授权

US07723192B2 Integrated circuit long and short channel metal gate devices and method of manufacture 有权
标题翻译：集成电路长短通道金属栅极器件及其制造方法
公开(公告)号：US07723192B2
公开(公告)日：2010-05-25
申请号：US12048414
申请日：2008-03-14
申请人： Richard J. Carter , Michael J. Hargrove , George J. Kluth , John G. Pellerin
发明人： Richard J. Carter , Michael J. Hargrove , George J. Kluth , John G. Pellerin
IPC分类号： H01L21/8234
CPC分类号： H01L21/823456 , H01L21/28114 , H01L21/823468 , H01L29/4933 , H01L29/66545
摘要： A method is provided for manufacturing an integrated circuit including a short channel (SC) device and a long channel (LC) device each overlaid by an interlayer dielectric. The SC device has an SC gate stack and the LC device initially has a dummy gate. In one embodiment, the method includes the steps of removing the dummy gate to form an LC device trench, and depositing metal gate material over the SC device and the LC device. The metal gate material contacts the SC gate stack and substantially fills the LC device trench.
摘要翻译：提供了一种用于制造集成电路的方法，该集成电路包括短沟道（SC）器件和每个由层间电介质覆盖的长沟道（LC）器件。 SC器件具有SC栅极堆叠，LC器件最初具有虚拟栅极。在一个实施例中，该方法包括以下步骤：去除伪栅极以形成LC器件沟槽，以及在SC器件和LC器件上沉积金属栅极材料。金属栅极材料接触SC栅极堆叠并且基本上填充LC器件沟槽。

9. 发明授权

US06992370B1 Memory cell structure having nitride layer with reduced charge loss and method for fabricating same 有权
标题翻译：具有具有降低的电荷损失的氮化物层的存储单元结构及其制造方法
公开(公告)号：US06992370B1
公开(公告)日：2006-01-31
申请号：US10655179
申请日：2003-09-04
申请人： George J. Kluth , Robert B. Clark-Phelps , Joong S. Jeon , Huicai Zhong , Arvind Halliyal , Mark T. Ramsbey , Robert B. Ogle, Jr. , Kuo T. Chang , Wenmei Li
发明人： George J. Kluth , Robert B. Clark-Phelps , Joong S. Jeon , Huicai Zhong , Arvind Halliyal , Mark T. Ramsbey , Robert B. Ogle, Jr. , Kuo T. Chang , Wenmei Li
IPC分类号： H01L23/58 , H01L21/302
CPC分类号： H01L21/28282 , H01L21/28176 , H01L21/28202 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： According to one embodiment, a memory cell structure comprises a semiconductor substrate, a first silicon oxide layer situated over the semiconductor substrate, a charge storing layer situated over the first silicon oxide layer, a second silicon oxide layer situated over the charge storing layer, and a gate layer situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer comprises silicon nitride having reduced hydrogen content, e.g., in the range of about 0 to 0.5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer. The reduced charge loss in the charge storing layer has the benefit of reducing threshold voltage shifts, programming data loss, and programming capability loss in the memory device, thereby improving memory device performance.
摘要翻译：根据一个实施例，存储单元结构包括半导体衬底，位于半导体衬底上的第一氧化硅层，位于第一氧化硅层之上的电荷存储层，位于电荷存储层上方的第二氧化硅层，以及位于所述第二氧化硅层上方的栅极层。在示例性实施例中，电荷存储层包括具有降低的氢含量的氮化硅，例如在约0至0.5原子百分比的范围内。结果，降低的氢含量降低了电荷存储层中的电荷损失。电荷存储层中的减少的电荷损失有利于减少存储器件中的阈值电压偏移，编程数据丢失和编程能力损失，从而提高存储器件性能。

10. 发明授权

US06902977B1 Method for forming polysilicon gate on high-k dielectric and related structure 失效
标题翻译：在高k电介质和相关结构上形成多晶硅栅极的方法
公开(公告)号：US06902977B1
公开(公告)日：2005-06-07
申请号：US10678445
申请日：2003-10-03
申请人： George J. Kluth , Joong S. Jeon , Qi Xiang , Huicai Zhong
发明人： George J. Kluth , Joong S. Jeon , Qi Xiang , Huicai Zhong
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78
CPC分类号： H01L29/78 , H01L21/28035 , H01L21/28194 , H01L29/4925 , H01L29/517
摘要： According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate comprises a step of forming a high-k dielectric layer over the substrate. The high-k dielectric layer may be, for example, hafnium oxide or zirconium oxide. The method further comprises forming a first polysilicon layer over the high-k dielectric layer, where the first polysilicon layer is formed by utilizing a precursor does not comprise hydrogen. The first polysilicon layer can have a thickness of between approximately 50.0 Angstroms and approximately 200.0 Angstroms, for example. According to this exemplary embodiment, the method can further comprise forming a second polysilicon layer over the first polysilicon layer. The second polysilicon layer may be formed, for example, by utilizing a precursor that comprises hydrogen, where the first polysilicon layer prevents the hydrogen from interacting with the high-k dielectric layer.
摘要翻译：根据一个示例性实施例，在衬底上形成场效应晶体管的方法包括在衬底上形成高k电介质层的步骤。高k电介质层可以是例如氧化铪或氧化锆。该方法还包括在高k电介质层上形成第一多晶硅层，其中通过利用前体形成第一多晶硅层不包含氢。例如，第一多晶硅层可以具有在约50.0埃和约200.0埃之间的厚度。根据该示例性实施例，该方法还可以包括在第一多晶硅层上形成第二多晶硅层。第二多晶硅层可以例如通过利用包含氢的前体形成，其中第一多晶硅层防止氢与高k电介质层相互作用。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式