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1. 发明授权

US4500951A Plant control system 失效
标题翻译：工厂控制系统
公开(公告)号：US4500951A
公开(公告)日：1985-02-19
申请号：US335689
申请日：1981-12-30
申请人： Norihiko Sugimoto , Nobuhiro Hamada , Ikuro Masuda , Jinichi Sakurai
发明人： Norihiko Sugimoto , Nobuhiro Hamada , Ikuro Masuda , Jinichi Sakurai
IPC分类号： G05B9/03 , G05B23/02 , G06F11/00 , G06F11/22 , G06F15/46
CPC分类号： G06F11/22 , G05B9/03 , G06F11/2033
摘要： In a plant control system, a transmission channel includes loop transmission lines arranged in duplex. Equivalently connected to this transmission channel are a plurality of one-loop controller stations, a backup station backing up a disabled one of the plural controller stations and a display station for displaying the status of the controller stations and the backup station. Each of the controller stations, backup station and display station includes a built-in microcomputer. Each of these stations includes also a transmission interface circuit and a self-diagnostic circuit. The transmission interface circuit in each station selects one of the transmission lines for data transmission between its own station and the others. The self-diagnostic circuit in each station detects the presence of failure of normal operation of its own station and disconnects the disabled station from the transmission line, so that the other stations may not be adversely affected by the disabled station.
摘要翻译：在工厂控制系统中，传输信道包括双工布置的环路传输线路。等效连接到该传输信道的是多个单环控制站，备份站备份多个控制站中的一个禁用站，以及显示站，用于显示控制站和备站的状态。控制台，备站和显示台均包括内置的微型计算机。这些站中的每一个还包括传输接口电路和自诊断电路。每个站中的传输接口电路选择传输线之一用于在其本站和其他站之间进行数据传输。各站自诊断电路检测本台站正常运行故障的存在，并将禁用站与传输线断开连接，使其他站不受残障站的不利影响。

2. 发明授权

US4366478A Signal transmitting and receiving apparatus 失效
标题翻译：信号发射和接收装置
公开(公告)号：US4366478A
公开(公告)日：1982-12-28
申请号：US222708
申请日：1981-01-05
申请人： Ikuro Masuda , Hisayoshi Shiraishi , Seiichiro Ogawa , Shigeo Shiono , Jinichi Sakurai , Takeo Yuminaka
发明人： Ikuro Masuda , Hisayoshi Shiraishi , Seiichiro Ogawa , Shigeo Shiono , Jinichi Sakurai , Takeo Yuminaka
IPC分类号： H04L1/08 , G06F13/42 , G06F17/40 , H04L1/00 , H04L13/08 , H04L25/45 , H04L29/00 , G08C25/00 , H04L7/00
CPC分类号： H04L25/45 , G06F13/4226
摘要： Disclosed is a signal transmitting and receiving apparatus for transmitting and receiving parallel-by-word data signals, converting the parallel-by-word data signal to serial-by-word data signal, and transmitting the serial-by-word data signal to control units connected in a multi-drop connection configuration or receiving the signals transmitted from the control units.An external control mode and an internal control mode in receiving the parallel-by-word data signal, a simulation mode, and the prevention of competing status between a write timing of the parallel-by-word data to a buffer memory and a read timing of the data for converting it to serial-by-word data are described.
摘要翻译：公开了一种用于发送和接收逐字数据信号的信号发送和接收装置，将逐字数据信号转换为逐字数据信号，并将逐字数据信号发送到控制以多点连接配置连接的单元或接收从控制单元发送的信号。外部控制模式和内部控制模式，用于接收逐字数据信号，模拟模式以及防止逐字数据到缓冲存储器的写定时与读时序之间的竞争状态描述用于将其转换为逐个字数据的数据。

3. 发明授权

US5117382A Semiconductor integrated circuit for performing an arithmetic operation including bipolar and MOS transistors 失效
标题翻译：用于执行包括双极和MOS晶体管在内的算术运算的半导体集成电路
公开(公告)号：US5117382A
公开(公告)日：1992-05-26
申请号：US618114
申请日：1990-11-26
申请人： Hideo Maejima , Takashi Hotta , Ikuro Masuda , Masahiro Iwamura , Kouzaburou Kurita , Masahiro Ueno
发明人： Hideo Maejima , Takashi Hotta , Ikuro Masuda , Masahiro Iwamura , Kouzaburou Kurita , Masahiro Ueno
IPC分类号： G06F5/01 , G06F7/50 , G06F7/508 , G06F13/40 , G06F15/78
CPC分类号： G06F7/508 , G06F13/4077 , G06F15/7832 , G06F5/015 , G06F2207/3872 , Y02B60/1207 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A semiconductor integrated circuit is provided for performing an arithmetic operation using an arithmetic operation circuit. The integrated circuit includes a read bus for connecting the arithmetic operation circuit with a plurality of registers which store input data and/or output data of said arithmetic operation circuit. A precharge and sense circuit connects said arithmetic operation circuit to said read bus. The precharge and sense circuit includes a precharge circuit to precharge the read bus to a first level before the read operation, and a sense circuit to detect that the level of the read bus has discharged to a second, lower level after the read operation begins. In this way, the integrated circuit can detect very slight potential variations on said read bus.

4. 发明授权

US4983862A Semiconductor integrated circuit with a bi-MOS input circuit for providing input signals to an internal logic block 失效
标题翻译：具有用于向内部逻辑块提供输入信号的双MOS输入电路的半导体集成电路
公开(公告)号：US4983862A
公开(公告)日：1991-01-08
申请号：US429489
申请日：1989-10-31
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177
CPC分类号： H03K19/09448 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09429 , H01L2924/0002
摘要： In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

5. 发明授权

US4879480A Bicmos gate array 失效
标题翻译：二门门阵列
公开(公告)号：US4879480A
公开(公告)日：1989-11-07
申请号：US240450
申请日：1988-09-02
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akiro Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akiro Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177
CPC分类号： H03K19/09448 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09429 , H01L2924/0002
摘要： In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
摘要翻译：在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由双极晶体管。因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

6. 发明授权

US4769561A Bipolar transistor-field effect transistor composite circuit 失效
标题翻译：双极晶体管场效应晶体管复合电路
公开(公告)号：US4769561A
公开(公告)日：1988-09-06
申请号：US680495
申请日：1984-12-11
申请人： Masahiro Iwamura , Ikuro Masuda
发明人： Masahiro Iwamura , Ikuro Masuda
IPC分类号： H03K19/01 , H03K17/567 , H03K17/687 , H03K19/08 , H03K19/0944
CPC分类号： H03K19/09448
摘要： A bipolar transistor-complementary field effect transistor composite circuit is provided which includes a pair of first and second bipolar transistors each having a collector of a first conductivity type, a base of a second conductivity type and an emitter of a first conductivity type. Collector-emitter current paths of the bipolar transistors are connected in series to each other between first and second potentials, with a connection node providing an output of the composite circuit. Field effect transistors are respectively coupled between the bases and collectors of the bipolar transistors for controlling the on-off states of the bipolar transistors in opposite relationship to one another in response to an input signal provided to the composite circuit. Also, discharge arrangements are provided for the bases of the first and second bipolar transistors to discharge parasitic capacitance in the bases of the first and second bipolar transistors when they are turned off.
摘要翻译：提供了双极晶体管 - 互补场效应晶体管复合电路，其包括一对第一和第二双极晶体管，每个具有第一导电类型的集电极，第二导电类型的基极和第一导电类型的发射极。双极晶体管的集电极 - 发射极电流路径在第一和第二电位之间彼此串联连接，连接节点提供复合电路的输出。场效应晶体管分别耦合在双极晶体管的基极和集电极之间，用于响应于提供给复合电路的输入信号而彼此相反地控制双极晶体管的导通截止状态。此外，为第一和第二双极晶体管的基极提供放电布置，以在第一和第二双极晶体管的基极中的寄生电容被截止时放电。

7. 发明授权

US4727517A Semiconductor memory with column line voltage sitting circuit 失效
标题翻译：半导体存储器与列线电压坐立电路
公开(公告)号：US4727517A
公开(公告)日：1988-02-23
申请号：US785654
申请日：1985-10-09
申请人： Masahiro Ueno , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Ikuro Masuda , Tetsuo Nakano
发明人： Masahiro Ueno , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Ikuro Masuda , Tetsuo Nakano
IPC分类号： G11C5/14 , G11C7/12 , G11C7/00
CPC分类号： G11C5/147 , G11C7/12
摘要： A semiconductor memory is provided including a plurality of row lines, memory cells driven by selecting a row line, sense amplifiers connected to the memory cells via column lines, and a column line voltage setting circuit for setting a predetermined voltage on the column lines. The predetermined voltage is defined by a voltage necessary to activate semiconductor switch elements constituting the column line voltage setting circuit, and is made nearly equal to the threshold voltage of the sense amplifiers. Thus, a high-speed, low power consumption semiconductor memory can be realized.
摘要翻译：提供一种半导体存储器，其包括多条行线，通过选择行线驱动的存储单元，经由列线连接到存储单元的读出放大器，以及用于在列线上设置预定电压的列线电压设置电路。预定电压由激活构成列线电压设定电路的半导体开关元件所需的电压限定，并且使其几乎等于读出放大器的阈值电压。因此，可以实现高速，低功耗的半导体存储器。

8. 发明授权

US4678943A Inverting logic buffer BICMOS switching circuit using an enabling switch for three-state operation with reduced dissipation 失效
标题翻译：反相逻辑缓冲器BICMOS开关电路使用启用开关进行三态操作，减少耗散
公开(公告)号：US4678943A
公开(公告)日：1987-07-07
申请号：US704209
申请日：1985-02-22
申请人： Akira Uragami , Yukio Suzuki , Shinji Kadono , Masahiro Iwamura , Ikuro Masuda , Tatsumi Yamauchi
发明人： Akira Uragami , Yukio Suzuki , Shinji Kadono , Masahiro Iwamura , Ikuro Masuda , Tatsumi Yamauchi
IPC分类号： H03K19/0175 , H03K17/04 , H03K17/60 , H03K19/0944
CPC分类号： H03K19/09448
摘要： A switching circuit comprises a pre-stage circuit coupled to receive an input signal and an output stage, wherein an output signal having a phase opposite to that of a signal of an input terminal IN can be obtained from an output terminal OUT of the output stage. The pre-stage circuit includes a p-channel MOSFET M1 and an n-channel MOSFET M2 that receive input signals at their gates. The output stage includes two NPN transistors Q1 and Q2 that are connected in series. The drain output of the p-channel MOSFET M1 is applied to the base of one of the transistors of the output stage, and the source output of the n-channel MOSFET M2 is applied to the base of the other of the transistors of the output stage. A third MOSFET M3 is coupled between a power supply and the p-channel MOSFET M1 and the n-channel MOSFET M2. When the MOSFET M3 is rendered non-conductive by a control signal EN, both MOSFETs M1 and M2 and both NPN transistors Q1 and Q2 become non-conductive irrespective of the signal of the input terminal IN. Under this condition, the output terminal OUT is in a floating state. Thus, the switching circuit is a tri-state circuit.
摘要翻译：开关电路包括耦合以接收输入信号的预级电路和输出级，其中可以从输出级的输出端OUT获得具有与输入端IN的信号相反的相位的输出信号。该前级电路包括在其栅极接收输入信号的p沟道MOSFET M1和n沟道MOSFET M2。输出级包括串联连接的两个NPN晶体管Q1和Q2。 p沟道MOSFET M1的漏极输出被施加到输出级的一个晶体管的基极，并且n沟道MOSFET M2的源极输出被施加到输出的晶体管的另一个的基极阶段。第三个MOSFET M3耦合在电源和p沟道MOSFET M1和n沟道MOSFET M2之间。当通过控制信号EN使MOSFET M3不导通时，无论输入端子IN的信号如何，MOSFET M1和M2以及两个NPN晶体管Q1和Q2都不导通。在这种情况下，输出端子OUT处于浮置状态。因此，开关电路是三态电路。

9. 发明授权

US4523276A Input/output control device with memory device for storing variable-length data and method of controlling thereof 失效
标题翻译：具有用于存储可变长度数据的存储装置的输入/输出控制装置及其控制方法
公开(公告)号：US4523276A
公开(公告)日：1985-06-11
申请号：US533803
申请日：1983-09-19
申请人： Hideo Maejima , Ikuro Masuda , Hidekazu Matsumoto , Shyoichi Miyazawa
发明人： Hideo Maejima , Ikuro Masuda , Hidekazu Matsumoto , Shyoichi Miyazawa
IPC分类号： G06F13/36 , G06F12/04 , G06F12/06 , G06F15/16 , G06F15/177 , G06F5/00 , G06F13/00
CPC分类号： G06F12/04
摘要： An input/output control device stores variable-length data in a memory device at a high storage efficiency and without reducing the speed of data processing. The data stored in a memory are read out in the form of data of a fixed word length and then processed, the data having been processed are stored in another memory in the form of data of the fixed word length. The data stored in another memory are subjected to data organization to be outputted in the form of data of a given word length. Each of the memories is divided into a plurality of regions, and each region stores therein data of the same word length, respectively.
摘要翻译：输入/输出控制装置以高存储效率将可变长度数据存储在存储装置中，而不降低数据处理的速度。存储在存储器中的数据以固定字长的数据的形式读出，然后被处理，已经处理的数据以固定字长的数据的形式存储在另一个存储器中。存储在另一存储器中的数据经受数据组织以以给定字长的数据的形式输出。每个存储器被分成多个区域，并且每个区域分别存储相同字长的数据。

10. 发明授权

US5378941A Bipolar transistor MOS transistor hybrid semiconductor integrated circuit device 失效
标题翻译：双极晶体管MOS晶体管混合半导体集成电路器件
公开(公告)号：US5378941A
公开(公告)日：1995-01-03
申请号：US983467
申请日：1992-11-30
申请人： Yoji Nishio , Ikuro Masuda , Kazuo Kato , Shigeo Kuboki , Masahiro Iwamura
发明人： Yoji Nishio , Ikuro Masuda , Kazuo Kato , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L21/331 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L27/118 , H01L29/73 , H03K19/173 , H03K19/02 , H03K19/084
CPC分类号： H01L27/11896
摘要： A high speed and low power consumption semiconductor integrated circuit device has a plurality of internal circuits each including circuit elements for performing a desired circuit operation, a plurality of input circuits for receiving external input signals and supplying the signals to the internal circuits and a plurality of output circuits for receiving the output signals from the internal circuits and supplying signals to an external circuit. Each of the internal circuits is primarily constructed by bipolar transistors and MOS transistors, and at least one of each of the input circuits and each of the output circuits is primarily constructed by bipolar transistors.
摘要翻译：高速低功耗半导体集成电路器件具有多个内部电路，每个内部电路包括用于执行期望的电路操作的电路元件，用于接收外部输入信号并将信号提供给内部电路的多个输入电路和多个输出电路，用于接收来自内部电路的输出信号并向外部电路提供信号。每个内部电路主要由双极晶体管和MOS晶体管构成，并且每个输入电路和每个输出电路中的至少一个主要由双极晶体管构成。

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