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1. 发明授权

US5566344A In-system programming architecture for a multiple chip processor 失效
标题翻译：用于多芯片处理器的系统内编程架构
公开(公告)号：US5566344A
公开(公告)日：1996-10-15
申请号：US445006
申请日：1995-05-19
申请人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Richard E. Crippen , Robert M. Salter, III
发明人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Richard E. Crippen , Robert M. Salter, III
IPC分类号： G06F15/78 , G11C16/10 , G06F15/76
CPC分类号： G11C16/102 , G06F15/7814 , Y02B60/1207 , Y02B60/1225
摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.The processor can be programmed internally or externally. In the in-system programming mode, the processor program counter is used to fetch running instructions out of an on-board ROM instruction memory on the processor die. The processor core outputs an address into which data is to be programmed on its output data bus. The processor core then receives from an external device the data which is to be programmed into the selected address and outputs it serially onto the data bus and therefrom to the memory die. The address and program data are then parallel output from separate registers on the memory die along with a program pulse to program the memory core.
摘要翻译：一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能的操作和其他控制信号。处理器可以在内部或外部进行编程。在系统内编程模式下，处理器程序计数器用于从处理器管芯上的板载ROM指令存储器中获取运行指令。处理器内核在其输出数据总线上输出要编程数据的地址。然后，处理器核心从外部设备接收要被编程到所选择的地址中的数据，并将其串行地输出到数据总线上并从其输出到存储器管芯。然后，地址和程序数据与存储器管芯上的单独寄存器一起并行输出，并且与编程脉冲一起编程存储器内核。

2. 发明授权

US4789958A Carry-look-ahead adder including bipolar and MOS transistors 失效
标题翻译：携带前视加法器包括双极和MOS晶体管
公开(公告)号：US4789958A
公开(公告)日：1988-12-06
申请号：US703171
申请日：1985-02-19
申请人： Hideo Maejima , Takashi Hotta , Ikuro Masuda , Masahiro Iwamura , Kouzaburou Kurita , Masahiro Ueno
发明人： Hideo Maejima , Takashi Hotta , Ikuro Masuda , Masahiro Iwamura , Kouzaburou Kurita , Masahiro Ueno
IPC分类号： G06F5/01 , G06F7/50 , G06F7/508 , G06F13/40 , G06F15/78
CPC分类号： G06F7/508 , G06F13/4077 , G06F15/7832 , G06F5/015 , G06F2207/3872 , Y02B60/1207 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A carry-look-ahead adder is provided which is implemented as a semiconductor integrated circuit. The integrated circuit includes a bipolar transistor coupled to the output terminal for providing an output indicative of the arithmetic operation. Impedance elements are coupled to the bipolar transistor and at least one FET is provided to control the on/off state of the bipolar transistor.
摘要翻译：提供了作为半导体集成电路实现的进位前视加法器。集成电路包括耦合到输出端的双极晶体管，用于提供表示算术运算的输出。阻抗元件耦合到双极晶体管，并且提供至少一个FET以控制双极晶体管的导通/截止状态。

3. 发明授权

US4418397A Address decode system 失效
标题翻译：地址解码系统
公开(公告)号：US4418397A
公开(公告)日：1983-11-29
申请号：US154339
申请日：1980-05-29
申请人： George L. Brantingham , Warren S. Graber
发明人： George L. Brantingham , Warren S. Graber
IPC分类号： G06F12/06 , G06F15/78 , G06F3/00 , H03K13/00
CPC分类号： G06F12/063 , G06F15/7867 , Y02B60/1207 , Y02B60/1225
摘要： An address decode scheme decodes address lines using a minimum number of electrical conductors and minimum area on the chip. Instead of decoding the true and the complementary signals of each address input using a PLA or static gate, the present decode scheme uses two sets of programmable transistors for respectively detecting zeros and ones on the address lines and for generating selected high and low decode signals in conjunction with precharge, discharge, and control transistors. This invention is equally effective in CMOS, NMOS, or PMOS technologies.
摘要翻译：地址解码方案使用最小数量的电导体和芯片上的最小面积解码地址线。本解码方案不是使用PLA或静态门对每个地址输入的真实和互补信号进行解码，而是使用两组可编程晶体管来分别检测地址线上的零和一个，并用于产生选择的高和低解码信号与预充电，放电和控制晶体管连接。本发明在CMOS，NMOS或PMOS技术中同样有效。

4. 发明授权

US6023742A Reconfigurable computing architecture for providing pipelined data paths 失效
标题翻译：可配置的计算架构，用于提供流水线数据路径
公开(公告)号：US6023742A
公开(公告)日：2000-02-08
申请号：US897094
申请日：1997-07-18
申请人： William Henry Carl Ebeling , Darren Charles Cronquist , Paul David Franklin
发明人： William Henry Carl Ebeling , Darren Charles Cronquist , Paul David Franklin
IPC分类号： G06F15/78 , G06F13/14
CPC分类号： G06F9/30036 , G06F15/7867 , Y02B60/1207 , Y02B60/1225
摘要： A configurable computing architecture (10) has its functionality controlled by a combination of static and dynamic control, wherein the configuration is referred to as static control and instructions are referred to as dynamic control. A reconfigurable data path (12) has a plurality of elements including functional units (32, 36), registers (30), and memories (34) whose interconnection and functionality is determined by a combination of static and dynamic control. These elements are connected together, using the static configuration, into a pipelined data path that performs a computation of interest. The dynamic control signals (21) are suitably used to change the operation of a functional unit and the routing of signals between functional units. The static control signals (23) are provided each by a static memory cell (62) that is written by a host (13). The controller (14) generates control instructions (16) that are interpreted by a control path (18) that computes the dynamic control signals. The control path is configured statically for a given application to perform the appropriate interpretation of the instructions generated by the controller. By using a combination of static and dynamic control information, the amount of dynamic control used to achieve flexible operation is significantly reduced.
摘要翻译：可配置的计算架构（10）具有由静态和动态控制的组合控制其功能，其中该配置被称为静态控制，并且指令被称为动态控制。可重构数据路径（12）具有包括功能单元（32,36），寄存器（30）和存储器（34）的多个元件，其互连和功能由静态和动态控制的组合确定。这些元素使用静态配置连接在一起，进入一个执行感兴趣的计算的流水线数据路径。动态控制信号（21）适于用于改变功能单元的操作和功能单元之间的信号路由。静态控制信号（23）由主机（13）写入的静态存储单元（62）提供。控制器（14）产生由计算动态控制信号的控制路径（18）解释的控制指令（16）。为给定的应用程序静态配置控制路径，以对控制器生成的指令执行适当的解释。通过使用静态和动态控制信息的组合，用于实现灵活操作的动态控制量显着降低。

5. 发明授权

US5784636A Reconfigurable computer architecture for use in signal processing applications 失效
标题翻译：用于信号处理应用的可重构计算机体系结构
公开(公告)号：US5784636A
公开(公告)日：1998-07-21
申请号：US654395
申请日：1996-05-28
申请人： Charle R. Rupp
发明人： Charle R. Rupp
IPC分类号： G06F15/78 , G06F15/80 , G06F15/00
CPC分类号： G06F15/8015 , G06F15/7867 , Y02B60/1207 , Y02B60/1225
摘要： An architecture for information processing devices which allows the construction of low cost, high performance systems for specialized computing applications involving sensor data processing. The reconfigurable processor architecture of the invention uses a programmable logic structure called an Adaptive Logic Processor (ALP). This structure is similar to an extendible field programmable gate array (FPGA) and is optimized for the implementation of program specific pipeline functions, where the function may be changed any number of times during the progress of a computation. A Reconfigurable Pipeline Instruction Control (RPIC) unit is used for loading the pipeline functions into the ALP during the configuration process and coordinating the operations of the ALP with other information processing structures, such as memory, I/O devices, and arithmetic processing units. Multiple components having the reconfigurable architecture of the present invention may be combined to produce high performance parallel processing systems based on the Single Instruction Multiple Data (SIMD) architecture concept.
摘要翻译：用于信息处理设备的架构，其允许构建用于涉及传感器数据处理的专用计算应用的低成本，高性能系统。本发明的可重构处理器架构使用称为自适应逻辑处理器（ALP）的可编程逻辑结构。该结构类似于可扩展现场可编程门阵列（FPGA），并且针对程序特定的流水线功能的实现进行了优化，其中在计算过程中可以改变任何次数的功能。可配置管道指令控制（RPIC）单元用于在配置过程中将流水线功能加载到ALP中，并将ALP与其他信息处理结构（如存储器，I / O设备和算术处理单元）的操作协调。可以组合具有本发明的可重构架构的多个组件，以便基于单指令多数据（SIMD）架构概念来产生高性能并行处理系统。

6. 发明授权

US5606710A Multiple chip package processor having feed through paths on one die 失效
标题翻译：多芯片封装处理器具有一个管芯上的馈通通路
公开(公告)号：US5606710A
公开(公告)日：1997-02-25
申请号：US359417
申请日：1994-12-20
申请人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Robert M. Salter, III , Richard E. Crippen
发明人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Robert M. Salter, III , Richard E. Crippen
IPC分类号： G06F15/78 , G11C16/10 , G06F13/00
CPC分类号： G11C16/102 , G06F15/7814 , Y02B60/1207 , Y02B60/1225
摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. A plurality of feed-throughs are provided on the non-volatile memory die to provide communication paths from the processor die to package pads which are in the shadow of the non-volatile memory die relative to the processor die and thus prevent direct connection from the processor die to the package pad. In normal run mode, these pads are exclusively used as feed-through, providing a direct connection between a specific pad on the processor die and a specific pad on the package. In other modes of operation, however, the signals input from (or output to) the feed-through package pads are re-routed by transfer gates to the non-volatile memory die.
摘要翻译：一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能的操作和其他控制信号。在非易失性存储器管芯上提供多个馈通以提供从处理器管芯到非易失性存储器管芯相对于处理器管芯的阴影中的封装焊盘的通信路径，从而防止从处理器裸片到封装垫。在正常运行模式下，这些焊盘专门用作馈通，提供处理器管芯上的特定焊盘与封装上的特定焊盘之间的直接连接。然而，在其他操作模式中，从（或输出到）馈通封装焊盘输入的信号通过传输门被重新路由到非易失性存储器管芯。

7. 发明授权

US5742844A IBM PC compatible multi-chip module 失效
标题翻译： IBM PC兼容多芯片模块
公开(公告)号：US5742844A
公开(公告)日：1998-04-21
申请号：US564688
申请日：1995-11-29
申请人： David L. Feldman
发明人： David L. Feldman
IPC分类号： G06F15/02 , G06F13/36 , G06F15/78 , G06F15/16 , H01L23/48 , H01L23/50
CPC分类号： H01L23/50 , G06F15/7814 , H01L2924/0002 , Y02B60/1207 , Y02B60/1225
摘要： A multi-chip module and a chip set that comprises a plurality of the multi-chip modules. The multi-chip module includes a plurality of functional circuits provided on a substrate, the circuits defining a plurality of signal inputs and outputs. A plurality of pins are secured in a single row along the periphery of the substrate and are connected to the inputs and outputs. The pins include a set of 91 signal pins, two ground pins, and a power pin, the signal pins having a configuration complying in number and signal type with the IEEE-Prequirements to define an ISA bus. The multi-chip module includes a rectangular housing wherein the pins, in the form of gull wing pins, extend laterally from a peripherally extending wall. The ISA bus pins extend along one side and partially along adjacent sides of the rectangular module. The functional circuits of one embodiment of the module include a CPU, serial interfaces, a parallel interface, a hard drive interface, a floppy disk interface, a keyboard interface, and flash memory. Other multi-chip modules can include a PCMCIA interface, an Ethernet interface, or a display controller.
摘要翻译：一种多芯片模块和包括多个所述多芯片模块的芯片组。多芯片模块包括设置在基板上的多个功能电路，电路限定多个信号输入和输出。多个引脚沿着基板的周边固定在单行中，并连接到输入和输出。引脚包括一组91个信号引脚，两个接地引脚和电源引脚，信号引脚具有符合IEEE-P要求的数量和信号类型的配置，用于定义ISA总线。多芯片模块包括矩形壳体，其中以鸥翼销形式的销从周向延伸的壁横向延伸。 ISA总线引脚沿着矩形模块的一侧和部分沿相邻侧面延伸。模块的一个实施例的功能电路包括CPU，串行接口，并行接口，硬盘驱动器接口，软盘接口，键盘接口和闪存。其他多芯片模块可以包括PCMCIA接口，以太网接口或显示控制器。

8. 发明授权

US5123107A Topography of CMOS microcomputer integrated circuit chip including core processor and memory, priority, and I/O interface circuitry coupled thereto 失效
标题翻译：包括核心处理器和存储器，优先级以及与其耦合的I / O接口电路的CMOS微计算机集成电路芯片的地形
公开(公告)号：US5123107A
公开(公告)日：1992-06-16
申请号：US368826
申请日：1989-06-20
申请人： William D. Mensch, Jr.
发明人： William D. Mensch, Jr.
IPC分类号： G06F15/78
CPC分类号： G06F15/7814 , Y02B60/1207 , Y02B60/1225
摘要： The topography of a CMOS microcomputer chip includes first, second, third, and fourth consecutive edges, with chip control logic being located along the upper left edge. Five peripheral I/O port buffer circuits are located around the edge of the periphery of the chip, except for an eight bit peripheral output port located along the lower right edge and multiplexed with chip select outputs. The microcomputer includes an eight bit W65CO2S CMOS microprocessor, 192 bytes of SRAM, 4096 bytes of SROM, 22 edge interrupt inputs, 3 level-sensitive interrupt inputs, a UART, serial interface buffer for effectuating correction to a local area token passing network, four timers, and priority interrupt control circuitry. The topography is arranged to provide convenient connection of terminals of the microcomputer when it is used as a "core" of a larger computer system chip including an external memory system, a serial communication system, and an interrupt and I/O system. Static bus holding devices are connected to the memories on which I/O terminals are connected, and allow the microprocessor to interpret trinary logic states presented to the I/O port leads by external devices.
摘要翻译： CMOS微计算机芯片的形状包括第一，第二，第三和第四连续边缘，其中芯片控制逻辑沿着左上边缘定位。五个外围I / O端口缓冲电路位于芯片外围的边缘周围，除了位于右下边缘的8位外设输出端口，并与芯片选择输出进行复用。微型计算机包括一个8位W65CO2S CMOS微处理器，192字节的SRAM，4096字节的SROM，22个边缘中断输入，3个电平敏感中断输入，一个UART，串行接口缓冲器，用于对局域令牌通过网络进行校正，四个定时器和优先级中断控制电路。该形状被设置为当用作包括外部存储器系统，串行通信系统以及中断和I / O系统的较大计算机系统芯片的“核心”时，提供微型计算机的终端的便利连接。静态总线保持装置连接到连接有I / O端子的存储器，并允许微处理器解释由外部设备呈现给I / O端口引线的三态逻辑状态。

9. 发明授权

US5117382A Semiconductor integrated circuit for performing an arithmetic operation including bipolar and MOS transistors 失效
标题翻译：用于执行包括双极和MOS晶体管在内的算术运算的半导体集成电路
公开(公告)号：US5117382A
公开(公告)日：1992-05-26
申请号：US618114
申请日：1990-11-26
申请人： Hideo Maejima , Takashi Hotta , Ikuro Masuda , Masahiro Iwamura , Kouzaburou Kurita , Masahiro Ueno
发明人： Hideo Maejima , Takashi Hotta , Ikuro Masuda , Masahiro Iwamura , Kouzaburou Kurita , Masahiro Ueno
IPC分类号： G06F5/01 , G06F7/50 , G06F7/508 , G06F13/40 , G06F15/78
CPC分类号： G06F7/508 , G06F13/4077 , G06F15/7832 , G06F5/015 , G06F2207/3872 , Y02B60/1207 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A semiconductor integrated circuit is provided for performing an arithmetic operation using an arithmetic operation circuit. The integrated circuit includes a read bus for connecting the arithmetic operation circuit with a plurality of registers which store input data and/or output data of said arithmetic operation circuit. A precharge and sense circuit connects said arithmetic operation circuit to said read bus. The precharge and sense circuit includes a precharge circuit to precharge the read bus to a first level before the read operation, and a sense circuit to detect that the level of the read bus has discharged to a second, lower level after the read operation begins. In this way, the integrated circuit can detect very slight potential variations on said read bus.

10. 发明授权

US4800487A Topography of integrated circuit including a microprocessor 失效
标题翻译：集成电路的地形包括一个微处理器
公开(公告)号：US4800487A
公开(公告)日：1989-01-24
申请号：US29272
申请日：1987-03-23
申请人： William D. Mensch, Jr.
发明人： William D. Mensch, Jr.
IPC分类号： G06F9/318 , G06F15/78
CPC分类号： G06F9/3017 , G06F15/7832 , Y02B60/1207 , Y02B60/1225
摘要： The topography of a CMOS microprocessor chip includes address buffer circuitry along the bottom and lower left hand edges of the chip, data bus buffers disposed along the lower right hand edge of the chip, address register circuitry and an arithmetic logic unit contained in a register section adjacent to both the address buffer circuitry and data bus buffer circuitry, register transfer circuitry adjacent to and above the register section, P channel circuitry disposed directly above the register transfer circuitry for producing sum-of-minterm signals applied to the register transfer circuitry in response to the minterm signals produced by N channel circuitry disposed adjacent to and immediately above the P channel circuitry. Status register circuitry responsive to status register control logic disposed along the top edge of the chip is positioned in the register section for direct, low capacitance connection to the internal data bus. N and P MOSFETs in the N and P channel circuitry, respectively, are aligned so that polycrystaline silicon conductors of the minterm signals terminate on the gate electrodes of P channel MOSFETs above points at which sum-of-minterm signals are coupled to the register transfer circuitry.
摘要翻译： CMOS微处理器芯片的形状包括沿着芯片的底部和左下边缘的地址缓冲器电路，沿着芯片的右下边缘设置的数据总线缓冲器，地址寄存器电路和包含在寄存器部分中的算术逻辑单元与地址缓冲器电路和数据总线缓冲器电路相邻，与寄存器部分相邻并且在寄存器部分上方的寄存器传送电路，P沟道电路直接设置在寄存器传输电路上方，用于响应于施加到寄存器传送电路的最小信号涉及由邻近于P信道电路并且紧邻P信道电路设置的N信道电路产生的最小信号。响应于沿着芯片的顶部边缘设置的状态寄存器控制逻辑的状态寄存器电路位于寄存器部分中，用于与内部数据总线的直接，低电容连接。 N和P沟道电路中的N和P MOSFET分别对准，使得minterm信号的多晶硅导体终止在P沟道MOSFET的栅电极上方，在最小值信号与寄存器传输耦合电路。

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