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1. 发明授权

US4689503A Level conversion circuitry for a semiconductor integrated circuit utilizing bis CMOS circuit elements 失效
标题翻译：利用双CMOS电路元件的半导体集成电路的电平转换电路
公开(公告)号：US4689503A
公开(公告)日：1987-08-25
申请号：US575567
申请日：1984-01-31
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177 , H03K19/01 , H03K19/013 , H03K19/017
CPC分类号： H03K19/09448 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09429 , H01L2924/0002
摘要： In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
摘要翻译：在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由双极晶体管。因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

2. 发明授权

US5245224A Level conversion circuitry for a semiconductor integrated circuit 失效
标题翻译：半导体集成电路的电平转换电路
公开(公告)号：US5245224A
公开(公告)日：1993-09-14
申请号：US845136
申请日：1992-03-03
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177
CPC分类号： H03K19/09448 , H03K19/017518 , H03K19/01806 , H03K19/09429
摘要： In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
摘要翻译：在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由双极晶体管。因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

3. 发明授权

US5103120A Level conversion circuitry for a semiconductor integrated circuit 失效
标题翻译：半导体集成电路的电平转换电路
公开(公告)号：US5103120A
公开(公告)日：1992-04-07
申请号：US636892
申请日：1991-01-02
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177
CPC分类号： H03K19/09448 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09429 , H01L2924/0002
摘要： In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
摘要翻译：在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。类似地，在用于CMOS电平操作的内部逻辑块的CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由双极晶体管。因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

4. 发明授权

US4983862A Semiconductor integrated circuit with a bi-MOS input circuit for providing input signals to an internal logic block 失效
标题翻译：具有用于向内部逻辑块提供输入信号的双MOS输入电路的半导体集成电路
公开(公告)号：US4983862A
公开(公告)日：1991-01-08
申请号：US429489
申请日：1989-10-31
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177
CPC分类号： H03K19/09448 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09429 , H01L2924/0002
摘要： In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

5. 发明授权

US5512847A BiCMOS tri-state output driver 失效
标题翻译： BiCMOS三态输出驱动器
公开(公告)号：US5512847A
公开(公告)日：1996-04-30
申请号：US321012
申请日：1994-10-06
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177 , H03K19/01
CPC分类号： H03K19/09448 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09429 , H01L2924/0002
摘要： In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
摘要翻译：在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由双极晶体管。因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

6. 发明授权

US4879480A Bicmos gate array 失效
标题翻译：二门门阵列
公开(公告)号：US4879480A
公开(公告)日：1989-11-07
申请号：US240450
申请日：1988-09-02
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akiro Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akiro Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177
CPC分类号： H03K19/09448 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09429 , H01L2924/0002
摘要： In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
摘要翻译：在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由双极晶体管。因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

7. 发明授权

US5495183A Level conversion circuitry for a semiconductor integrated circuit 失效
标题翻译：半导体集成电路的电平转换电路
公开(公告)号：US5495183A
公开(公告)日：1996-02-27
申请号：US440335
申请日：1995-05-12
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Urragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Urragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177
CPC分类号： H03K19/1778 , H03K19/017518 , H03K19/01806 , H03K19/09429 , H03K19/09448 , H03K19/17784 , H03K19/17792
摘要： In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
摘要翻译：在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由双极晶体管。因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

8. 发明授权

US4678943A Inverting logic buffer BICMOS switching circuit using an enabling switch for three-state operation with reduced dissipation 失效
标题翻译：反相逻辑缓冲器BICMOS开关电路使用启用开关进行三态操作，减少耗散
公开(公告)号：US4678943A
公开(公告)日：1987-07-07
申请号：US704209
申请日：1985-02-22
申请人： Akira Uragami , Yukio Suzuki , Shinji Kadono , Masahiro Iwamura , Ikuro Masuda , Tatsumi Yamauchi
发明人： Akira Uragami , Yukio Suzuki , Shinji Kadono , Masahiro Iwamura , Ikuro Masuda , Tatsumi Yamauchi
IPC分类号： H03K19/0175 , H03K17/04 , H03K17/60 , H03K19/0944
CPC分类号： H03K19/09448
摘要： A switching circuit comprises a pre-stage circuit coupled to receive an input signal and an output stage, wherein an output signal having a phase opposite to that of a signal of an input terminal IN can be obtained from an output terminal OUT of the output stage. The pre-stage circuit includes a p-channel MOSFET M1 and an n-channel MOSFET M2 that receive input signals at their gates. The output stage includes two NPN transistors Q1 and Q2 that are connected in series. The drain output of the p-channel MOSFET M1 is applied to the base of one of the transistors of the output stage, and the source output of the n-channel MOSFET M2 is applied to the base of the other of the transistors of the output stage. A third MOSFET M3 is coupled between a power supply and the p-channel MOSFET M1 and the n-channel MOSFET M2. When the MOSFET M3 is rendered non-conductive by a control signal EN, both MOSFETs M1 and M2 and both NPN transistors Q1 and Q2 become non-conductive irrespective of the signal of the input terminal IN. Under this condition, the output terminal OUT is in a floating state. Thus, the switching circuit is a tri-state circuit.
摘要翻译：开关电路包括耦合以接收输入信号的预级电路和输出级，其中可以从输出级的输出端OUT获得具有与输入端IN的信号相反的相位的输出信号。该前级电路包括在其栅极接收输入信号的p沟道MOSFET M1和n沟道MOSFET M2。输出级包括串联连接的两个NPN晶体管Q1和Q2。 p沟道MOSFET M1的漏极输出被施加到输出级的一个晶体管的基极，并且n沟道MOSFET M2的源极输出被施加到输出的晶体管的另一个的基极阶段。第三个MOSFET M3耦合在电源和p沟道MOSFET M1和n沟道MOSFET M2之间。当通过控制信号EN使MOSFET M3不导通时，无论输入端子IN的信号如何，MOSFET M1和M2以及两个NPN晶体管Q1和Q2都不导通。在这种情况下，输出端子OUT处于浮置状态。因此，开关电路是三态电路。

9. 发明授权

US4694203A High speed bi-comos switching circuit 失效
标题翻译：高速双电源开关电路
公开(公告)号：US4694203A
公开(公告)日：1987-09-15
申请号：US716151
申请日：1985-03-26
申请人： Akira Uragami , Yukio Suzuki , Masahiro Iwamura , Ikuro Masuda
发明人： Akira Uragami , Yukio Suzuki , Masahiro Iwamura , Ikuro Masuda
IPC分类号： H03K19/08 , H03K17/04 , H03K17/0412 , H03K17/567 , H03K17/60 , H03K17/687 , H03K19/017 , H03K19/0944 , H03K19/013
CPC分类号： H03K17/04126 , H03K17/567 , H03K19/09448
摘要： A bipolar/CMOS mixed type switching circuit comprising two npn-type bipolar transistors Q.sub.1, Q.sub.2 that are connected in the form of a totem pole in the output stage, a CMOS inverter and an NMOSFET M.sub.3 for driving these transistors in a complementary manner, and resistance means R for discharging the electric charge stored in the base of the transistor Q.sub.2. The threshold voltage of an NMOSFET M.sub.2 constituting the CMOS inverter in the absence of substrate effect is set to be substantially equal to the threshold voltage of the NMOSFET M.sub.3 in the absence of the substrate effect, and the channel conductance W.sub.N /L.sub.N of the NMOSFET M.sub.3 is so set that the threshold voltage V.sub.LT1 of the CMOS inverter and the practical threshold voltage V.sub.LT2 of the NMOSFET M.sub.3 will be nearly the same. Owing to the above structure, there is obtained a switching circuit which permits little through current to flow and which operates at high speeds.
摘要翻译：一种双极/ CMOS混合型开关电路，包括在输出级以图腾柱形式连接的两个npn型双极晶体管Q1，Q2，CMOS反相器和用于以互补方式驱动这些晶体管的NMOSFET M3;以及用于对存储在晶体管Q2的基极中的电荷进行放电的电阻装置R. 在不存在衬底效应的情况下，构成CMOS反相器的NMOSFET M2的阈值电压被设置为在没有衬底效应的情况下基本上等于NMOSFET M3的阈值电压，并且NMOSFET M3的沟道电导WN / LN 被设置为使得CMOS反相器的阈值电压VLT1和NMOSFET M3的实际阈值电压VLT2将几乎相同。由于上述结构，所以获得了允许很少的直流电流并且高速运行的开关电路。

10. 发明授权

US5378941A Bipolar transistor MOS transistor hybrid semiconductor integrated circuit device 失效
标题翻译：双极晶体管MOS晶体管混合半导体集成电路器件
公开(公告)号：US5378941A
公开(公告)日：1995-01-03
申请号：US983467
申请日：1992-11-30
申请人： Yoji Nishio , Ikuro Masuda , Kazuo Kato , Shigeo Kuboki , Masahiro Iwamura
发明人： Yoji Nishio , Ikuro Masuda , Kazuo Kato , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L21/331 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L27/118 , H01L29/73 , H03K19/173 , H03K19/02 , H03K19/084
CPC分类号： H01L27/11896
摘要： A high speed and low power consumption semiconductor integrated circuit device has a plurality of internal circuits each including circuit elements for performing a desired circuit operation, a plurality of input circuits for receiving external input signals and supplying the signals to the internal circuits and a plurality of output circuits for receiving the output signals from the internal circuits and supplying signals to an external circuit. Each of the internal circuits is primarily constructed by bipolar transistors and MOS transistors, and at least one of each of the input circuits and each of the output circuits is primarily constructed by bipolar transistors.
摘要翻译：高速低功耗半导体集成电路器件具有多个内部电路，每个内部电路包括用于执行期望的电路操作的电路元件，用于接收外部输入信号并将信号提供给内部电路的多个输入电路和多个输出电路，用于接收来自内部电路的输出信号并向外部电路提供信号。每个内部电路主要由双极晶体管和MOS晶体管构成，并且每个输入电路和每个输出电路中的至少一个主要由双极晶体管构成。

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