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1. 发明申请

US20110090657A1 PRINTED WIRING BOARD WITH BUILT-IN SEMICONDUCTOR ELEMENT, AND PROCESS FOR PRODUCING THE SAME 有权
标题翻译：具有内置半导体元件的印刷电路板及其制造方法
公开(公告)号：US20110090657A1
公开(公告)日：2011-04-21
申请号：US12966251
申请日：2010-12-13
申请人： Yutaka YOSHINO , Takahiro Shirai , Shinji Kadono , Mineo Kawamoto , Minoru Enomoto , Masakatsu Goto , Makoto Araki , Naoki Toda
发明人： Yutaka YOSHINO , Takahiro Shirai , Shinji Kadono , Mineo Kawamoto , Minoru Enomoto , Masakatsu Goto , Makoto Araki , Naoki Toda
IPC分类号： H05K1/18
CPC分类号： H01L23/5389 , H01L25/105 , H01L2224/16237 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73204 , H01L2224/73265 , H01L2224/82039 , H01L2924/01004 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/3011 , H05K1/023 , H05K1/186 , H05K3/4602 , H05K3/4623 , H05K3/4652 , H05K2201/0187 , H05K2201/10674 , Y10T29/49146 , H01L2924/00014
摘要： A printed wiring board includes a built-in semiconductor element. A protective film is formed on a semiconductor element-mounted surface of a base substrate to which the built-in semiconductor element is connected to protect the semiconductor element-mounted surface excepting a mounting pad. Upper and side surfaces of the built-in semiconductor element are covered with a first insulating film formed by filling a sealing material. The first insulating film is covered with a second insulating film formed of an insulating resin melted from an insulating layer that is provided in side and upper portions of the built-in semiconductor element.
摘要翻译：印刷电路板包括内置的半导体元件。在与内置半导体元件连接的基底基板的半导体元件安装面上形成保护膜，以保护除了安装焊盘之外的半导体元件安装表面。通过填充密封材料形成的第一绝缘膜覆盖内置半导体元件的上表面和侧表面。第一绝缘膜被由设置在内置半导体元件的侧部和上部的绝缘层熔化的绝缘树脂形成的第二绝缘膜覆盖。

2. 发明授权

US4983862A Semiconductor integrated circuit with a bi-MOS input circuit for providing input signals to an internal logic block 失效
标题翻译：具有用于向内部逻辑块提供输入信号的双MOS输入电路的半导体集成电路
公开(公告)号：US4983862A
公开(公告)日：1991-01-08
申请号：US429489
申请日：1989-10-31
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177
CPC分类号： H03K19/09448 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09429 , H01L2924/0002
摘要： In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

3. 发明授权

US4879480A Bicmos gate array 失效
标题翻译：二门门阵列
公开(公告)号：US4879480A
公开(公告)日：1989-11-07
申请号：US240450
申请日：1988-09-02
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akiro Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akiro Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177
CPC分类号： H03K19/09448 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09429 , H01L2924/0002
摘要： In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
摘要翻译：在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由双极晶体管。因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

4. 发明授权

US4678943A Inverting logic buffer BICMOS switching circuit using an enabling switch for three-state operation with reduced dissipation 失效
标题翻译：反相逻辑缓冲器BICMOS开关电路使用启用开关进行三态操作，减少耗散
公开(公告)号：US4678943A
公开(公告)日：1987-07-07
申请号：US704209
申请日：1985-02-22
申请人： Akira Uragami , Yukio Suzuki , Shinji Kadono , Masahiro Iwamura , Ikuro Masuda , Tatsumi Yamauchi
发明人： Akira Uragami , Yukio Suzuki , Shinji Kadono , Masahiro Iwamura , Ikuro Masuda , Tatsumi Yamauchi
IPC分类号： H03K19/0175 , H03K17/04 , H03K17/60 , H03K19/0944
CPC分类号： H03K19/09448
摘要： A switching circuit comprises a pre-stage circuit coupled to receive an input signal and an output stage, wherein an output signal having a phase opposite to that of a signal of an input terminal IN can be obtained from an output terminal OUT of the output stage. The pre-stage circuit includes a p-channel MOSFET M1 and an n-channel MOSFET M2 that receive input signals at their gates. The output stage includes two NPN transistors Q1 and Q2 that are connected in series. The drain output of the p-channel MOSFET M1 is applied to the base of one of the transistors of the output stage, and the source output of the n-channel MOSFET M2 is applied to the base of the other of the transistors of the output stage. A third MOSFET M3 is coupled between a power supply and the p-channel MOSFET M1 and the n-channel MOSFET M2. When the MOSFET M3 is rendered non-conductive by a control signal EN, both MOSFETs M1 and M2 and both NPN transistors Q1 and Q2 become non-conductive irrespective of the signal of the input terminal IN. Under this condition, the output terminal OUT is in a floating state. Thus, the switching circuit is a tri-state circuit.
摘要翻译：开关电路包括耦合以接收输入信号的预级电路和输出级，其中可以从输出级的输出端OUT获得具有与输入端IN的信号相反的相位的输出信号。该前级电路包括在其栅极接收输入信号的p沟道MOSFET M1和n沟道MOSFET M2。输出级包括串联连接的两个NPN晶体管Q1和Q2。 p沟道MOSFET M1的漏极输出被施加到输出级的一个晶体管的基极，并且n沟道MOSFET M2的源极输出被施加到输出的晶体管的另一个的基极阶段。第三个MOSFET M3耦合在电源和p沟道MOSFET M1和n沟道MOSFET M2之间。当通过控制信号EN使MOSFET M3不导通时，无论输入端子IN的信号如何，MOSFET M1和M2以及两个NPN晶体管Q1和Q2都不导通。在这种情况下，输出端子OUT处于浮置状态。因此，开关电路是三态电路。

5. 发明授权

US5512847A BiCMOS tri-state output driver 失效
标题翻译： BiCMOS三态输出驱动器
公开(公告)号：US5512847A
公开(公告)日：1996-04-30
申请号：US321012
申请日：1994-10-06
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177 , H03K19/01
CPC分类号： H03K19/09448 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09429 , H01L2924/0002
摘要： In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
摘要翻译：在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由双极晶体管。因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

6. 发明授权

US07894200B2 Printed wiring board with built-in semiconductor element, and process for producing the same 有权
标题翻译：具有内置半导体元件的印刷电路板及其制造方法
公开(公告)号：US07894200B2
公开(公告)日：2011-02-22
申请号：US11913559
申请日：2006-11-28
申请人： Yutaka Yoshino , Takahiro Shirai , Shinji Kadono , Mineo Kawamoto , Minoru Enomoto , Masakatsu Goto , Makoto Araki , Naoki Toda
发明人： Yutaka Yoshino , Takahiro Shirai , Shinji Kadono , Mineo Kawamoto , Minoru Enomoto , Masakatsu Goto , Makoto Araki , Naoki Toda
IPC分类号： H05K1/18
CPC分类号： H01L23/5389 , H01L25/105 , H01L2224/16237 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73204 , H01L2224/73265 , H01L2224/82039 , H01L2924/01004 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/3011 , H05K1/023 , H05K1/186 , H05K3/4602 , H05K3/4623 , H05K3/4652 , H05K2201/0187 , H05K2201/10674 , Y10T29/49146 , H01L2924/00014
摘要： The present invention provides a printed wiring board with a built-in semiconductor element in which an insufficient or excessive amount of filled sealing material does not affect excellent adhesion of the printed wiring board to an overlying wiring board. The printed wiring board with a built-in semiconductor element comprises a built-in semiconductor element, in which at least the lower surface, the upper surface, or the side surface of the semiconductor element is covered with an insulating film, and an insulating layer is provided in the side and upper portions of the semiconductor element. There is also provided a process for producing a printed wiring board with a built-in semiconductor element, comprising the steps of mounting a semiconductor element on a base substrate and covering at least the lower surface, the upper surface, or the side surface of the semiconductor element with an insulating film, disposing and stacking a semicured insulating sheet in the side portion of the semiconductor element, and disposing and stacking a semicured insulating sheet in the upper portion of the semiconductor element.
摘要翻译：本发明提供一种具有内置半导体元件的印刷电路板，其中填充的密封材料的量不足或过量不会影响印刷电路板对上覆布线板的优异的粘附性。具有内置半导体元件的印刷线路板包括内置半导体元件，其中至少半导体元件的下表面，上表面或侧表面被绝缘膜覆盖，绝缘层设置在半导体元件的侧部和上部。还提供了一种用于制造具有内置半导体元件的印刷线路板的方法，包括以下步骤：将半导体元件安装在基底基板上，并且至少覆盖基底基板的下表面，上表面或侧表面具有绝缘膜的半导体元件，在半导体元件的侧部设置和层叠半固化绝缘片，并且在半导体元件的上部设置和层叠半固化绝缘片。

7. 发明授权

US4689503A Level conversion circuitry for a semiconductor integrated circuit utilizing bis CMOS circuit elements 失效
标题翻译：利用双CMOS电路元件的半导体集成电路的电平转换电路
公开(公告)号：US4689503A
公开(公告)日：1987-08-25
申请号：US575567
申请日：1984-01-31
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177 , H03K19/01 , H03K19/013 , H03K19/017
CPC分类号： H03K19/09448 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09429 , H01L2924/0002
摘要： In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
摘要翻译：在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由双极晶体管。因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

8. 发明授权

US4158883A Refresh control system 失效
标题翻译：刷新控制系统
公开(公告)号：US4158883A
公开(公告)日：1979-06-19
申请号：US737350
申请日：1976-11-01
申请人： Shinji Kadono , Tsuneyo Chiba , Kiyoshi Umezawa
发明人： Shinji Kadono , Tsuneyo Chiba , Kiyoshi Umezawa
IPC分类号： G06F12/00 , G06F13/16 , G11C11/406 , G06F13/00 , G11C7/00
CPC分类号： G11C11/406 , G06F13/1636
摘要： In a refresh control system including a main memory having a volatile memory, at least one processing unit for accessing the main memory, a memory bus for effecting signal transfer between the main memory and the processing unit and a supervision circuit for allotting use of the memory bus in response to a request signal, the refresh control system is characterized by a refresh control circuit for transferring the request signal to the supervision circuit at the time the refresh signal is required and for commanding the initiation of the refresh operation to the main memory in response to a grant signal from the supervision circuit.
摘要翻译：在包括具有易失性存储器的主存储器的刷新控制系统中，用于访问主存储器的至少一个处理单元，用于在主存储器和处理单元之间进行信号传送的存储器总线和用于分配存储器的使用的监控电路总线响应于请求信号，刷新控制系统的特征在于刷新控制电路，用于在需要刷新信号时将请求信号传送到监控电路，并且用于命令向主存储器启动刷新操作响应来自监控电路的授权信号。

9. 发明授权

US08035979B2 Printed wiring board with built-in semiconductor element, and process for producing the same 有权
标题翻译：具有内置半导体元件的印刷电路板及其制造方法
公开(公告)号：US08035979B2
公开(公告)日：2011-10-11
申请号：US12966251
申请日：2010-12-13
申请人： Yutaka Yoshino , Takahiro Shirai , Shinji Kadono , Mineo Kawamoto , Minoru Enomoto , Masakatsu Goto , Makoto Araki , Naoki Toda
发明人： Yutaka Yoshino , Takahiro Shirai , Shinji Kadono , Mineo Kawamoto , Minoru Enomoto , Masakatsu Goto , Makoto Araki , Naoki Toda
IPC分类号： H05K1/18
CPC分类号： H01L23/5389 , H01L25/105 , H01L2224/16237 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73204 , H01L2224/73265 , H01L2224/82039 , H01L2924/01004 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/3011 , H05K1/023 , H05K1/186 , H05K3/4602 , H05K3/4623 , H05K3/4652 , H05K2201/0187 , H05K2201/10674 , Y10T29/49146 , H01L2924/00014
摘要： A printed wiring board includes a built-in semiconductor element. A protective film is formed on a semiconductor element-mounted surface of a base substrate to which the built-in semiconductor element is connected to protect the semiconductor element-mounted surface excepting a mounting pad. Upper and side surfaces of the built-in semiconductor element are covered with a first insulating film formed by filling a sealing material. The first insulating film is covered with a second insulating film formed of an insulating resin melted from an insulating layer that is provided in side and upper portions of the built-in semiconductor element.
摘要翻译：印刷电路板包括内置的半导体元件。在与内置半导体元件连接的基底基板的半导体元件安装面上形成保护膜，以保护除了安装焊盘之外的半导体元件安装表面。通过填充密封材料形成的第一绝缘膜覆盖内置半导体元件的上表面和侧表面。第一绝缘膜被由设置在内置半导体元件的侧部和上部的绝缘层熔化的绝缘树脂形成的第二绝缘膜覆盖。

10. 发明授权

US5495183A Level conversion circuitry for a semiconductor integrated circuit 失效
标题翻译：半导体集成电路的电平转换电路
公开(公告)号：US5495183A
公开(公告)日：1996-02-27
申请号：US440335
申请日：1995-05-12
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Urragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Urragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177
CPC分类号： H03K19/1778 , H03K19/017518 , H03K19/01806 , H03K19/09429 , H03K19/09448 , H03K19/17784 , H03K19/17792
摘要： In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
摘要翻译：在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由双极晶体管。因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

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