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1. 发明授权

US07713817B2 Methods of forming semiconductor structures 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US07713817B2
公开(公告)日：2010-05-11
申请号：US11968281
申请日：2008-01-02
申请人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
发明人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
IPC分类号： H01L21/8242
CPC分类号： H01L21/288 , H01L21/76805 , H01L21/76816 , H01L21/76879 , H01L23/522 , H01L27/10855 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.
摘要翻译：可以利用无电镀形成与半导体衬底相关的电互连。例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。随后，导电材料可以在开口内无电镀，以在开口内形成电接触。延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

2. 发明授权

US07335935B2 Semiconductor structures 有权
标题翻译：半导体结构
公开(公告)号：US07335935B2
公开(公告)日：2008-02-26
申请号：US11188235
申请日：2005-07-22
申请人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
发明人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L21/288 , H01L21/76805 , H01L21/76816 , H01L21/76879 , H01L23/522 , H01L27/10855 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.
摘要翻译：可以利用无电镀形成与半导体衬底相关的电互连。例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。随后，导电材料可以在开口内无电镀，以在开口内形成电接触。延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

3. 发明申请

US20100190314A1 Methods Of Forming Semiconductor Structures 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US20100190314A1
公开(公告)日：2010-07-29
申请号：US12751786
申请日：2010-03-31
申请人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
发明人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
IPC分类号： H01L21/02
CPC分类号： H01L21/288 , H01L21/76805 , H01L21/76816 , H01L21/76879 , H01L23/522 , H01L27/10855 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.
摘要翻译：可以利用无电镀形成与半导体衬底相关的电互连。例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。随后，导电材料可以在开口内无电镀，以在开口内形成电接触。延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

4. 发明授权

US07005379B2 Semiconductor processing methods for forming electrical contacts 失效
标题翻译：用于形成电触头的半导体加工方法
公开(公告)号：US07005379B2
公开(公告)日：2006-02-28
申请号：US10822030
申请日：2004-04-08
申请人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
发明人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
IPC分类号： H01L21/44 , H01L21/8242 , H01L21/20
CPC分类号： H01L21/288 , H01L21/76805 , H01L21/76816 , H01L21/76879 , H01L23/522 , H01L27/10855 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.
摘要翻译：可以利用无电镀形成与半导体衬底相关的电互连。例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。随后，导电材料可以在开口内无电镀，以在开口内形成电接触。延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

5. 发明授权

US08232206B2 Methods of forming electrical contacts to structures that are at different heights over a substrate relative to one another 有权
标题翻译：将电触点形成在相对于彼此在衬底上不同高度的结构的方法
公开(公告)号：US08232206B2
公开(公告)日：2012-07-31
申请号：US12751786
申请日：2010-03-31
申请人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
发明人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
IPC分类号： H01L21/44
CPC分类号： H01L21/288 , H01L21/76805 , H01L21/76816 , H01L21/76879 , H01L23/522 , H01L27/10855 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.
摘要翻译：可以利用无电镀形成与半导体衬底相关的电互连。例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。随后，导电材料可以在开口内无电镀，以在开口内形成电接触。延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

6. 发明授权

US08163613B2 Methods of forming a plurality of capacitors 有权
标题翻译：形成多个电容器的方法
公开(公告)号：US08163613B2
公开(公告)日：2012-04-24
申请号：US12823797
申请日：2010-06-25
申请人： Fred D. Fishburn
发明人： Fred D. Fishburn
IPC分类号： H01L21/8242
CPC分类号： H01L27/10817 , H01L27/0207 , H01L27/10852 , H01L28/91
摘要： A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two masking steps is used to form an array of first openings over a plurality of storage node contacts. A later of the two masking steps is used to form an array of second openings received partially over and partially offset from the array of first openings. Overlapping portions of the first and second openings are received over the storage node contacts. After both of the two masking steps, conductive material of the individual capacitor electrodes is deposited into the overlapping portions of each of the first and second openings. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.
摘要翻译：形成多个电容器的方法包括使用两个掩蔽步骤形成多个单独的电容器电极。使用两个屏蔽步骤中较早的一个来形成多个存储节点触点上的第一开口的阵列。两个掩蔽步骤之后的后面被用于形成部分地在第一开口的阵列上部分偏移并且部分地偏离第一开口阵列的第二开口的阵列。第一和第二开口的重叠部分被接收在存储节点触点上。在两个掩模步骤之后，单个电容器电极的导电材料沉积到第一和第二开口中的每一个的重叠部分中。各个电容器电极被并入到多个电容器中。考虑了其他方面和实现。

7. 发明授权

US07517754B2 Methods of forming semiconductor constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US07517754B2
公开(公告)日：2009-04-14
申请号：US11971747
申请日：2008-01-09
申请人： Terrence B. McDaniel , Scott A. Southwick , Fred D. Fishburn
发明人： Terrence B. McDaniel , Scott A. Southwick , Fred D. Fishburn
IPC分类号： H01L21/8242 , H01L21/4763
CPC分类号： H01L27/10885 , H01L27/10852 , H01L27/10894 , H01L27/10897 , H01L28/90
摘要： The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The bitlines can be formed within trenches having faceted top portions. The invention also includes semiconductor structures containing trenches with faceted top portions, and containing bitlines within the trenches.
摘要翻译：本发明包括形成半导体结构的方法，其中在位线之间形成导电结构以与存储节点接触电连接。位线可以形成在具有多边形顶部的沟槽内。本发明还包括含有具有多面顶部的沟槽并且在沟槽内包含位线的半导体结构。

8. 发明授权

US07384847B2 Methods of forming DRAM arrays 有权
标题翻译：形成DRAM阵列的方法
公开(公告)号：US07384847B2
公开(公告)日：2008-06-10
申请号：US11111625
申请日：2005-04-21
申请人： Luan C. Tran , Fred D. Fishburn
发明人： Luan C. Tran , Fred D. Fishburn
IPC分类号： H01L21/336
CPC分类号： H01L27/10888 , H01L27/1052 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/115 , H01L27/11521 , H01L27/11531 , H01L27/24 , Y10S257/906 , Y10S257/908
摘要： The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.
摘要翻译：本发明包括可用于形成存储器阵列的存储器阵列和方法。在存储器阵列制造期间可以使用图案化蚀刻停止件，其中蚀刻停止覆盖存储节点接触位置，同时将开口留在位线接触位置。可以在蚀刻停止点上方和位线接触位置上形成绝缘材料，并且可以通过绝缘材料形成沟槽。可以在沟槽内提供导电材料以形成与位线接触位置电接触的位线互连线，并且通过蚀刻停止件与存储节点接触位置电隔离。在随后的处理中，可以通过蚀刻停止件向存储节点接触位置形成开口。然后可以在开口内形成存储器存储装置，并与存储节点接触位置电接触。

9. 发明授权

US07153778B2 Methods of forming openings, and methods of forming container capacitors 有权
公开(公告)号：US07153778B2
公开(公告)日：2006-12-26
申请号：US10783843
申请日：2004-02-20
申请人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Yoshiki Hishiro , Ulrich C. Boettiger , Richard D. Holscher
发明人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Yoshiki Hishiro , Ulrich C. Boettiger , Richard D. Holscher
IPC分类号： H01L21/3205
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L27/10852 , H01L28/91 , Y10S438/942 , Y10S438/946
摘要： A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.

10. 发明授权

US07060570B2 Methods of fabricating multiple sets of field effect transistors 失效
公开(公告)号：US07060570B2
公开(公告)日：2006-06-13
申请号：US10914825
申请日：2004-08-09
申请人： Fred D. Fishburn , Martin Ceredig Roberts
发明人： Fred D. Fishburn , Martin Ceredig Roberts
IPC分类号： H01L21/8232
CPC分类号： H01L21/31053 , H01L21/32139 , H01L21/82345 , H01L21/823828 , H01L21/823842 , Y10S438/941
摘要： The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate layer are patterned and etched to form a first set of conductive gate constructions over the substrate. A dielectric material is formed and planarized over the first set of gate constructions. Thereafter, the insulative capping layer and the conductive gate layer are patterned and etched to form a second set of conductive gate constructions over the substrate. Other aspects and implementations are contemplated.

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