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1. 发明授权

US07153778B2 Methods of forming openings, and methods of forming container capacitors 有权
公开(公告)号：US07153778B2
公开(公告)日：2006-12-26
申请号：US10783843
申请日：2004-02-20
申请人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Yoshiki Hishiro , Ulrich C. Boettiger , Richard D. Holscher
发明人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Yoshiki Hishiro , Ulrich C. Boettiger , Richard D. Holscher
IPC分类号： H01L21/3205
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L27/10852 , H01L28/91 , Y10S438/942 , Y10S438/946
摘要： A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.

2. 发明授权

US07538036B2 Methods of forming openings, and methods of forming container capacitors 失效
标题翻译：形成开口的方法，以及形成容器电容器的方法
公开(公告)号：US07538036B2
公开(公告)日：2009-05-26
申请号：US11216759
申请日：2005-08-31
申请人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Yoshiki Hishiro , Ulrich C. Boettiger , Richard D. Holscher
发明人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Yoshiki Hishiro , Ulrich C. Boettiger , Richard D. Holscher
IPC分类号： H01L21/3205
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L27/10852 , H01L28/91 , Y10S438/942 , Y10S438/946
摘要： A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.
摘要翻译：图案化掩模可以如下形成。在掩模层上形成第一图案化的光致抗蚀剂，并在第一蚀刻进入掩模层期间使用。第一蚀刻延伸到掩模层中的深度不到完全通过掩模层的深度。随后在掩模层上形成第二图案化的光致抗蚀剂，并在第二次蚀刻进入掩模层期间利用。组合的第一和第二蚀刻形成完全延伸穿过掩模层的开口，从而在掩模层中形成掩模层。图案化掩模可以用于在掩模下面的衬底中形成图案。形成在基板中的图案可以对应于电容器容器开口的阵列。可以在开口内形成电容结构。电容器结构可以并入DRAM阵列中。

3. 发明授权

US07321149B2 Capacitor structures, and DRAM arrays 有权
标题翻译：电容结构和DRAM阵列
公开(公告)号：US07321149B2
公开(公告)日：2008-01-22
申请号：US11187210
申请日：2005-07-22
申请人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Richard D. Holscher
发明人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Richard D. Holscher
IPC分类号： H01L29/72
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L27/10852 , H01L28/91 , Y10S438/942 , Y10S438/946
摘要： A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.
摘要翻译：图案化掩模可以如下形成。在掩模层上形成第一图案化的光致抗蚀剂，并在第一蚀刻进入掩模层期间使用。第一蚀刻延伸到掩模层中的深度不到完全通过掩模层的深度。随后在掩模层上形成第二图案化的光致抗蚀剂，并在第二次蚀刻进入掩模层期间利用。组合的第一和第二蚀刻形成完全延伸穿过掩模层的开口，从而在掩模层中形成掩模层。图案化掩模可以用于在掩模下面的衬底中形成图案。形成在基板中的图案可以对应于电容器容器开口的阵列。可以在开口内形成电容结构。电容器结构可以并入DRAM阵列中。

4. 发明授权

US07384847B2 Methods of forming DRAM arrays 有权
标题翻译：形成DRAM阵列的方法
公开(公告)号：US07384847B2
公开(公告)日：2008-06-10
申请号：US11111625
申请日：2005-04-21
申请人： Luan C. Tran , Fred D. Fishburn
发明人： Luan C. Tran , Fred D. Fishburn
IPC分类号： H01L21/336
CPC分类号： H01L27/10888 , H01L27/1052 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/115 , H01L27/11521 , H01L27/11531 , H01L27/24 , Y10S257/906 , Y10S257/908
摘要： The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.
摘要翻译：本发明包括可用于形成存储器阵列的存储器阵列和方法。在存储器阵列制造期间可以使用图案化蚀刻停止件，其中蚀刻停止覆盖存储节点接触位置，同时将开口留在位线接触位置。可以在蚀刻停止点上方和位线接触位置上形成绝缘材料，并且可以通过绝缘材料形成沟槽。可以在沟槽内提供导电材料以形成与位线接触位置电接触的位线互连线，并且通过蚀刻停止件与存储节点接触位置电隔离。在随后的处理中，可以通过蚀刻停止件向存储节点接触位置形成开口。然后可以在开口内形成存储器存储装置，并与存储节点接触位置电接触。

5. 发明授权

US07135401B2 Methods of forming electrical connections for semiconductor constructions 有权
标题翻译：形成半导体结构电连接的方法
公开(公告)号：US07135401B2
公开(公告)日：2006-11-14
申请号：US10841708
申请日：2004-05-06
申请人： Luan C. Tran , Fred D. Fishburn
发明人： Luan C. Tran , Fred D. Fishburn
IPC分类号： H01L21/4763
CPC分类号： H01L21/7681 , H01L21/76895 , H01L21/823475
摘要： The invention includes methods for forming electrical connections associated with semiconductor constructions. A semiconductor substrate is provided which has a conductive line thereover, and which has at least two diffusion regions adjacent the conductive line. A patterned etch stop is formed over the diffusion regions. The patterned etch stop has a pair of openings extending through it, with the openings being along a row substantially parallel to an axis of the line. An insulative material is formed over the etch stop. The insulative material is exposed to an etch to form a trench within the insulative material, and to extend the openings from the etch stop to the diffusion regions. At least a portion of the trench is directly over the openings and extends along the axis of the line. An electrically conductive material is formed within the openings and within the trench.
摘要翻译：本发明包括用于形成与半导体结构相关联的电连接的方法。提供一种半导体衬底，其具有其上的导电线，并且具有与导电线相邻的至少两个扩散区域。在扩散区域上形成图案化的蚀刻停止层。图案化蚀刻停止件具有延伸穿过其的一对开口，其中开口沿着大致平行于该线的轴线。在蚀刻停止点上形成绝缘材料。绝缘材料暴露于蚀刻以在绝缘材料内形成沟槽，并且将开口从蚀刻停止件延伸到扩散区域。沟槽的至少一部分直接在开口上方并且沿着线的轴线延伸。在开口内和沟槽内形成导电材料。

6. 发明授权

US07279379B2 Methods of forming memory arrays; and methods of forming contacts to bitlines 有权
标题翻译：形成存储器阵列的方法以及形成与位线的接触的方法
公开(公告)号：US07279379B2
公开(公告)日：2007-10-09
申请号：US10832543
申请日：2004-04-26
申请人： Luan C. Tran , Fred D. Fishburn
发明人： Luan C. Tran , Fred D. Fishburn
IPC分类号： H01L21/00
CPC分类号： H01L27/10888 , H01L27/1052 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/115 , H01L27/11521 , H01L27/11531 , H01L27/24 , Y10S257/906 , Y10S257/908
摘要： The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.
摘要翻译：本发明包括可用于形成存储器阵列的存储器阵列和方法。在存储器阵列制造期间可以使用图案化蚀刻停止件，其中蚀刻停止覆盖存储节点接触位置，同时将开口留在位线接触位置。可以在蚀刻停止点上方和位线接触位置上形成绝缘材料，并且可以通过绝缘材料形成沟槽。可以在沟槽内提供导电材料以形成与位线接触位置电接触的位线互连线，并且通过蚀刻停止件与存储节点接触位置电隔离。在随后的处理中，可以通过蚀刻停止件向存储节点接触位置形成开口。然后可以在开口内形成存储器存储装置，并与存储节点接触位置电接触。

7. 发明授权

US07205227B2 Methods of forming CMOS constructions 有权
标题翻译：形成CMOS结构的方法
公开(公告)号：US07205227B2
公开(公告)日：2007-04-17
申请号：US11353592
申请日：2006-02-14
申请人： Luan C. Tran , Fred D. Fishburn
发明人： Luan C. Tran , Fred D. Fishburn
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/7681 , H01L21/76895 , H01L21/823475
摘要： The invention includes methods for forming electrical connections associated with semiconductor constructions. A semiconductor substrate is provided which has a conductive line thereover, and which has at least two diffusion regions adjacent the conductive line. A patterned etch stop is formed over the diffusion regions. The patterned etch stop has a pair of openings extending through it, with the openings being along a row substantially parallel to an axis of the line. An insulative material is formed over the etch stop. The insulative material is exposed to an etch to form a trench within the insulative material, and to extend the openings from the etch stop to the diffusion regions. At least a portion of the trench is directly over the openings and extends along the axis of the line. An electrically conductive material is formed within the openings and within the trench.
摘要翻译：本发明包括用于形成与半导体结构相关联的电连接的方法。提供一种半导体衬底，其具有其上的导电线，并且具有与导电线相邻的至少两个扩散区域。在扩散区域上形成图案化的蚀刻停止层。图案化蚀刻停止件具有延伸穿过其的一对开口，其中开口沿着大致平行于该线的轴线。在蚀刻停止点上形成绝缘材料。绝缘材料暴露于蚀刻以在绝缘材料内形成沟槽，并且将开口从蚀刻停止件延伸到扩散区域。沟槽的至少一部分直接在开口上方并且沿着线的轴线延伸。在开口内和沟槽内形成导电材料。

8. 发明授权

US07659161B2 Methods of forming storage nodes for a DRAM array 有权
标题翻译：形成DRAM阵列的存储节点的方法
公开(公告)号：US07659161B2
公开(公告)日：2010-02-09
申请号：US11111360
申请日：2005-04-21
申请人： Luan C. Tran , Fred D. Fishburn
发明人： Luan C. Tran , Fred D. Fishburn
IPC分类号： H01L21/00
CPC分类号： H01L27/10888 , H01L27/1052 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/115 , H01L27/11521 , H01L27/11531 , H01L27/24 , Y10S257/906 , Y10S257/908
摘要： The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.
摘要翻译：本发明包括可用于形成存储器阵列的存储器阵列和方法。在存储器阵列制造期间可以使用图案化蚀刻停止件，其中蚀刻停止覆盖存储节点接触位置，同时将开口留在位线接触位置。可以在蚀刻停止点上方和位线接触位置上形成绝缘材料，并且可以通过绝缘材料形成沟槽。可以在沟槽内提供导电材料以形成与位线接触位置电接触的位线互连线，并且通过蚀刻停止件与存储节点接触位置电隔离。在随后的处理中，可以通过蚀刻停止件向存储节点接触位置形成开口。然后可以在开口内形成存储器存储装置，并与存储节点接触位置电接触。

9. 发明授权

US07288806B2 DRAM arrays 有权
标题翻译： DRAM阵列
公开(公告)号：US07288806B2
公开(公告)日：2007-10-30
申请号：US11111605
申请日：2005-04-21
申请人： Luan C. Tran , Fred D. Fishburn
发明人： Luan C. Tran , Fred D. Fishburn
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10888 , H01L27/1052 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/115 , H01L27/11521 , H01L27/11531 , H01L27/24 , Y10S257/906 , Y10S257/908
摘要： The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.
摘要翻译：本发明包括可用于形成存储器阵列的存储器阵列和方法。在存储器阵列制造期间可以使用图案化蚀刻停止件，其中蚀刻停止覆盖存储节点接触位置，同时将开口留在位线接触位置。可以在蚀刻停止点上方和位线接触位置上形成绝缘材料，并且可以通过绝缘材料形成沟槽。可以在沟槽内提供导电材料以形成与位线接触位置电接触的位线互连线，并且通过蚀刻停止件与存储节点接触位置电隔离。在随后的处理中，可以通过蚀刻停止件向存储节点接触位置形成开口。然后可以在开口内形成存储器存储装置，并与存储节点接触位置电接触。

10. 发明授权

US07202127B2 Methods of forming a plurality of capacitors 有权
标题翻译：形成多个电容器的方法
公开(公告)号：US07202127B2
公开(公告)日：2007-04-10
申请号：US10928931
申请日：2004-08-27
申请人： Brett W. Busch , Fred D. Fishburn , James Rominger
发明人： Brett W. Busch , Fred D. Fishburn , James Rominger
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10852
摘要： A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is greater within the capacitor electrode-forming material than is a second set of the openings. Conductive first capacitor electrode material is formed therein. A sacrificial retaining structure is formed elevationally over both the first capacitor electrode material and the capacitor electrode-forming material, leaving some of the capacitor electrode-forming material exposed. With the retaining structure in place, at least some of the capacitor electrode-forming material is etched from the substrate effective to expose outer sidewall surfaces of the first capacitor electrode material. Then, the sacrificial retaining structure is removed from the substrate, and then capacitor dielectric material and conductive second capacitor electrode material are formed over the outer sidewall surfaces of the first capacitor electrode material formed within the first and second sets of capacitor openings.
摘要翻译：在电容器电极形成材料内形成多个电容器电极开口。第一组开口形成为在电容器电极形成材料内比第二组开口更大的深度。在其中形成导电的第一电容器电极材料。牺牲保持结构在第一电容器电极材料和电容器电极形成材料两者之上形成高度，从而使一些电容器电极形成材料暴露。在保持结构就位的情况下，有效地暴露出第一电容器电极材料的外侧壁表面的至少一些电容器电极形成材料被从衬底上蚀刻。然后，从衬底去除牺牲保持结构，然后在形成在第一组和第二组电容器开口内的第一电容器电极材料的外侧壁表面上形成电容器电介质材料和导电的第二电容器电极材料。

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