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1. 发明授权

US07713817B2 Methods of forming semiconductor structures 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US07713817B2
公开(公告)日：2010-05-11
申请号：US11968281
申请日：2008-01-02
申请人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
发明人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
IPC分类号： H01L21/8242
CPC分类号： H01L21/288 , H01L21/76805 , H01L21/76816 , H01L21/76879 , H01L23/522 , H01L27/10855 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.
摘要翻译：可以利用无电镀形成与半导体衬底相关的电互连。例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。随后，导电材料可以在开口内无电镀，以在开口内形成电接触。延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

2. 发明申请

US20100190314A1 Methods Of Forming Semiconductor Structures 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US20100190314A1
公开(公告)日：2010-07-29
申请号：US12751786
申请日：2010-03-31
申请人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
发明人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
IPC分类号： H01L21/02
CPC分类号： H01L21/288 , H01L21/76805 , H01L21/76816 , H01L21/76879 , H01L23/522 , H01L27/10855 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.
摘要翻译：可以利用无电镀形成与半导体衬底相关的电互连。例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。随后，导电材料可以在开口内无电镀，以在开口内形成电接触。延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

3. 发明授权

US07005379B2 Semiconductor processing methods for forming electrical contacts 失效
标题翻译：用于形成电触头的半导体加工方法
公开(公告)号：US07005379B2
公开(公告)日：2006-02-28
申请号：US10822030
申请日：2004-04-08
申请人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
发明人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
IPC分类号： H01L21/44 , H01L21/8242 , H01L21/20
CPC分类号： H01L21/288 , H01L21/76805 , H01L21/76816 , H01L21/76879 , H01L23/522 , H01L27/10855 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.
摘要翻译：可以利用无电镀形成与半导体衬底相关的电互连。例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。随后，导电材料可以在开口内无电镀，以在开口内形成电接触。延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

4. 发明授权

US07335935B2 Semiconductor structures 有权
标题翻译：半导体结构
公开(公告)号：US07335935B2
公开(公告)日：2008-02-26
申请号：US11188235
申请日：2005-07-22
申请人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
发明人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L21/288 , H01L21/76805 , H01L21/76816 , H01L21/76879 , H01L23/522 , H01L27/10855 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.
摘要翻译：可以利用无电镀形成与半导体衬底相关的电互连。例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。随后，导电材料可以在开口内无电镀，以在开口内形成电接触。延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

5. 发明授权

US08232206B2 Methods of forming electrical contacts to structures that are at different heights over a substrate relative to one another 有权
标题翻译：将电触点形成在相对于彼此在衬底上不同高度的结构的方法
公开(公告)号：US08232206B2
公开(公告)日：2012-07-31
申请号：US12751786
申请日：2010-03-31
申请人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
发明人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
IPC分类号： H01L21/44
CPC分类号： H01L21/288 , H01L21/76805 , H01L21/76816 , H01L21/76879 , H01L23/522 , H01L27/10855 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.
摘要翻译：可以利用无电镀形成与半导体衬底相关的电互连。例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。随后，导电材料可以在开口内无电镀，以在开口内形成电接触。延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

6. 发明申请

US20080102596A1 Methods of Forming Semiconductor Structures 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US20080102596A1
公开(公告)日：2008-05-01
申请号：US11968281
申请日：2008-01-02
申请人： Nishant Sinha , Dinesh Chopra , Fred Fishburn
发明人： Nishant Sinha , Dinesh Chopra , Fred Fishburn
IPC分类号： H01L21/02 , H01L21/4763
CPC分类号： H01L21/288 , H01L21/76805 , H01L21/76816 , H01L21/76879 , H01L23/522 , H01L27/10855 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.
摘要翻译：可以利用无电镀形成与半导体衬底相关的电互连。例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。随后，导电材料可以在开口内无电镀，以在开口内形成电接触。延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

7. 发明申请

US20060252268A1 Slurry for use in polishing semiconductor device conductive structures that include copper and tungsten and polishing methods 失效
公开(公告)号：US20060252268A1
公开(公告)日：2006-11-09
申请号：US11484957
申请日：2006-07-12
申请人： Dinesh Chopra , Nishant Sinha
发明人： Dinesh Chopra , Nishant Sinha
IPC分类号： H01L21/461 , B44C1/22 , C03C15/00
CPC分类号： C23F3/04 , C09G1/02 , C23F3/06 , H01L21/3212
摘要： A method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer. The method includes use of a polishing pad with a slurry solution in which copper and a material, such as tungsten, of the barrier layer are removed at substantially the same rate. The slurry is formulated so as to oxidize copper and a material of the barrier layer at substantially the same rates. Thus, copper and the barrier layer material have substantially the same oxidation energies in the slurry. Systems for substantially polishing copper conductive structures and adjacent barrier structures on semiconductor device structures are also disclosed.

8. 发明授权

US07118686B2 Slurry for use in polishing semiconductor device conductive structures that include copper and tungsten and polishing methods 有权
公开(公告)号：US07118686B2
公开(公告)日：2006-10-10
申请号：US10326651
申请日：2002-12-19
申请人： Nishant Sinha , Dinesh Chopra
发明人： Nishant Sinha , Dinesh Chopra
IPC分类号： C09K13/00
CPC分类号： C23F3/04 , C09G1/02 , C23F3/06 , H01L21/3212
摘要： A method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer. The method includes use of a polishing pad with a slurry solution in which copper and a material, such as tungsten, of the barrier layer are removed at substantially the same rate. The slurry is formulated so as to oxidize copper and a material of the barrier layer at substantially the same rates. Thus, copper and the barrier layer material have substantially the same oxidation energies in the slurry. Systems for substantially polishing copper conductive structures and adjacent barrier structures on semiconductor device structures are also disclosed.

9. 发明申请

US20050153556A1 Methods for polishing copper features of semiconductor devices structures 审中-公开
标题翻译：抛光半导体器件结构铜特征的方法
公开(公告)号：US20050153556A1
公开(公告)日：2005-07-14
申请号：US11011363
申请日：2004-12-14
申请人： Dinesh Chopra , Nishant Sinha
发明人： Dinesh Chopra , Nishant Sinha
IPC分类号： B24B37/04 , C09K13/00 , H01L21/304 , H01L21/321 , H01L21/302 , H01L21/461
CPC分类号： B24B37/0056 , B24B37/04 , H01L21/3212
摘要： A method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer includes use of a slurry that is formulated so as to oxidize copper at substantially the same rate as or at a faster rate than a material of the barrier layer is oxidized. Thus, copper and the barrier layer material have substantially the same oxidation energies in the slurry or the oxidation energy of the barrier layer material in the slurry may be greater than that of copper. The slurry may be configured for use with a fixed-abrasive type polishing pad and, therefore, may be substantially abrasive-free.
摘要翻译：用于基本上同时抛光半导体器件结构和相邻阻挡层的铜导电结构的方法包括使用浆料，其被配制为以与屏障材料基本相同的速率或更快的速率氧化铜层被氧化。因此，铜和阻挡层材料在浆料中具有基本相同的氧化能量，或者浆料中的阻挡层材料的氧化能可能大于铜的氧化能。浆料可以被配置为与固定研磨型抛光垫一起使用，因此可以是基本上无磨蚀的。

10. 发明授权

US06602117B1 Slurry for use with fixed-abrasive polishing pads in polishing semiconductor device conductive structures that include copper and tungsten and polishing methods 失效
标题翻译：用于抛光半导体器件导电结构（包括铜和钨）和抛光方法的固定研磨抛光垫的浆料
公开(公告)号：US06602117B1
公开(公告)日：2003-08-05
申请号：US09651808
申请日：2000-08-30
申请人： Dinesh Chopra , Nishant Sinha
发明人： Dinesh Chopra , Nishant Sinha
IPC分类号： B24B100
CPC分类号： B24B37/0056 , B24B37/04 , H01L21/3212
摘要： A method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer. The method includes use of a fixed-abrasive type polishing pad with a substantially abrasive-free slurry in which copper is removed at a rate that is substantially the same as or faster than a rate at which a material, such as tungsten, of the barrier layer is removed. The slurry is formulated so as to oxidize copper at substantially the same rate as or at a faster rate than a material of the barrier layer is oxidized. Thus, copper and the barrier layer material have substantially the same oxidation energies in the slurry or the oxidation energy of the barrier layer material in the slurry may be greater than that of copper. Systems for substantially polishing copper conductive structures and adjacent barrier structures on semiconductor device structures are also disclosed.
摘要翻译：一种用于基本上同时抛光半导体器件结构和相邻阻挡层的铜导电结构的方法。该方法包括使用固体研磨型抛光垫，其具有基本上无磨料的浆料，其中以与阻挡层材料（例如钨）的材料基本相同或更快的速率除去铜图层被删除。将浆料配制成以与阻挡层的材料氧化为基本相同的速率或以更快的速率氧化铜。因此，铜和阻挡层材料在浆料中具有基本相同的氧化能量，或者浆料中的阻挡层材料的氧化能可能大于铜的氧化能。还公开了用于在半导体器件结构上基本抛光铜导电结构和相邻阻挡结构的系统。

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