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1. 发明授权

US6162699A Method for generating limited isolation trench width structures and a device having a narrow isolation trench surrounding its periphery 有权
标题翻译：用于产生有限隔离沟槽宽度结构的方法和具有围绕其周边的窄隔离沟槽的器件
公开(公告)号：US6162699A
公开(公告)日：2000-12-19
申请号：US181561
申请日：1998-10-29
申请人： Larry Wang , Nick Kepler , Olov Karlsson , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
发明人： Larry Wang , Nick Kepler , Olov Karlsson , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , Y10S438/942 , Y10S438/945
摘要： A method for effectively generating limited trench width isolation structures without incurring the susceptibility to dishing problems to produce high quality ICs employs a computer to generate data representing a trench isolation mask capable of being used to etch a limited trench width isolation structure about the perimeter of active region layers, polygate layers, and Local Interconnect (LI) layers. Once the various layers are defined using data on the computer and configured such that chip real estate is maximized, then the boundaries are combined using, for example, logical OR operators to produce data representing an overall composite layer. Once the data representing the composite layer is determined, the data is expanded evenly outward in all horizontal directions by a predetermined amount, .lambda., to produce data representing a preliminary expanded region. Any narrow regions are then merged together with the preliminary expanded region to produce data representing a final expanded region, which is used to produce a mask employed to produce an even width trench about the perimeter of the composite layer. The computer then generates the mask according to the results achieved and the isolation trenches are etched. The resulting isolation trenches prevent short-circuits from occurring between the various electrical devices on the semiconductor device.
摘要翻译：用于有效地产生有限的沟槽宽度隔离结构而不会产生对凹陷问题的敏感性以产生高质量IC的方法使用计算机产生表示沟槽隔离掩模的数据，所述沟槽隔离掩模能够用于围绕有源的周边刻蚀有限的沟槽宽度隔离结构区域层，多晶硅层和局部互连（LI）层。一旦使用计算机上的数据来定义各个层，并且配置为使得芯片空间最大化，则使用例如逻辑OR运算符来组合边界以产生表示整个复合层的数据。一旦确定了表示复合层的数据，则数据在所有水平方向上均匀地向外扩展预定量的λ，以产生表示初步扩展区域的数据。然后将任何窄区域与预扩展区域合并以产生表示最终扩展区域的数据，其用于产生用于围绕复合层的周边产生均匀宽度沟槽的掩模。然后，计算机根据实现的结果生成掩模，并且蚀刻隔离沟槽。所产生的隔离沟槽防止在半导体器件上的各种电器件之间发生短路。

2. 发明授权

US06380047B1 Shallow trench isolation formation with two source/drain masks and simplified planarization mask 有权
标题翻译：浅沟槽隔离形成，具有两个源/漏屏蔽和简化的平面化掩模
公开(公告)号：US06380047B1
公开(公告)日：2002-04-30
申请号：US09634990
申请日：2000-08-08
申请人： Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Ibok , Christopher F. Lyons
发明人： Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate with improved planarity using a simplified reverse source/drain planarization mask. Embodiments include forming large trenches and refilling them with an insulating material which also covers the substrate surface, masking the areas above the large trenches, etching to remove substantially all of the insulating material on the substrate surface and polishing to planarize the insulating material above the large trenches. Small trenches and peripheral trenches surrounding the large trenches are then formed, refilled with insulating material, and planarized. Since the large trenches are formed prior to and separately from the small trenches, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. The use of a planarization mask with relatively few features having a relatively large geometry avoids the need to create and implement a complex and critical mask, thereby reducing manufacturing costs and increasing production throughput. Furthermore, because the large and small trenches are not polished at the same time, overpolishing is avoided, thereby improving planarity and, hence, the accuracy of subsequent photolithographic processing.
摘要翻译：使用简化的反向源极/漏极平面化掩模，在具有改善的平面度的半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。实施例包括形成大沟槽并用也覆盖衬底表面的绝缘材料再填充它们，掩蔽大沟槽上方的区域，蚀刻以基本上除去衬底表面上的所有绝缘材料，并抛光以平坦化绝缘材料沟渠然后形成围绕大沟槽的小沟槽和外围沟槽，用绝缘材料重新填充并平坦化。由于在小沟槽之前和分开形成大沟槽，所以可以在仅在大沟槽上而不是小沟槽形成相对简单的平坦化掩模之后进行蚀刻。使用具有相对较大几何特征的平面化掩模的使用避免了创建和实现复杂和关键掩模的需要，从而降低制造成本并提高生产量。此外，因为大的和小的沟槽不同时被抛光，所以避免了过度抛光，从而提高平面度，从而提高随后的光刻处理的精度。

3. 发明授权

US6124183A Shallow trench isolation formation with simplified reverse planarization mask 失效
标题翻译：浅沟槽隔离形成，具有简化的反向平面化掩模
公开(公告)号：US6124183A
公开(公告)日：2000-09-26
申请号：US992490
申请日：1997-12-18
申请人： Olov Karlsson , Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Larry Wang , Effiong Ibok
发明人： Olov Karlsson , Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Larry Wang , Effiong Ibok
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate using a simplified reverse source/drain planarization mask. Embodiments include forming trenches and refilling them with an insulating material which also covers a main surface of the substrate, polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches, furnace annealing to densify and strengthen the remaining insulating material, masking the insulating material above the large trenches, isotropically etching the insulating material, and polishing to planarize the insulating material. Since the insulating material is partially planarized and strengthened prior to etching, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. Because the features of the planarization mask are relatively few and have a relatively large geometry, the present invention avoids the need to create and implement a critical mask, enabling production costs to be reduced and manufacturing throughput to be increased.
摘要翻译：使用简化的反向源极/漏极平面化掩模在半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。实施例包括形成沟槽并用绝缘材料再填充它们，该绝缘材料也覆盖衬底的主表面，抛光以除去绝缘材料的上部并平面化小沟槽上方的绝缘材料，炉退火致密化并加强其余部分绝缘材料，掩蔽大沟槽上方的绝缘材料，各向同性地蚀刻绝缘材料，并抛光以使绝缘材料平坦化。由于在蚀刻之前绝缘材料被部分平坦化和加强，因此可以在仅在大的沟槽上而不是小沟槽形成相对简单的平坦化掩模之后进行蚀刻。由于平面化掩模的特征相对较少并且具有相对较大的几何形状，因此本发明避免了创建和实施关键掩模的需要，从而能够降低生产成本并提高生产量。

4. 发明授权

US06599810B1 Shallow trench isolation formation with ion implantation 有权
标题翻译：浅沟隔离形成与离子注入
公开(公告)号：US06599810B1
公开(公告)日：2003-07-29
申请号：US09186078
申请日：1998-11-05
申请人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
发明人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L2176
CPC分类号： H01L21/76237 , H01L21/26586 , H01L21/76235
摘要： An insulated trench isolation structure is formed by ion implanting impurities proximate to the trench edges for enhancing the oxidation rate and, hence, increasing the thickness of the oxide at the trench edges. Embodiments include ion implanting impurities prior to growing an oxide liner. The resulting thick oxide on the trench edges avoids overlap of a subsequently deposited polysilicon layer and breakdown problems attendant upon a thinned gate oxide at the trench edges.
摘要翻译：通过离子注入靠近沟槽边缘的杂质形成绝缘沟槽隔离结构，以增强氧化速率，并因此增加沟槽边缘处氧化物的厚度。实施例包括在生长氧化物衬垫之前的离子注入杂质。沟槽边缘上产生的厚氧化物避免随后沉积的多晶硅层的重叠以及伴随沟槽边缘处的薄化栅极氧化物的破坏问题。

5. 发明授权

US6143624A Shallow trench isolation formation with spacer-assisted ion implantation 有权
标题翻译：浅沟槽隔离形成与间隔子辅助离子注入
公开(公告)号：US6143624A
公开(公告)日：2000-11-07
申请号：US172088
申请日：1998-10-14
申请人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
发明人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L21/762
CPC分类号： H01L21/76235 , H01L21/76237 , Y10S438/966 , Y10S438/981
摘要： An insulated trench isolation structure is formed by ion implanting impurities proximate the trench edges to enhance the silicon oxidation rate and, hence, increase the thickness of the resulting oxide at the trench edges. Embodiments include masking and etching a barrier nitride layer, forming protective spacers on portions of the substrate corresponding to subsequently formed trench edges, etching the trench, removing the protective spacers, ion implanting impurities into those portions of the substrate previously covered by the protective spacers, and then growing an oxide liner. The resulting oxide formed on the trench edges is thick due to the enhanced silicon oxidation rate, thereby avoiding overlap of a subsequently deposited polysilicon layer and breakdown problems attendant upon a thinned gate oxide at the trench edges.
摘要翻译：通过离子注入靠近沟槽边缘的杂质形成绝缘沟槽隔离结构，以增强硅的氧化速率，并因此增加在沟槽边缘处产生的氧化物的厚度。实施例包括掩蔽和蚀刻阻挡氮化物层，在对应于随后形成的沟槽边缘的衬底的部分上形成保护性间隔物，蚀刻沟槽，去除保护性间隔物，将先前被保护隔离层覆盖的衬底的离子注入杂质，然后生长氧化物衬垫。形成在沟槽边缘上的所得氧化物由于硅氧化速率的增强而变厚，从而避免随后沉积的多晶硅层的重叠以及伴随沟槽边缘处的薄化栅极氧化物的破坏问题。

6. 发明授权

US6037671A Stepper alignment mark structure for maintaining alignment integrity 有权
标题翻译：用于保持对准完整性的步进对准标记结构
公开(公告)号：US6037671A
公开(公告)日：2000-03-14
申请号：US184861
申请日：1998-11-03
申请人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
发明人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
IPC分类号： G03F9/00 , H01L23/544
CPC分类号： G03F9/7076 , G03F9/70 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/975
摘要： Accurate photolighographic processing is achieved employing a stepper global alignment structure enabling formation thereon of a substantially transparent layer having a substantially planar upper surface. Embodiments include a set of global alignment marks comprising spaced apart trenches, each trench segmented into a plurality of narrow trenches spaced apart by uprights and forming a dummy topographical area of narrow trenches surrounding the set of alignment marks. The segmented trenches and the dummy topographical area effectively provide a substantially uniform topography enabling deposition of a transparent layer without steps and effective local planarization. Since the upper surface of the transparent layer is substantially planar, layers of material deposited on the transparent layer during subsequent processing also have a substantially planar upper surface, thereby enabling transmission of the signal produced by the alignment marks to the stepper with minimal distortion.
摘要翻译：使用步进全局对准结构可实现准确的视差处理，该结构能够在其上形成具有基本平坦的上表面的基本上透明的层。实施例包括一组包括间隔开的沟槽的全局对准标记，每个沟槽被分段成由立柱间隔开的多个窄沟槽，并形成围绕该组对准标记的窄沟槽的虚拟地形区域。分段沟槽和虚拟地形区域有效地提供基本均匀的形貌，使得能够沉积透明层而无需步骤和有效的局部平面化。由于透明层的上表面基本上是平面的，因此在随后的处理期间沉积在透明层上的材料层也具有基本平坦的上表面，从而能够以最小的变形将由对准标记产生的信号传输到步进机。

7. 发明授权

US5970363A Shallow trench isolation formation with improved trench edge oxide 失效
标题翻译：浅沟槽隔离形成，具有改善的沟槽边缘氧化物
公开(公告)号：US5970363A
公开(公告)日：1999-10-19
申请号：US993827
申请日：1997-12-18
申请人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
发明人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L21/762 , H01L21/8242
CPC分类号： H01L21/76232
摘要： A shallow trench isolation structure is formed which enables the growth of a high quality gate oxide at the trench edges. Embodiments include forming a photoresist mask directly on a pad oxide layer which, in turn, is formed on a main surface of a semiconductor substrate or an epitaxial layer on a semiconductor substrate. After masking, the substrate is etched to form a trench, an oxide liner is grown in the trench surface, and a polish stop layer is deposited over the oxide liner and the pad oxide layer. The polish stop layer is then masked to the trench edges, and the polish stop in the trench etched away. The trench is then filled with an insulating material, the insulating material is planarized, and the polish stop is removed by etching. Thus, the oxide liner is allowed to grow on the trench edges without the restraint of a polish stop, resulting in a thick, rounded oxide on the trench edges. Additionally, no polish stop layer remains in the trench to cause unwanted electrical effects.
摘要翻译：形成浅沟槽隔离结构，其能够在沟槽边缘处生长高质量的栅极氧化物。实施例包括直接在衬垫氧化物层上形成光致抗蚀剂掩模，衬垫氧化物层又形成在半导体衬底的主表面或半导体衬底上的外延层上。在掩模之后，蚀刻衬底以形成沟槽，在沟槽表面生长氧化物衬垫，并且抛光停止层沉积在氧化物衬垫和衬垫氧化物层上。然后抛光停止层被掩蔽到沟槽边缘，并且沟槽中的抛光停止被蚀刻掉。然后用绝缘材料填充沟槽，将绝缘材料平坦化，并通过蚀刻去除抛光止动件。因此，允许氧化物衬垫在沟槽边缘上生长而不受抛光停止的限制，导致沟槽边缘上的厚的圆形氧化物。此外，沟槽中不留下抛光停止层，引起不必要的电气效应。

8. 发明授权

US5970362A Simplified shallow trench isolation formation with no polish stop 失效
标题翻译：简化浅沟隔离结构，无抛光停止
公开(公告)号：US5970362A
公开(公告)日：1999-10-19
申请号：US992488
申请日：1997-12-18
申请人： Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Ibok
发明人： Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Ibok
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232
摘要： An insulated trench isolation structure is formed in a semiconductor substrate omitting a barrier nitride polish stop layer, thereby simplifying the formation of the trench isolating structure, and enabling the substrate to be polished substantially flush with the trench fill. The planar trench fill-substrate interface avoids additional topography, thereby facilitating application of, and enhancing the accuracy of, photolithographic techniques in forming features with minimal dimensions.
摘要翻译：在省略了阻挡氮化物抛光停止层的半导体衬底中形成绝缘沟槽隔离结构，从而简化了沟槽隔离结构的形成，并使衬底能够与沟槽填充基本齐平。平面沟槽填充 - 衬底接口避免了额外的形貌，从而有助于光刻技术在最小尺寸形成特征时的应用和提高光刻技术的准确性。

9. 发明授权

US06074927A Shallow trench isolation formation with trench wall spacer 失效
标题翻译：浅沟槽隔离形成与沟槽壁间隔
公开(公告)号：US06074927A
公开(公告)日：2000-06-13
申请号：US87662
申请日：1998-06-01
申请人： Nick Kepler , Basab Bandyopadhyay , Olov Karlsson , Larry Wang , Effiong Ibok , Christopher F. Lyons
发明人： Nick Kepler , Basab Bandyopadhyay , Olov Karlsson , Larry Wang , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232
摘要： A shallow trench isolation structure is formed which enables the growth of a high quality gate oxide at the trench edges and protects the field oxide from gouging during post-gate processing, such as during the local interconnect etch, thereby allowing the formation of high-quality implanted junctions. Embodiments include forming a photoresist mask directly on a pad oxide layer which, in turn, is formed on a main surface of a semiconductor substrate or an epitaxial layer on a semiconductor substrate. After masking, the substrate is etched to form a trench, an oxide liner is grown in the trench surface, and a polish stop layer is deposited in the trench on the oxide liner and on the pad oxide layer. The polish stop layer is then masked to the trench edges, and the polish stop in the trench is anisotropically etched, to remove the polish stop at the bottom of the trenches leaving a portion overlying the side surfaces and edges of the trench on the oxide liner. The trench is then filled with an insulating material, the insulating material is planarized, and the polish stop over the pad oxide layer is removed by anisotropic etching. Thus, the oxide liner is allowed to grow on the trench edges without the restraint of a polish stop, resulting in a thick, rounded oxide on the trench edges. The portion of the polish stop remaining in the trench and on the oxide liner at the trench edges serves as a protective spacer, protecting the field oxide from erosion during subsequent processing steps.
摘要翻译：形成浅沟槽隔离结构，其使得能够在沟槽边缘处生长高质量的栅极氧化物，并且保护场氧化物在后栅极处理（例如在局部互连蚀刻期间）中的气蚀，从而允许形成高质量植入路口。实施例包括直接在衬垫氧化物层上形成光致抗蚀剂掩模，衬垫氧化物层又形成在半导体衬底的主表面或半导体衬底上的外延层上。在掩模之后，蚀刻衬底以形成沟槽，在沟槽表面中生长氧化物衬垫，并且抛光停止层沉积在氧化物衬垫和衬垫氧化物层上的沟槽中。然后将抛光停止层掩蔽到沟槽边缘，并且沟槽中的抛光停止点被各向异性地蚀刻，以去除沟槽底部的抛光停止部，留下覆盖氧化物衬垫上的沟槽的侧表面和边缘的部分。然后用绝缘材料填充沟槽，使绝缘材料平坦化，并通过各向异性蚀刻去除衬垫氧化物层上的抛光剂停止。因此，允许氧化物衬垫在沟槽边缘上生长而不受抛光停止的限制，导致沟槽边缘上的厚的圆形氧化物。保留在沟槽中的抛光停止部分和在沟槽边缘处的氧化物衬垫上的部分用作保护间隔物，在随后的处理步骤期间保护场氧化物免受侵蚀。

10. 发明授权

US06171962B2 Shallow trench isolation formation without planarization mask 失效
标题翻译：浅沟槽隔离形成无平面化掩模
公开(公告)号：US06171962B2
公开(公告)日：2001-01-09
申请号：US08993889
申请日：1997-12-18
申请人： Olov Karlsson , Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Larry Wang , Effiong Ibok
发明人： Olov Karlsson , Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Larry Wang , Effiong Ibok
IPC分类号： H01L21302
CPC分类号： H01L21/76229 , H01L21/31053
摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate without a planarization mask or etch. Embodiments include forming trenches and refilling them with an insulating material which also covers the substrate surface, followed by polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches. A second layer of insulating material is then deposited to fill seams in the insulating material above the small trenches and to fill steps in the insulating material above the large trenches. The insulating material is then planarized. Since the insulating material is partially planarized by the first polish and the seams and steps are filled by the second deposition, the resulting topography of the upper surface of the second layer of insulating material is small enough to enable a direct final polish without the need to create and implement a planarization mask and to perform an etch and mask removal, thereby reducing manufacturing costs and increasing production throughput.
摘要翻译：在半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构，而不需要平坦化掩模或蚀刻。实施例包括用绝缘材料形成沟槽并再填充它们，该绝缘材料也覆盖衬底表面，接着进行抛光以除去绝缘材料的上部并使小沟槽上方的绝缘材料平坦化。然后沉积第二层绝缘材料以填充小沟槽上方的绝缘材料中的接缝，并填充大沟槽上方的绝缘材料的步骤。然后将绝缘材料平坦化。由于绝缘材料被第一抛光部分地平坦化并且接缝和步骤通过第二次沉积来填充，所以第二层绝缘材料的上表面的所得形貌足够小以使得能够进行直接的最终抛光，而不需要创建并实现平面化掩模并执行蚀刻和掩模去除，从而降低制造成本并提高生产量。

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