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1. 发明授权

US06764920B1 Method for reducing shallow trench isolation edge thinning on tunnel oxides using partial nitride strip and small bird's beak formation for high performance flash memory devices 有权
标题翻译：用于使用偏氮化物带和用于高性能闪存器件的小鸟嘴形成来减少隧道氧化物上的浅沟槽隔离边缘薄化的方法
公开(公告)号：US06764920B1
公开(公告)日：2004-07-20
申请号：US10126840
申请日：2002-04-19
申请人： Nian Yang , John Jianshi Wang , Unsoon Kim
发明人： Nian Yang , John Jianshi Wang , Unsoon Kim
IPC分类号： H01L2176
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/76224 , H01L21/823481 , H01L29/66825
摘要： A method of semiconductor integrated circuit fabrication. Specifically, one embodiment of the present invention discloses a method for reducing shallow trench isolation (STI) corner recess of silicon in order to reduce STI edge thinning on tunnel oxides (510) for flash memories (devices M and N). An STI process is implemented to isolate flash memory devices (devices M and N) in the semiconductor structure (200). In the STI process, a nitride layer (210) is deposited over a silicon substrate (280). An STI region (290) is formed defining STI corners (240) where a top surface (270) of the silicon substrate (280) and the STI region (290) converge. The STI region (290) is filled with an STI field oxide and planarized until reaching the nitride layer (210). A local oxidation of silicon (LOCOS) is then performed to oxidize the top surface (270) of the silicon substrate adjacent to the STI corners (240). Oxidized silicon is grown to boost the thickness of a later formed tunnel oxide layer (510) at the STI corners (240).
摘要翻译：一种半导体集成电路制造方法。具体地，本发明的一个实施例公开了一种用于减少硅的浅沟槽隔离（STI）角凹槽的方法，以便减少闪存（器件M和N）的隧道氧化物（510）上的STI边缘变薄。实施STI处理以隔离半导体结构（200）中的闪存器件（器件M和N）。在STI工艺中，氮化物层（210）沉积在硅衬底（280）上。形成STI区域（290），其限定了硅基板（280）的顶表面（270）和STI区域（290）会聚的STI拐角（240）。 STI区域（290）填充有STI场氧化物并且被平坦化直到到达氮化物层（210）。然后进行硅的局部氧化（LOCOS）以氧化邻近STI拐角（240）的硅衬底的顶表面（270）。生长氧化硅以增强在STI拐角（240）处的稍后形成的隧道氧化物层（510）的厚度。

2. 发明授权

US06924220B1 Self-aligned gate formation using polysilicon polish with peripheral protective layer 失效
标题翻译：使用多晶硅抛光与外围保护层的自对准栅极形成
公开(公告)号：US06924220B1
公开(公告)日：2005-08-02
申请号：US09922536
申请日：2001-08-03
申请人： Kai Yang , John Jianshi Wang , Unsoon Kim
发明人： Kai Yang , John Jianshi Wang , Unsoon Kim
IPC分类号： H01L21/321 , H01L21/8247 , H01L27/105 , H01L21/3201
CPC分类号： H01L27/11526 , H01L21/3212 , H01L27/105 , H01L27/11531
摘要： A method of protecting a peripheral region, by forming a protective mask over the peripheral area, during polysilicon polishing while forming self-aligned polysilicon gates in flash memory circuits. In one aspect, the protective mask is formed over a substantial area of the Peripheral region. In another aspect, the protective mask is formed over a substantial area of an active part of the peripheral region.
摘要翻译：一种通过在多晶硅抛光期间在周边区域上形成保护掩模来保护外围区域的方法，同时在闪速存储器电路中形成自对准的多晶硅栅极。在一个方面，保护掩模形成在外围区域的大部分区域上。另一方面，保护掩模形成在周边区域的有效部分的实质区域上。

3. 发明授权

US08802537B1 System and method for improving reliability in a semiconductor device 有权
标题翻译：用于提高半导体器件的可靠性的系统和方法
公开(公告)号：US08802537B1
公开(公告)日：2014-08-12
申请号：US11189874
申请日：2005-07-27
申请人： Yider Wu , Unsoon Kim , Kuo-Tung Chang , Harpreet Sachar
发明人： Yider Wu , Unsoon Kim , Kuo-Tung Chang , Harpreet Sachar
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/02057
摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The memory device is pre-cleaned to prepare a surface of the memory device for oxide formation thereon, where cleaning the memory device removes portions of the barrier oxide layer on opposite sides of the trench. The nitride layer is trimmed on opposite sides of the trench. A liner oxide layer is formed in the trench.
摘要翻译：提供了一种用于形成存储器件的方法。在衬底上形成氮化物层。蚀刻氮化物层和衬底以形成沟槽。存储器件被预先清洁以准备用于其上形成氧化物的存储器件的表面，其中清洁存储器件去除沟槽相对侧上的阻挡氧化物层的部分。在沟槽的相对侧上修整氮化物层。在沟槽中形成衬里氧化物层。

4. 发明授权

US08742486B2 Flash memory cells having trenched storage elements 有权
标题翻译：具有沟槽存储元件的闪存单元
公开(公告)号：US08742486B2
公开(公告)日：2014-06-03
申请号：US11702846
申请日：2007-02-05
申请人： Wei Zheng , Chi Chang , Unsoon Kim
发明人： Wei Zheng , Chi Chang , Unsoon Kim
IPC分类号： H01L29/68
CPC分类号： H01L29/792 , H01L21/823418 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/7923
摘要： An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the second sidewall of the second trench.
摘要翻译：本发明的实施例涉及存储单元。存储单元包括形成在半导体衬底中的第一沟槽和形成在与所述第一沟槽相邻的所述半导体衬底中的第二沟槽。第一沟槽和第二沟槽分别限定第一侧壁和第二侧壁。存储单元还包括形成在第一沟槽的第一侧壁上的第一存储元件和形成在第二沟槽的第二侧壁上的第二存储元件。

5. 发明授权

US07307002B2 Non-critical complementary masking method for poly-1 definition in flash memory device fabrication 有权
标题翻译：闪存器件制造中poly-1定义的非关键互补掩模方法
公开(公告)号：US07307002B2
公开(公告)日：2007-12-11
申请号：US11099339
申请日：2005-04-04
申请人： Unsoon Kim , Hiroyuki Kinoshita , Yu Sun , Krishnashree Achuthan , Christopher H. Raeder , Christopher M. Foster , Harpreet Kaur Sachar , Kashmir Singh Sahota
发明人： Unsoon Kim , Hiroyuki Kinoshita , Yu Sun , Krishnashree Achuthan , Christopher H. Raeder , Christopher M. Foster , Harpreet Kaur Sachar , Kashmir Singh Sahota
IPC分类号： H01L21/76
CPC分类号： H01L27/105 , H01L21/3212 , H01L21/32139 , H01L21/76229 , H01L27/1052 , H01L27/11526 , H01L27/11543 , H01L27/11568
摘要： A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.
摘要翻译：公开了一种用于在半导体晶片中定义多晶硅层的方法。使用非临界掩模在聚-1沉积之前将外围的场氧化物凹入等于最终聚-1厚度的量。使用互补的非关键掩模来允许芯的CMP将浅层隔离沟的核心氧化物台面的顶部暴露出来。

6. 发明授权

US06444530B1 Process for fabricating an integrated circuit with a self-aligned contact 有权
标题翻译：用于制造具有自对准接触的集成电路的工艺
公开(公告)号：US06444530B1
公开(公告)日：2002-09-03
申请号：US09318429
申请日：1999-05-25
申请人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
发明人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/76897 , H01L23/485 , H01L27/115 , H01L2924/0002 , Y10T428/12542 , Y10T428/1259 , Y10T428/12625 , Y10T428/12778 , H01L2924/00
摘要： A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.
摘要翻译：在闪速存储器件中形成触点的方法利用局部互连处理技术。局部互连处理技术允许接触件与存储器单元相关联的堆叠栅极对接或重叠。接触可以包括钨。堆叠的栅极被也覆盖绝缘间隔物的阻挡层覆盖。

7. 发明授权

US06433383B1 Methods and arrangements for forming a single interpoly dielectric layer in a semiconductor device 有权
标题翻译：在半导体器件中形成单个互间电介质层的方法和布置
公开(公告)号：US06433383B1
公开(公告)日：2002-08-13
申请号：US09357333
申请日：1999-07-20
申请人： Mark Ramsbey , Unsoon Kim , Kenneth Wo-Wai Au , David H. Chi , James Markarian
发明人： Mark Ramsbey , Unsoon Kim , Kenneth Wo-Wai Au , David H. Chi , James Markarian
IPC分类号： H01L27108
CPC分类号： H01L27/11521 , H01L21/3144 , H01L21/3145 , H01L27/115 , H01L29/511
摘要： A single interpoly dielectric layer is provided for use in semiconductor devices. The single interpoly dielectric layer being formed of silicon graded such that certain regions within the single interpoly dielectric layer are either oxygen-rich or nitrogen-rich. The single interpoly dielectric layer can be formed in-situ within a single deposition tool. In certain embodiments, the resulting single interpoly dielectric layer can be made thinner and/or can be formed to provide improved dielectric characteristics when compared to a conventional oxide-nitride-oxide (ONO) interpoly dielectric layer that has three separate and unique layers. Thus, the single interpoly dielectric layer is highly desirable for use in reduced-size semiconductor devices and/or semiconductor devices requiring improved data retention capabilities, such as non-volatile memory cells.
摘要翻译：提供了一个用于半导体器件的单互补电介质层。由硅分级形成的单个间隔电介质层使得单个互间介电层内的某些区域是富氧或富含氮的。单个间隔电介质层可以在单个沉积工具内原位形成。在某些实施例中，当与具有三个独立且独特的层的常规氧化物 - 氮化物 - 氧化物（ONO）间隔电介质层相比时，所得到的单个间隔电介质层可以制成更薄和/或可形成以提供改善的介电特性。因此，对于需要改进的数据保持能力的尺寸较小的半导体器件和/或半导体器件（例如非易失性存储器单元），单个互聚电介质层是非常需要的。

8. 发明授权

US5907781A Process for fabricating an integrated circuit with a self-aligned contact 失效
公开(公告)号：US5907781A
公开(公告)日：1999-05-25
申请号：US49517
申请日：1998-03-27
申请人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
发明人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L21/335
CPC分类号： H01L21/76897 , H01L21/76895
摘要： A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

9. 发明授权

US08759894B1 System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device 有权
标题翻译：用于减少半导体器件中的电荷存储元件之间的交叉耦合噪声的系统和方法
公开(公告)号：US08759894B1
公开(公告)日：2014-06-24
申请号：US11189765
申请日：2005-07-27
申请人： Yider Wu , Hiroyuki Ogawa , Unsoon Kim , Angela T. Hui
发明人： Yider Wu , Hiroyuki Ogawa , Unsoon Kim , Angela T. Hui
IPC分类号： H01L29/78
CPC分类号： H01L27/11524 , H01L21/28273 , H01L29/66825 , H01L29/66833
摘要： A memory device is provided including a substrate. A first dielectric layer is formed over the substrate. An isolation trench is formed in a portion of the substrate and the first dielectric layer. At least two charge storage elements are formed over the first dielectric layer on opposite sides of the isolation trench. A second dielectric layer is formed over the at least two charge storage elements. A control gate layer is formed over the second dielectric layer, where the isolation trench has a width suitable for reducing cross-coupling noise of charge storage elements, and where the at least two charge storage elements have a height suitable for providing sufficient gate coupling between the at least two charge storage elements and the control gate layer.
摘要翻译：提供了包括基板的存储器件。第一电介质层形成在衬底上。在衬底和第一介电层的一部分中形成隔离沟槽。在隔离沟槽的相对侧上的第一介电层上形成至少两个电荷存储元件。在所述至少两个电荷存储元件上形成第二电介质层。控制栅极层形成在第二介电层上，其中隔离沟槽具有适于减小电荷存储元件的交叉耦合噪声的宽度，并且其中至少两个电荷存储元件具有适于提供足够的栅极耦合的高度所述至少两个电荷存储元件和所述控制栅极层。

10. 发明授权

US07785965B2 Dual storage node memory devices and methods for fabricating the same 有权
标题翻译：双存储节点存储器件及其制造方法
公开(公告)号：US07785965B2
公开(公告)日：2010-08-31
申请号：US11530145
申请日：2006-09-08
申请人： Unsoon Kim , Kyunghoon Min , Ning Cheng , Hiroyuki Kinoshita , Sugino Rinji , Timothy Thurgate , Angela Hui , Jihwan Choi , Chi Chang
发明人： Unsoon Kim , Kyunghoon Min , Ning Cheng , Hiroyuki Kinoshita , Sugino Rinji , Timothy Thurgate , Angela Hui , Jihwan Choi , Chi Chang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/42352 , H01L29/7923
摘要： Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.
摘要翻译：已经提供了双存储节点存储器件和用于制造双存储节点存储器件的方法。根据示例性实施例，一种方法包括以下步骤：蚀刻半导体衬底中的多个沟槽并在沟槽内形成分层结构。层状结构包括隧道介电层和电荷存储层。位线形成在半导体衬底内，并且一层导电材料沉积在层叠结构之上。

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