专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06229347B1 Circuit for evaluating an asysmetric antenna effect 有权
标题翻译：评估非对称天线效应的电路
公开(公告)号：US06229347B1
公开(公告)日：2001-05-08
申请号：US09228366
申请日：1999-01-11
申请人： Mu-Chun Wang , Chau-Neng Wu , Shiang Huang-Lu
发明人： Mu-Chun Wang , Chau-Neng Wu , Shiang Huang-Lu
IPC分类号： H03K522
CPC分类号： H03F3/45183 , H03F2203/45674 , H03K5/2418 , H03K5/2481
摘要： A circuit for evaluating the asymmetric antenna effect of a transistor pair is provided, which can be implemented by using bipolar or complementary metal oxide semiconductor (CMOS) transistors to implement a differential amplifier, with which a pair of transistors Q1 and Q2 having similar characteristics are connected. The transistors Q1 and Q2 have a structure of, for example, one polysilicon layer and three metal layers, in which a second metal layer M2 and a third metal layer M3 are used for signal input, and metal layer M1 close to the gate oxide layer of both the transistors Q1 and Q2 are used to obtain a differential antenna ratio. The differential amplifier comprises transistors Q3 and Q4 serving as an active load, and transistor Q5, which is used for adjusting the voltage gain.
摘要翻译：提供了一种用于评估晶体管对的不对称天线效应的电路，其可以通过使用双极或互补金属氧化物半导体（CMOS）晶体管来实现差分放大器来实现，其中具有相似特性的一对晶体管Q1和Q2具有连接的。晶体管Q1和Q2具有例如一个多晶硅层和三个金属层的结构，其中第二金属层M2和第三金属层M3用于信号输入，并且金属层M1靠近栅极氧化物层使用晶体管Q1和Q2两者来获得差分天线比。差分放大器包括用作有源负载的晶体管Q3和Q4以及用于调整电压增益的晶体管Q5。

2. 发明授权

US06483045B1 Via plug layout structure for connecting different metallic layers 失效
标题翻译：通过插头布局结构连接不同的金属层
公开(公告)号：US06483045B1
公开(公告)日：2002-11-19
申请号：US09626409
申请日：2000-07-26
申请人： Mu-Chun Wang , Shih-Chieh Kao , Shiang Huang-Lu , Yuan-Chang Liu
发明人： Mu-Chun Wang , Shih-Chieh Kao , Shiang Huang-Lu , Yuan-Chang Liu
IPC分类号： H05K111
CPC分类号： H01L23/528 , H01L23/5226 , H01L2924/0002 , H05K1/115 , H05K2201/0769 , H05K2201/0969 , H05K2201/0979 , H01L2924/00
摘要： A via plug layout structure for connecting different metallic layers. The structure includes a plurality of via plugs arranged in a fan-shaped pattern and a plurality of empty bars positioned between a single via plug and the fanned-out via plugs so that incoming current to the single via plug is equally distributed to every one of the fanned-out via plug and current stress in each fanned-out via plug is identical. Hence, via plugs having particularly serious electromigration problem can be discovered. In addition, single via plug having different critical dimension can be fabricated so that maximum critical dimension sustainable by the via plug is determined after an electromigration test.
摘要翻译：用于连接不同金属层的通孔插头布局结构。该结构包括布置成扇形图案的多个通孔塞和位于单个通孔插头和扇形通孔之间的多个空杆，使得到单个通孔塞的进入电流被均等地分配到通过插头的每个扇形插头中的插头和电流应力都是相同的。因此，可以发现通过具有特别严重的电迁移问题的插头。此外，可以制造具有不同临界尺寸的单通孔塞，使得在电迁移测试之后确定由通孔插塞可持续的最大临界尺寸。

3. 发明授权

US06291285B1 Method for protecting gate oxide layer and monitoring damage 有权
标题翻译：保护栅极氧化层和监测损伤的方法
公开(公告)号：US06291285B1
公开(公告)日：2001-09-18
申请号：US09215884
申请日：1998-12-16
申请人： Mu-Chun Wang , Shiang Huang-Lu
发明人： Mu-Chun Wang , Shiang Huang-Lu
IPC分类号： H01L218234
CPC分类号： H01L21/28123 , H01L23/552 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： A method for protecting the gate oxide layer of a MOS device. The method can also be used to monitor the intensity of radiation and charged particles falling on the gate oxide layer. The method includes the provision of a substrate having a gate structure thereon and an inter-layer dielectric layer over the gate structure, wherein the gate structure further includes a gate oxide layer and a gate electrode. Thereafter, a shielding layer is formed over the inter-layer dielectric layer, and then a protection diode is formed to link the shielding to the substrate.
摘要翻译：一种用于保护MOS器件的栅极氧化物层的方法。该方法还可用于监测落在栅极氧化物层上的辐射强度和带电粒子的强度。该方法包括提供其上具有栅极结构的衬底和栅极结构上的层间电介质层，其中栅极结构还包括栅极氧化物层和栅电极。此后，在层间电介质层上形成屏蔽层，然后形成保护二极管以将屏蔽连接到基板。

4. 发明授权

US06245610B1 Method of protecting a well at a floating stage 失效
标题翻译：在浮动阶段保护井的方法
公开(公告)号：US06245610B1
公开(公告)日：2001-06-12
申请号：US09406517
申请日：1999-09-28
申请人： Mu-Chun Wang , Tzung-Han Lee , Shiang Huang-Lu
发明人： Mu-Chun Wang , Tzung-Han Lee , Shiang Huang-Lu
IPC分类号： H01L218234
CPC分类号： H01L21/823475 , H01L21/76892 , H01L21/8234 , H01L21/823493
摘要： A method of protecting a well at a floating stage. In a first conductive type substrate, a second conductive type well is formed. A first conductive type heavily doped region and a second conductive type heavily doped region are respectively formed in the first conductive type substrate and the second conductive type well. These two heavily doped regions are electrically connected with each at an early stage of fabrication process to provide a protection from being damaged during subsequent plasma process or other processes. While forming a top metal layer of a multi-level interconnect, these two heavily doped regions are disconnected, that is, open to each other, to obtain a better electrical characteristic of the device or the integrated circuit formed on the substrate.
摘要翻译：在浮动阶段保护井的方法。在第一导电型衬底中，形成第二导电型阱。第一导电型重掺杂区和第二导电型重掺杂区分别形成在第一导电类型衬底和第二导电类型阱中。这两个重掺杂区域在制造工艺的早期阶段与每一个电连接以提供保护以防止在随后的等离子体处理或其它工艺期间损坏。当形成多层互连的顶层金属层时，这两个重掺杂区域被断开，即彼此开放，以获得器件或形成在衬底上的集成电路的更好的电特性。

5. 发明授权

US06191602B1 Wafer acceptance testing method and structure of a test key used in the method 有权
标题翻译：晶圆验收测试方法和方法中使用的测试键的结构
公开(公告)号：US06191602B1
公开(公告)日：2001-02-20
申请号：US09220097
申请日：1998-12-23
申请人： Shiang Huang-Lu , Mu-Chun Wang , Kun-Cho Chen
发明人： Shiang Huang-Lu , Mu-Chun Wang , Kun-Cho Chen
IPC分类号： G01R3126
CPC分类号： H01L22/34
摘要： A wafer acceptance testing (WAT) method with a test key is provided. The test key structure includes a testing structure on a substrate. An inter-layer-dielectric layer covers over the substrate to isolate the testing structure. A grounded metal layer is located on the inter-layer dielectric layer. An interconnecting structure is located on the grounded metal layer. A conductive pad layer and a passivation layer are sequentially located on the interconnecting structure. The testing structure is electrically coupled to the interconnecting structure. The interconnecting structure is also electrically coupled to the conductive pad layer. The grounded metal layer is grounded without any further coupling such that the grounded metal layer is not coupled to the testing structure and the interconnecting structure.
摘要翻译：提供了具有测试键的晶片验收测试（WAT）方法。测试键结构包括在衬底上的测试结构。层间电介质层覆盖在衬底上以隔离测试结构。接地的金属层位于层间电介质层上。互连结构位于接地的金属层上。导电焊盘层和钝化层依次位于互连结构上。测试结构电耦合到互连结构。互连结构也电耦合到导电焊盘层。接地的金属层没有任何进一步的耦合而接地，使得接地的金属层不耦合到测试结构和互连结构。

6. 发明授权

US06873505B2 Electrostatic discharge protective circuitry equipped with a common discharge line 有权
标题翻译：静电放电保护电路配有普通放电线
公开(公告)号：US06873505B2
公开(公告)日：2005-03-29
申请号：US09912288
申请日：2001-07-24
申请人： Shiao-Shien Chen , Tien-Hao Tang , Mu-Chun Wang
发明人： Shiao-Shien Chen , Tien-Hao Tang , Mu-Chun Wang
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0262 , H01L27/0255
摘要： A semiconductor device having an electrostatic discharge protective circuitry adapted to a common discharge line (CDL) is disclosed. In the embodiments of the present invention, semiconductor device includes a plurality of bonding pads, each having at least one connecting terminal, a common discharge line, and a protective device connected between the connecting terminal and the common discharge line. Moreover, the protective device is composed of a silicon-control-rectifier that is used for electrostatic discharge protection and a zener diode for lowering a trigger voltage of the silicon-control-rectifier.
摘要翻译：公开了具有适用于公共放电线（CDL）的静电放电保护电路的半导体器件。在本发明的实施例中，半导体器件包括多个接合焊盘，每个焊盘具有至少一个连接端子，公共放电线以及连接在连接端子和公共放电线路之间的保护器件。此外，保护装置由用于静电放电保护的硅控整流器和用于降低硅控整流器的触发电压的齐纳二极管组成。

7. 发明授权

US06051986A Method of testing a transistor 失效
标题翻译：测试晶体管的方法
公开(公告)号：US06051986A
公开(公告)日：2000-04-18
申请号：US999236
申请日：1997-12-29
申请人： Mu-Chun Wang
发明人： Mu-Chun Wang
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： A method of testing for a kink effect typically occurring during the fabrication of shallow trench isolation of a transistor in an integrated circuit. A curve of source/drain current versus gate voltage is plotted. A second order differential of the curve is performed and plotted, and the existence of a kink effect is determined by the number of the local maxima and local minima. The degree of kink effect as low as and below a 0.25 .mu.m level is determined according to the level of a global minimum value.
摘要翻译：在集成电路中的晶体管的浅沟槽隔离的制造期间通常发生的扭结效应的测试方法。绘制源极/漏极电流与栅极电压的曲线。执行曲线的二阶微分，并绘制扭结效应的存在由局部最大值和局部最小值的数量确定。根据全局最小值的水平确定低于或低于0.25μm水平的扭结效应的程度。

8. 发明授权

US06878581B1 Electrostatic discharge protection structure and a method for forming the same 有权
标题翻译：静电放电保护结构及其形成方法
公开(公告)号：US06878581B1
公开(公告)日：2005-04-12
申请号：US09791099
申请日：2001-02-22
申请人： Yuan-Chang Liu , Mu-Chun Wang , Tien-Hao Tang
发明人： Yuan-Chang Liu , Mu-Chun Wang , Tien-Hao Tang
IPC分类号： H01L21/8234 , H01L27/02 , H01L21/8238
CPC分类号： H01L27/027 , H01L21/823418
摘要： A device structure and a method of fabricating an electrostatic discharge (ESD) protection circuit on a semiconductor device. A substrate is provided. A layer of silicon oxide is formed on the substrate. A photoresist mask is formed on the layer of silicon oxide. A species of n-type ions is implanted into the surface to form source/drain regions in the ESD protection area. After removing the photoresist, a metal layer is blanket deposited over the surface. A thermal process is performed to form salicide layers on the source/drain regions. A patterned photoresist is respectively formed to cover a portion of the salicide layer. An etching process is performed to strip away the exposed portion of the salicide layer.
摘要翻译：一种在半导体器件上制造静电放电（ESD）保护电路的器件结构和方法。提供基板。在衬底上形成一层氧化硅。在氧化硅层上形成光致抗蚀剂掩模。将一种n型离子注入表面以在ESD保护区域中形成源极/漏极区域。去除光致抗蚀剂后，金属层被覆盖在表面上。进行热处理以在源极/漏极区域上形成自对准硅化物层。分别形成图案化的光致抗蚀剂以覆盖自对准硅化物层的一部分。执行蚀刻处理以剥离自对准硅化物层的暴露部分。

9. 发明授权

US06242763B1 Low triggering voltage SOI silicon-control-rectifier (SCR) structure 有权
标题翻译：低触发电压SOI硅控整流（SCR）结构
公开(公告)号：US06242763B1
公开(公告)日：2001-06-05
申请号：US09396163
申请日：1999-09-14
申请人： Shiao-Shien Chen , Tien-Hao Tang , Jih-Wen Chou , Mu-Chun Wang
发明人： Shiao-Shien Chen , Tien-Hao Tang , Jih-Wen Chou , Mu-Chun Wang
IPC分类号： H01L2924
CPC分类号： H01L27/0262 , H01L29/87
摘要： A low triggering voltage PD-SOI (Partially-Depleted Silicon-on-Insulator) electrostatic discharge (ESD) protection structure is disclosed. In one embodiment, the protection structure includes: A semiconductor substrate; a thin film layer separated from a bulk silicon substrate by an insulator inside the semiconductor substrate; a first isolation region formed in the thin film layer; a second isolation region formed in the thin film layer; a first region having a first conductivity type formed in between the first and second isolation region; a second region formed in between the first region and the second isolation region, the second region being of a second conductivity type; a third region formed in between the first isolation region and the first region, the third region being of the first conductivity type; a fourth region formed in between the second isolation region and the second region, the fourth region being of the first conductivity type; a fifth region having an exposed upper surface formed in the first region, the fifth region being of the second conductivity type; a sixth region having an exposed surface formed in the second region, the sixth region being of the second conductivity type; and a seventh region having an exposed upper surface formed in the second region and overlapping the first region, moreover, the seventh region being between the fifth and sixth region and the seventh region being of the first conductivity type. Another embodiment of the present invention is very similar to the previous one, which is also extracted in the present specification.
摘要翻译：公开了低触发电压PD-SOI（部分耗尽的绝缘体上硅）静电放电（ESD）保护结构。在一个实施例中，保护结构包括：半导体衬底; 通过半导体衬底内的绝缘体与体硅衬底分离的薄膜层; 形成在所述薄膜层中的第一隔离区域; 形成在所述薄膜层中的第二隔离区域; 形成在第一和第二隔离区之间的具有第一导电类型的第一区域; 形成在所述第一区域和所述第二隔离区域之间的第二区域，所述第二区域是第二导电类型; 第三区域，形成在第一隔离区域和第一区域之间，第三区域是第一导电类型; 形成在第二隔离区域和第二区域之间的第四区域，第四区域是第一导电类型; 第五区域，其具有形成在第一区域中的暴露的上表面，第五区域是第二导电类型; 第六区域，具有形成在第二区域中的暴露表面，第六区域是第二导电类型; 以及具有形成在所述第二区域中并与所述第一区域重叠的暴露的上表面的第七区域，此外，所述第五区域和第六区域之间的所述第七区域和所述第七区域是所述第一导电类型。本发明的另一实施例与前面的实施例非常相似，这也在本说明书中提取。

10. 发明授权

US06159864A Method of preventing damages of gate oxides of a semiconductor wafer in a plasma-related process 失效
标题翻译：在等离子体相关工艺中防止半导体晶片的栅极氧化物损坏的方法
公开(公告)号：US06159864A
公开(公告)日：2000-12-12
申请号：US257172
申请日：1999-02-24
申请人： Mu-Chun Wang , Shih-Chung Li , Shih-Chieh Kao
发明人： Mu-Chun Wang , Shih-Chung Li , Shih-Chieh Kao
IPC分类号： H01L21/28 , H01L23/544 , H01L21/00
CPC分类号： H01L22/34 , H01L21/28123
摘要： The present invention provides a method for preventing gate oxides on a semiconductor wafer from being damaged by electromagnetic waves or particles generated in a plasma-related process. The semiconductor wafer comprises a substrate, a plurality of gate oxides positioned separately on the substrate, a first dielectric layer positioned on the gate oxides for isolating the gate oxides, and a conducting layer positioned on the first dielectric layer having at least one testing slit with a predetermined test pattern installed above each of the gate oxides. The method first performs a predetermined plasma-related process on the surface of the semiconductor wafer. Next, an electrical test is performed to find damaged gate oxides out of the gate oxides on the substrate. Based on damages of the damaged gate oxides, the predetermined plasma-related process is adjusted to prevent gate oxides on other semiconductor wafers from being damaged in the predetermined plasma-related process.
摘要翻译：本发明提供一种防止半导体晶片上的栅极氧化物被等离子体相关工艺中产生的电磁波或微粒损坏的方法。半导体晶片包括基板，分别位于基板上的多个栅极氧化物，位于用于隔离栅极氧化物的栅极氧化物上的第一介电层，以及位于第一介电层上的导电层，其具有至少一个具有安装在每个栅极氧化物上方的预定测试图案。该方法首先在半导体晶片的表面上执行预定的等离子体相关处理。接下来，进行电气测试以从基板上的栅极氧化物中发现损坏的栅极氧化物。基于损坏的栅极氧化物的损坏，调整预定的等离子体相关工艺以防止其它半导体晶片上的栅极氧化物在预定的等离子体相关工艺中被损坏。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式