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1. 发明授权

US06229347B1 Circuit for evaluating an asysmetric antenna effect 有权
标题翻译：评估非对称天线效应的电路
公开(公告)号：US06229347B1
公开(公告)日：2001-05-08
申请号：US09228366
申请日：1999-01-11
申请人： Mu-Chun Wang , Chau-Neng Wu , Shiang Huang-Lu
发明人： Mu-Chun Wang , Chau-Neng Wu , Shiang Huang-Lu
IPC分类号： H03K522
CPC分类号： H03F3/45183 , H03F2203/45674 , H03K5/2418 , H03K5/2481
摘要： A circuit for evaluating the asymmetric antenna effect of a transistor pair is provided, which can be implemented by using bipolar or complementary metal oxide semiconductor (CMOS) transistors to implement a differential amplifier, with which a pair of transistors Q1 and Q2 having similar characteristics are connected. The transistors Q1 and Q2 have a structure of, for example, one polysilicon layer and three metal layers, in which a second metal layer M2 and a third metal layer M3 are used for signal input, and metal layer M1 close to the gate oxide layer of both the transistors Q1 and Q2 are used to obtain a differential antenna ratio. The differential amplifier comprises transistors Q3 and Q4 serving as an active load, and transistor Q5, which is used for adjusting the voltage gain.
摘要翻译：提供了一种用于评估晶体管对的不对称天线效应的电路，其可以通过使用双极或互补金属氧化物半导体（CMOS）晶体管来实现差分放大器来实现，其中具有相似特性的一对晶体管Q1和Q2具有连接的。晶体管Q1和Q2具有例如一个多晶硅层和三个金属层的结构，其中第二金属层M2和第三金属层M3用于信号输入，并且金属层M1靠近栅极氧化物层使用晶体管Q1和Q2两者来获得差分天线比。差分放大器包括用作有源负载的晶体管Q3和Q4以及用于调整电压增益的晶体管Q5。

2. 发明授权

US06849479B2 Substrate based ESD network protection method for flip chip design 有权
标题翻译：基于基板的ESD网络保护方法，用于倒装芯片设计
公开(公告)号：US06849479B2
公开(公告)日：2005-02-01
申请号：US10308446
申请日：2002-12-03
申请人： Chau-Neng Wu
发明人： Chau-Neng Wu
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L23/60 , H01L23/62 , H05K1/18 , H05K3/06 , H05K3/20 , H05K3/46
CPC分类号： H01L23/60 , H01L24/06 , H01L2224/05554 , H01L2924/14 , H05K1/0259 , H05K2201/09681 , H01L2924/00
摘要： In accordance with the objectives of the invention a new method is provided for ESD protection of mounted flip chips. In a first embodiment of the invention, the Input/Output cells and power cells are provided with ESD protection that is connected to a dedicated bump pad. The substrate of the flip chip package interconnects all of the dedicated bump pads, completing the ESD network. Under the second embodiment of the invention, the Input/Output cells and power cells are provided with ESD protection that is connected to a dedicated bump pad, a last metal layer interconnects all of the dedicated bump pads, completing the ESD network.
摘要翻译：根据本发明的目的，提供了一种用于安装倒装芯片的ESD保护的新方法。在本发明的第一实施例中，输入/输出单元和功率单元具有连接到专用凸块焊盘的ESD保护。倒装芯片封装的衬底互连所有专用的焊盘，从而完成ESD网络。在本发明的第二实施例中，输入/输出单元和功率单元被提供有连接到专用凸块焊盘的ESD保护，最后的金属层互连所有专用凸块焊盘，从而完成ESD网络。

3. 发明授权

US5631793A Capacitor-couple electrostatic discharge protection circuit 失效
标题翻译：电容耦合静电放电保护电路
公开(公告)号：US5631793A
公开(公告)日：1997-05-20
申请号：US523653
申请日：1995-09-05
申请人： Ming-Dou Ker , Chung-Yu Wu , Tao Cheng , Chau-Neng Wu , Ta-Lee Yu
发明人： Ming-Dou Ker , Chung-Yu Wu , Tao Cheng , Chau-Neng Wu , Ta-Lee Yu
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0251
摘要： The present invention is related to a capacitor-couple electrostatic discharge (ESD) protection circuit for protecting an internal circuit and/or an output buffer of an IC from being damaged by an ESD current. The capacitor-couple ESD protection circuit according to the present invention includes an ESD bypass device for bypassing the ESD current, a capacitor-couple circuit for coupling a portion of voltage to the ESD bypass device, and a potential leveling device for keeping an ESD voltage transmitted for the internal circuit at a low potential level. By using the present ESD protection circuit, the snapback breakdown voltage can be lowered to protect the very thin gate oxide of the internal circuit especially in the submicron CMOS technologies.
摘要翻译：本发明涉及用于保护IC的内部电路和/或输出缓冲器免受ESD电流损坏的电容器对偶静电放电（ESD）保护电路。根据本发明的电容耦合ESD保护电路包括用于旁路ESD电流的ESD旁路装置，用于将一部分电压耦合到ESD旁路装置的电容器耦合电路和用于保持ESD电压的电位调节装置在低电位电平下为内部电路传输。通过使用本ESD保护电路，可以降低回跳击穿电压，以保护内部电路的非常薄的栅极氧化物，特别是在亚微米CMOS技术中。

4. 再颁专利

USRE38222E1 Electrostatic discharge protection circuit triggered by capacitive-coupling 失效
标题翻译：静电放电保护电路由电容耦合触发
公开(公告)号：USRE38222E1
公开(公告)日：2003-08-19
申请号：US09436404
申请日：1999-11-09
申请人： Chau-Neng Wu
发明人： Chau-Neng Wu
IPC分类号： H01L2362
CPC分类号： H01L27/0266 , H01L27/0251
摘要： An electrostatic discharge (ESD) protection circuit connected to an integrated circuit pad for protecting an internal circuit from ESD damage. The ESD protection circuit includes an NMOS/PMOS transistor, a capacitor, and a load The NMOS/PMOS is configured with a drain connected to the IC pad and a source for connection to the circuit VSS/VDD. Agate of the NMOS/PMOS transistor is tied to the source. The capacitor is connected between the IC pad and the bulk of the NMOS/PMOS transistor The load, which is either another NMOS/PMOS transistor or a resistor, is to be connected between the VSS/VDD and the bulk of the NMOS/PMOS transistor. In accordance with the invention, the NMOS/PMOS transistor is fabricated in a P-well/N-well region of a semiconductor substrate. The capacitor includes an IC pad and a polysilicon layer therebelow, with an intervening dielectric layer.

5. 发明授权

US5777368A Electrostatic discharge protection device and its method of fabrication 失效
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US5777368A
公开(公告)日：1998-07-07
申请号：US648225
申请日：1996-05-13
申请人： Chau-Neng Wu , Ta-Lee Yu , Alex Wang
发明人： Chau-Neng Wu , Ta-Lee Yu , Alex Wang
IPC分类号： H01L27/02 , H01L27/092 , H01L23/62 , H01L29/41
CPC分类号： H01L27/0928 , H01L27/0248 , H01L27/0266
摘要： An electrostatic discharge (ESD) protection device includes a drain region and a source region, each having a heavily-doped region and a lightly-doped region, wherein the junction depth of the lightly-doped region is deeper than that of the heavily doped region. Accordingly, the ESD current density will be decreased owing to the enlarged junction area during the ESD event. In addition, the heat dissipation can be spread over the enlarged junction area instead of being focused on the drain cylindrical edge. Moreover, low parasitic capacitance in the bond pad is achieved because the junction capacitance of the lightly-doped region is smaller than that of the heavily-doped region. Furthermore, conducting blocks are arranged between the lightly-doped regions and the source/drain electrodes, respectively, to prevent the metal melt filament from spiking the junction.
摘要翻译：静电放电（ESD）保护器件包括漏极区域和源极区域，每个区域具有重掺杂区域和轻掺杂区域，其中轻掺杂区域的结深度比重掺杂区域的深度深。因此，由于ESD事件期间扩大的接合面积，ESD电流密度将降低。此外，散热可以扩展在扩大的接合面积上，而不是聚焦在排水圆柱形边缘上。此外，由于轻掺杂区域的结电容小于重掺杂区域的结电容，因此实现了接合焊盘中的低寄生电容。此外，导电块分别布置在轻掺杂区域和源/漏电极之间，以防止金属熔体丝线尖端接合。

6. 发明申请

US20060274465A1 Electrostatic discharge (ESD) protection circuits using metal-insulator-metal (MIM) capacitors 审中-公开
标题翻译：使用金属绝缘体金属（MIM）电容器的静电放电（ESD）保护电路
公开(公告)号：US20060274465A1
公开(公告)日：2006-12-07
申请号：US11140991
申请日：2005-06-01
申请人： Chau-Neng Wu , Jian-Hsing Lee
发明人： Chau-Neng Wu , Jian-Hsing Lee
IPC分类号： H02H9/00
CPC分类号： H01L27/0251
摘要： An electrostatic discharge (ESD) protection circuit is provided for use in an integrated circuit (IC) to provide protection against an ESD on a contact pad of the IC. The IC includes a driver circuit. The ESD protection circuit is connectable to a first power supply voltage and includes an ESD protection device connectable between the contact pad and the first power supply voltage and a capacitor connectable between the contact pad and the driver circuit.
摘要翻译：提供了用于集成电路（IC）中的静电放电（ESD）保护电路，以提供针对IC接触焊盘上ESD的保护。 IC包括驱动电路。 ESD保护电路可连接到第一电源电压，并且包括可在接触焊盘和第一电源电压之间连接的ESD保护装置以及可在接触焊盘和驱动器电路之间连接的电容器。

7. 发明授权

US5892262A Capacitor-triggered electrostatic discharge protection circuit 失效
标题翻译：电容触发式静电放电保护电路
公开(公告)号：US5892262A
公开(公告)日：1999-04-06
申请号：US655073
申请日：1996-06-03
申请人： Chau-Neng Wu , Ming-Dou Ker
发明人： Chau-Neng Wu , Ming-Dou Ker
IPC分类号： H01L27/02 , H01L23/62
CPC分类号： H01L27/0251
摘要： A capacitor-triggered electrostatic discharge (ESD) protection circuit is disposed between a metal pad and V.sub.ss potential level, wherein the pad may be an input pad, an output pad, or a V.sub.DD power rail. The circuit includes a thick oxide device, a capacitor, and a resistor. The thick oxide device is configured with its drain and source connected to the pad and circuit ground V.sub.SS, respectively. The gate of the thick oxide device is tied to the pad, and the oxide device bulk is coupled by the resistor to circuit ground V.sub.SS. The capacitor is connected between the pad and the bulk of the thick oxide device. The bulk of the device is constructed by a P-well region formed in a substrate. The capacitor is formed between the pad and a polysilicon layer just therebelow, without consuming extra layout areas. When a positive-to-ground ESD pulse is conducted at the pad, the capacitor will couple the ESD voltage to the well region, forward bias the bulk/source junction, and then turn on the thick oxide device operated in a bipolar mode to bypass the ESD stress. Moreover, a diode is connected between the pad and circuit ground by its cathode and anode, respectively, to bypass a negative-to-ground ESD pulse. The diode can be an extra or built-in PN junction.
摘要翻译：电容触发的静电放电（ESD）保护电路设置在金属焊盘和Vss电位之间，其中焊盘可以是输入焊盘，输出焊盘或VDD电源轨。该电路包括厚氧化物，电容器和电阻。厚氧化物器件被配置为其漏极和源极分别连接到焊盘和电路接地VSS。厚氧化物器件的栅极连接到焊盘，并且氧化物器件体积被电阻器耦合到电路接地VSS。电容器连接在焊盘和厚氧化物器件的主体之间。器件的主体由形成在衬底中的P阱区域构成。电容器形成在焊盘和刚好在其之间的多晶硅层之间，而不消耗额外的布局面积。当在焊盘上进行正对地ESD脉冲时，电容器将ESD静电电压耦合到阱区域，正向偏置体/源极结，然后打开以双极模式工作的厚氧化物器件旁路 ESD应力。此外，二极管分别通过其阴极和阳极连接在焊盘和电路接地之间，以绕过负对地ESD脉冲。二极管可以是额外的或内置的PN结。

8. 发明授权

US5777369A Bit-line pull-up circuit or static random access memory (SRAM) devices 失效
标题翻译：位线上拉电路或静态随机存取存储器（SRAM）器件
公开(公告)号：US5777369A
公开(公告)日：1998-07-07
申请号：US778264
申请日：1997-01-02
申请人： Shi-Tron Lin , Ming-Tsan Yeh , Chau-Neng Wu , Chi-Hsi Wu
发明人： Shi-Tron Lin , Ming-Tsan Yeh , Chau-Neng Wu , Chi-Hsi Wu
IPC分类号： G11C11/412 , G11C11/419 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： G11C11/4125 , G11C11/419 , Y10S257/903
摘要： A bit-line pull-up circuit for an SRAM device which utilizes an improved diffusion structure for enhanced immunity of the SRAM device against electrostatic discharge. The improved diffusion structure includes an undivided diffusion region that serves as a common drain for a plurality of MOS transistors. The undivided diffusion region has at least a pair of recessed diffusion edges formed on opposite sides thereof. The forming of the recessed diffusion edges prevents the so-called electrical field crowding effect and also enhances ESD immunity for the MOS transistor. Further, since the drain diffusion region is an undivided area, an increased number of metal contact windows are provided therein, and at least one of the metal contact windows is arranged substantially between the two recessed diffusion edges. In the event of an electrostatic discharge, this allows the discharge current flowing into the drain to be divided into a greater number of small-magnitude currents flowing to the source.
摘要翻译：一种用于SRAM器件的位线上拉电路，其利用改进的扩散结构来增强SRAM器件对静电放电的免疫力。改进的扩散结构包括用作多个MOS晶体管的公共漏极的未分开的扩散区域。未分开的扩散区域具有形成在其相对侧上的至少一对凹进的扩散边缘。凹陷扩散边缘的形成防止了所谓的电场拥挤效应，并且还提高了MOS晶体管的ESD抗扰度。此外，由于漏极扩散区域是不分割的区域，所以在其中设置了增加数量的金属接触窗口，并且金属接触窗口中的至少一个基本上被布置在两个凹进的扩散边缘之间。在静电放电的情况下，这允许流入漏极的放电电流被分成更大数量的流向源极的小电流电流。

9. 发明授权

US5721656A Electrostatc discharge protection network 失效
标题翻译： Electrostatc放电保护网络
公开(公告)号：US5721656A
公开(公告)日：1998-02-24
申请号：US661105
申请日：1996-06-10
申请人： Chau-Neng Wu , Ming-Dou Ker
发明人： Chau-Neng Wu , Ming-Dou Ker
IPC分类号： H01L27/02 , H02H3/22
CPC分类号： H01L27/0251
摘要： An electrostatic discharge protection network which diverts ESD stress arising between any two contact pads of an IC device, in order to prevent damage to the internal circuitry of the IC device. An ESD discharge bus is arranged around the periphery of an IC chip. Between each IC pad and the discharge bus, there is a protection circuit to directly bypass an ESD stress arising at any two IC pads. Each ESD protection circuit includes a diode, a thick-oxide device, a resistor, and a capacitor. The protection circuit is operated in snapback mode without causing breakdown. Therefore, the triggering voltage of the ESD protection circuit is lowered to the level of the snapback voltage but not to the level of the breakdown voltage.
摘要翻译：一种静电放电保护网络，其转移IC器件的任何两个接触焊盘之间产生的ESD应力，以防止损坏IC器件的内部电路。 ESD放电总线设置在IC芯片的周围。在每个IC焊盘和放电总线之间，有一个保护电路直接绕过任何两个IC焊盘产生的ESD应力。每个ESD保护电路包括二极管，厚氧化物装置，电阻器和电容器。保护电路以快速恢复模式运行，不会导致故障。因此，ESD保护电路的触发电压降低到回跳电压的水平，但不降低到击穿电压的水平。

10. 发明申请

US20080055802A1 ESD protection circuit for a mixed-voltage semiconductor device 有权
公开(公告)号：US20080055802A1
公开(公告)日：2008-03-06
申请号：US11509998
申请日：2006-08-26
申请人： Chau-Neng Wu , Jian-Hsing Lee
发明人： Chau-Neng Wu , Jian-Hsing Lee
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： An ESD protection circuit is implemented for a semiconductor device having a first circuit system operating with a first power supply voltage and a first complementary power supply voltage, and a second circuit system operating with a second power supply voltage and a second complementary power supply voltage. The ESD protection circuit includes a first diode having an anode coupled to the first power supply voltage and a cathode coupled to a first node connecting the first circuit system and the second circuit system for preventing a crosstalk of current between the first power supply voltage and the second complementary power supply voltage. A first MOS transistor module is coupled between the first node and the first complementary power supply for selectively creating a current path from the first node to the first complementary supply voltage for dissipating an ESD current during an ESD event.

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