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1. 发明授权

US06242763B1 Low triggering voltage SOI silicon-control-rectifier (SCR) structure 有权
标题翻译：低触发电压SOI硅控整流（SCR）结构
公开(公告)号：US06242763B1
公开(公告)日：2001-06-05
申请号：US09396163
申请日：1999-09-14
申请人： Shiao-Shien Chen , Tien-Hao Tang , Jih-Wen Chou , Mu-Chun Wang
发明人： Shiao-Shien Chen , Tien-Hao Tang , Jih-Wen Chou , Mu-Chun Wang
IPC分类号： H01L2924
CPC分类号： H01L27/0262 , H01L29/87
摘要： A low triggering voltage PD-SOI (Partially-Depleted Silicon-on-Insulator) electrostatic discharge (ESD) protection structure is disclosed. In one embodiment, the protection structure includes: A semiconductor substrate; a thin film layer separated from a bulk silicon substrate by an insulator inside the semiconductor substrate; a first isolation region formed in the thin film layer; a second isolation region formed in the thin film layer; a first region having a first conductivity type formed in between the first and second isolation region; a second region formed in between the first region and the second isolation region, the second region being of a second conductivity type; a third region formed in between the first isolation region and the first region, the third region being of the first conductivity type; a fourth region formed in between the second isolation region and the second region, the fourth region being of the first conductivity type; a fifth region having an exposed upper surface formed in the first region, the fifth region being of the second conductivity type; a sixth region having an exposed surface formed in the second region, the sixth region being of the second conductivity type; and a seventh region having an exposed upper surface formed in the second region and overlapping the first region, moreover, the seventh region being between the fifth and sixth region and the seventh region being of the first conductivity type. Another embodiment of the present invention is very similar to the previous one, which is also extracted in the present specification.
摘要翻译：公开了低触发电压PD-SOI（部分耗尽的绝缘体上硅）静电放电（ESD）保护结构。在一个实施例中，保护结构包括：半导体衬底; 通过半导体衬底内的绝缘体与体硅衬底分离的薄膜层; 形成在所述薄膜层中的第一隔离区域; 形成在所述薄膜层中的第二隔离区域; 形成在第一和第二隔离区之间的具有第一导电类型的第一区域; 形成在所述第一区域和所述第二隔离区域之间的第二区域，所述第二区域是第二导电类型; 第三区域，形成在第一隔离区域和第一区域之间，第三区域是第一导电类型; 形成在第二隔离区域和第二区域之间的第四区域，第四区域是第一导电类型; 第五区域，其具有形成在第一区域中的暴露的上表面，第五区域是第二导电类型; 第六区域，具有形成在第二区域中的暴露表面，第六区域是第二导电类型; 以及具有形成在所述第二区域中并与所述第一区域重叠的暴露的上表面的第七区域，此外，所述第五区域和第六区域之间的所述第七区域和所述第七区域是所述第一导电类型。本发明的另一实施例与前面的实施例非常相似，这也在本说明书中提取。

2. 发明授权

US06873505B2 Electrostatic discharge protective circuitry equipped with a common discharge line 有权
标题翻译：静电放电保护电路配有普通放电线
公开(公告)号：US06873505B2
公开(公告)日：2005-03-29
申请号：US09912288
申请日：2001-07-24
申请人： Shiao-Shien Chen , Tien-Hao Tang , Mu-Chun Wang
发明人： Shiao-Shien Chen , Tien-Hao Tang , Mu-Chun Wang
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0262 , H01L27/0255
摘要： A semiconductor device having an electrostatic discharge protective circuitry adapted to a common discharge line (CDL) is disclosed. In the embodiments of the present invention, semiconductor device includes a plurality of bonding pads, each having at least one connecting terminal, a common discharge line, and a protective device connected between the connecting terminal and the common discharge line. Moreover, the protective device is composed of a silicon-control-rectifier that is used for electrostatic discharge protection and a zener diode for lowering a trigger voltage of the silicon-control-rectifier.
摘要翻译：公开了具有适用于公共放电线（CDL）的静电放电保护电路的半导体器件。在本发明的实施例中，半导体器件包括多个接合焊盘，每个焊盘具有至少一个连接端子，公共放电线以及连接在连接端子和公共放电线路之间的保护器件。此外，保护装置由用于静电放电保护的硅控整流器和用于降低硅控整流器的触发电压的齐纳二极管组成。

3. 发明申请

US20050110092A1 CMOS silicon-control-rectifier (SCR) structure for electrostatic discharge (ESD) protection 有权
标题翻译： CMOS硅控整流器（SCR）结构，用于静电放电（ESD）保护
公开(公告)号：US20050110092A1
公开(公告)日：2005-05-26
申请号：US10954735
申请日：2004-09-30
申请人： Shiao-Shien Chen , Tien-Hao Tang , Mu-Chun Wang
发明人： Shiao-Shien Chen , Tien-Hao Tang , Mu-Chun Wang
IPC分类号： H01L23/62 , H01L27/02 , H01L29/41 , H01L29/74
CPC分类号： H01L27/0262 , H01L29/87 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection device, including a silicon-control-rectifier, in complementary metal-oxide semiconductor (CMOS) process is disclosed. In one embodiment of the present invention, the protection device includes a semiconductor substrate having a first conductivity type. A well region formed with a second conductivity type in the semiconductor substrate. A first region formed within the semiconductor substrate and outside the well region. A second region formed within the semiconductor substrate and in between the first region and the well region. Moreover, a third region formed having a portion in the well region and another portion outside the well region. A fourth region formed in the well region. A fifth region also formed within the well region and in between the third region and the fourth region. Furthermore, the third region and the fifth region form the p+-n+ junction of the zener diode and the breakdown voltage of the zener diode is controlled by adjusting the ion dosage in the third region. Another embodiment of the present invention is very similar to the previous one, which is also extracted in the present specification.
摘要翻译：公开了一种在互补金属氧化物半导体（CMOS）工艺中的包括硅控制整流器的静电放电保护器件。在本发明的一个实施例中，保护装置包括具有第一导电类型的半导体衬底。在半导体衬底中形成有第二导电类型的阱区。形成在半导体衬底内并在阱区外的第一区域。形成在半导体衬底内并位于第一区域与阱区之间的第二区域。此外，第三区域形成为具有在所述阱区域中的一部分以及在所述阱区域外部的另一部分。形成在该区域中的第四区域。第五区域也形成在阱区域内并且在第三区域和第四区域之间。此外，第三区域和第五区域形成齐纳二极管的p + + / - SUP + +连接，并且齐纳二极管的击穿电压通过调节离子剂量在第三个地区。本发明的另一实施例与前面的实施例非常相似，这也在本说明书中提取。

4. 发明授权

US07217980B2 CMOS silicon-control-rectifier (SCR) structure for electrostatic discharge (ESD) protection 有权
标题翻译： CMOS硅控整流器（SCR）结构，用于静电放电（ESD）保护
公开(公告)号：US07217980B2
公开(公告)日：2007-05-15
申请号：US10954735
申请日：2004-09-30
申请人： Shiao-Shien Chen , Tien-Hao Tang , Mu-Chun Wang
发明人： Shiao-Shien Chen , Tien-Hao Tang , Mu-Chun Wang
IPC分类号： H01L23/62 , H01L29/74 , H01L31/111
CPC分类号： H01L27/0262 , H01L29/87 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection device, including a silicon-control-rectifier, in complementary metal-oxide semiconductor (CMOS) process is disclosed. in one embodiment of the present invention, the protection device includes a semiconductor substrate having a first conductivity type. A well region formed with a second conductivity type in the semiconductor substrate. A first region formed in the well region. A second region formed having a portion in the weil region and another portion outside the well region, but still within the semiconductor substrate. Moreover, a third region formed within the well region and in between the first; region and the second region. A fourth region formed within the semiconductor substrate and outside the well region. A fifth region formed within the semiconductor substrate and in between the second region and the fourth region. Furthermore, the second region and the fifth region form the n+-p+ junction of a zener diode and the breakdown voltage of the zener diode is controlled by adjusting the ion dosage in the second region.
摘要翻译：公开了一种在互补金属氧化物半导体（CMOS）工艺中的包括硅控制整流器的静电放电保护器件。在本发明的一个实施例中，保护装置包括具有第一导电类型的半导体衬底。在半导体衬底中形成有第二导电类型的阱区。在该区域中形成的第一区域。第二区域形成为具有在所述il区域中的一部分和在所述阱区域外部但在所述半导体衬底内的另一部分。此外，形成在所述井区域内且在所述第一区域之间的第三区域; 区域和第二区域。形成在半导体衬底内并在阱区外的第四区域。形成在所述半导体衬底内并且位于所述第二区域和所述第四区域之间的第五区域。此外，第二区域和第五区域形成齐纳二极管的n + + / - p + + + / - 连接点，并且齐纳二极管的击穿电压通过调节离子剂量在第二个地区。

5. 发明授权

US06878581B1 Electrostatic discharge protection structure and a method for forming the same 有权
标题翻译：静电放电保护结构及其形成方法
公开(公告)号：US06878581B1
公开(公告)日：2005-04-12
申请号：US09791099
申请日：2001-02-22
申请人： Yuan-Chang Liu , Mu-Chun Wang , Tien-Hao Tang
发明人： Yuan-Chang Liu , Mu-Chun Wang , Tien-Hao Tang
IPC分类号： H01L21/8234 , H01L27/02 , H01L21/8238
CPC分类号： H01L27/027 , H01L21/823418
摘要： A device structure and a method of fabricating an electrostatic discharge (ESD) protection circuit on a semiconductor device. A substrate is provided. A layer of silicon oxide is formed on the substrate. A photoresist mask is formed on the layer of silicon oxide. A species of n-type ions is implanted into the surface to form source/drain regions in the ESD protection area. After removing the photoresist, a metal layer is blanket deposited over the surface. A thermal process is performed to form salicide layers on the source/drain regions. A patterned photoresist is respectively formed to cover a portion of the salicide layer. An etching process is performed to strip away the exposed portion of the salicide layer.
摘要翻译：一种在半导体器件上制造静电放电（ESD）保护电路的器件结构和方法。提供基板。在衬底上形成一层氧化硅。在氧化硅层上形成光致抗蚀剂掩模。将一种n型离子注入表面以在ESD保护区域中形成源极/漏极区域。去除光致抗蚀剂后，金属层被覆盖在表面上。进行热处理以在源极/漏极区域上形成自对准硅化物层。分别形成图案化的光致抗蚀剂以覆盖自对准硅化物层的一部分。执行蚀刻处理以剥离自对准硅化物层的暴露部分。

6. 发明授权

US06483045B1 Via plug layout structure for connecting different metallic layers 失效
标题翻译：通过插头布局结构连接不同的金属层
公开(公告)号：US06483045B1
公开(公告)日：2002-11-19
申请号：US09626409
申请日：2000-07-26
申请人： Mu-Chun Wang , Shih-Chieh Kao , Shiang Huang-Lu , Yuan-Chang Liu
发明人： Mu-Chun Wang , Shih-Chieh Kao , Shiang Huang-Lu , Yuan-Chang Liu
IPC分类号： H05K111
CPC分类号： H01L23/528 , H01L23/5226 , H01L2924/0002 , H05K1/115 , H05K2201/0769 , H05K2201/0969 , H05K2201/0979 , H01L2924/00
摘要： A via plug layout structure for connecting different metallic layers. The structure includes a plurality of via plugs arranged in a fan-shaped pattern and a plurality of empty bars positioned between a single via plug and the fanned-out via plugs so that incoming current to the single via plug is equally distributed to every one of the fanned-out via plug and current stress in each fanned-out via plug is identical. Hence, via plugs having particularly serious electromigration problem can be discovered. In addition, single via plug having different critical dimension can be fabricated so that maximum critical dimension sustainable by the via plug is determined after an electromigration test.
摘要翻译：用于连接不同金属层的通孔插头布局结构。该结构包括布置成扇形图案的多个通孔塞和位于单个通孔插头和扇形通孔之间的多个空杆，使得到单个通孔塞的进入电流被均等地分配到通过插头的每个扇形插头中的插头和电流应力都是相同的。因此，可以发现通过具有特别严重的电迁移问题的插头。此外，可以制造具有不同临界尺寸的单通孔塞，使得在电迁移测试之后确定由通孔插塞可持续的最大临界尺寸。

7. 发明授权

US06051986A Method of testing a transistor 失效
标题翻译：测试晶体管的方法
公开(公告)号：US06051986A
公开(公告)日：2000-04-18
申请号：US999236
申请日：1997-12-29
申请人： Mu-Chun Wang
发明人： Mu-Chun Wang
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： A method of testing for a kink effect typically occurring during the fabrication of shallow trench isolation of a transistor in an integrated circuit. A curve of source/drain current versus gate voltage is plotted. A second order differential of the curve is performed and plotted, and the existence of a kink effect is determined by the number of the local maxima and local minima. The degree of kink effect as low as and below a 0.25 .mu.m level is determined according to the level of a global minimum value.
摘要翻译：在集成电路中的晶体管的浅沟槽隔离的制造期间通常发生的扭结效应的测试方法。绘制源极/漏极电流与栅极电压的曲线。执行曲线的二阶微分，并绘制扭结效应的存在由局部最大值和局部最小值的数量确定。根据全局最小值的水平确定低于或低于0.25μm水平的扭结效应的程度。

8. 发明授权

US06159864A Method of preventing damages of gate oxides of a semiconductor wafer in a plasma-related process 失效
标题翻译：在等离子体相关工艺中防止半导体晶片的栅极氧化物损坏的方法
公开(公告)号：US06159864A
公开(公告)日：2000-12-12
申请号：US257172
申请日：1999-02-24
申请人： Mu-Chun Wang , Shih-Chung Li , Shih-Chieh Kao
发明人： Mu-Chun Wang , Shih-Chung Li , Shih-Chieh Kao
IPC分类号： H01L21/28 , H01L23/544 , H01L21/00
CPC分类号： H01L22/34 , H01L21/28123
摘要： The present invention provides a method for preventing gate oxides on a semiconductor wafer from being damaged by electromagnetic waves or particles generated in a plasma-related process. The semiconductor wafer comprises a substrate, a plurality of gate oxides positioned separately on the substrate, a first dielectric layer positioned on the gate oxides for isolating the gate oxides, and a conducting layer positioned on the first dielectric layer having at least one testing slit with a predetermined test pattern installed above each of the gate oxides. The method first performs a predetermined plasma-related process on the surface of the semiconductor wafer. Next, an electrical test is performed to find damaged gate oxides out of the gate oxides on the substrate. Based on damages of the damaged gate oxides, the predetermined plasma-related process is adjusted to prevent gate oxides on other semiconductor wafers from being damaged in the predetermined plasma-related process.
摘要翻译：本发明提供一种防止半导体晶片上的栅极氧化物被等离子体相关工艺中产生的电磁波或微粒损坏的方法。半导体晶片包括基板，分别位于基板上的多个栅极氧化物，位于用于隔离栅极氧化物的栅极氧化物上的第一介电层，以及位于第一介电层上的导电层，其具有至少一个具有安装在每个栅极氧化物上方的预定测试图案。该方法首先在半导体晶片的表面上执行预定的等离子体相关处理。接下来，进行电气测试以从基板上的栅极氧化物中发现损坏的栅极氧化物。基于损坏的栅极氧化物的损坏，调整预定的等离子体相关工艺以防止其它半导体晶片上的栅极氧化物在预定的等离子体相关工艺中被损坏。

9. 发明授权

US06060347A Method for preventing damage to gate oxide from well in complementary metal-oxide semiconductor 有权
标题翻译：用于防止互补金属氧化物半导体中的阱对栅极氧化物的损伤的方法
公开(公告)号：US06060347A
公开(公告)日：2000-05-09
申请号：US139445
申请日：1998-08-25
申请人： Mu-Chun Wang
发明人： Mu-Chun Wang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857
摘要： A method for preventing damage to a gate oxide layer from a floating well in a CMOS device includes a first via plug and a second via plug formed in a dielectric layer. The first via plug is coupled to a substrate and the second via plug is coupled to the well. These two via plugs are further coupled by a conductive bridge so that both the well and the substrate have the same voltage.
摘要翻译：一种用于防止CMOS器件中的浮动阱对栅极氧化物层的损坏的方法包括形成在电介质层中的第一通孔插塞和第二通孔插塞。第一通孔塞耦合到基底，第二通孔塞耦合到孔。这两个通孔插头进一步通过导电桥耦合，使得阱和衬底都具有相同的电压。

10. 发明授权

US06291285B1 Method for protecting gate oxide layer and monitoring damage 有权
标题翻译：保护栅极氧化层和监测损伤的方法
公开(公告)号：US06291285B1
公开(公告)日：2001-09-18
申请号：US09215884
申请日：1998-12-16
申请人： Mu-Chun Wang , Shiang Huang-Lu
发明人： Mu-Chun Wang , Shiang Huang-Lu
IPC分类号： H01L218234
CPC分类号： H01L21/28123 , H01L23/552 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： A method for protecting the gate oxide layer of a MOS device. The method can also be used to monitor the intensity of radiation and charged particles falling on the gate oxide layer. The method includes the provision of a substrate having a gate structure thereon and an inter-layer dielectric layer over the gate structure, wherein the gate structure further includes a gate oxide layer and a gate electrode. Thereafter, a shielding layer is formed over the inter-layer dielectric layer, and then a protection diode is formed to link the shielding to the substrate.
摘要翻译：一种用于保护MOS器件的栅极氧化物层的方法。该方法还可用于监测落在栅极氧化物层上的辐射强度和带电粒子的强度。该方法包括提供其上具有栅极结构的衬底和栅极结构上的层间电介质层，其中栅极结构还包括栅极氧化物层和栅电极。此后，在层间电介质层上形成屏蔽层，然后形成保护二极管以将屏蔽连接到基板。

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