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1. 发明授权

US06483045B1 Via plug layout structure for connecting different metallic layers 失效
标题翻译：通过插头布局结构连接不同的金属层
公开(公告)号：US06483045B1
公开(公告)日：2002-11-19
申请号：US09626409
申请日：2000-07-26
申请人： Mu-Chun Wang , Shih-Chieh Kao , Shiang Huang-Lu , Yuan-Chang Liu
发明人： Mu-Chun Wang , Shih-Chieh Kao , Shiang Huang-Lu , Yuan-Chang Liu
IPC分类号： H05K111
CPC分类号： H01L23/528 , H01L23/5226 , H01L2924/0002 , H05K1/115 , H05K2201/0769 , H05K2201/0969 , H05K2201/0979 , H01L2924/00
摘要： A via plug layout structure for connecting different metallic layers. The structure includes a plurality of via plugs arranged in a fan-shaped pattern and a plurality of empty bars positioned between a single via plug and the fanned-out via plugs so that incoming current to the single via plug is equally distributed to every one of the fanned-out via plug and current stress in each fanned-out via plug is identical. Hence, via plugs having particularly serious electromigration problem can be discovered. In addition, single via plug having different critical dimension can be fabricated so that maximum critical dimension sustainable by the via plug is determined after an electromigration test.
摘要翻译：用于连接不同金属层的通孔插头布局结构。该结构包括布置成扇形图案的多个通孔塞和位于单个通孔插头和扇形通孔之间的多个空杆，使得到单个通孔塞的进入电流被均等地分配到通过插头的每个扇形插头中的插头和电流应力都是相同的。因此，可以发现通过具有特别严重的电迁移问题的插头。此外，可以制造具有不同临界尺寸的单通孔塞，使得在电迁移测试之后确定由通孔插塞可持续的最大临界尺寸。

2. 发明授权

US06191602B1 Wafer acceptance testing method and structure of a test key used in the method 有权
标题翻译：晶圆验收测试方法和方法中使用的测试键的结构
公开(公告)号：US06191602B1
公开(公告)日：2001-02-20
申请号：US09220097
申请日：1998-12-23
申请人： Shiang Huang-Lu , Mu-Chun Wang , Kun-Cho Chen
发明人： Shiang Huang-Lu , Mu-Chun Wang , Kun-Cho Chen
IPC分类号： G01R3126
CPC分类号： H01L22/34
摘要： A wafer acceptance testing (WAT) method with a test key is provided. The test key structure includes a testing structure on a substrate. An inter-layer-dielectric layer covers over the substrate to isolate the testing structure. A grounded metal layer is located on the inter-layer dielectric layer. An interconnecting structure is located on the grounded metal layer. A conductive pad layer and a passivation layer are sequentially located on the interconnecting structure. The testing structure is electrically coupled to the interconnecting structure. The interconnecting structure is also electrically coupled to the conductive pad layer. The grounded metal layer is grounded without any further coupling such that the grounded metal layer is not coupled to the testing structure and the interconnecting structure.
摘要翻译：提供了具有测试键的晶片验收测试（WAT）方法。测试键结构包括在衬底上的测试结构。层间电介质层覆盖在衬底上以隔离测试结构。接地的金属层位于层间电介质层上。互连结构位于接地的金属层上。导电焊盘层和钝化层依次位于互连结构上。测试结构电耦合到互连结构。互连结构也电耦合到导电焊盘层。接地的金属层没有任何进一步的耦合而接地，使得接地的金属层不耦合到测试结构和互连结构。

3. 发明授权

US06229347B1 Circuit for evaluating an asysmetric antenna effect 有权
标题翻译：评估非对称天线效应的电路
公开(公告)号：US06229347B1
公开(公告)日：2001-05-08
申请号：US09228366
申请日：1999-01-11
申请人： Mu-Chun Wang , Chau-Neng Wu , Shiang Huang-Lu
发明人： Mu-Chun Wang , Chau-Neng Wu , Shiang Huang-Lu
IPC分类号： H03K522
CPC分类号： H03F3/45183 , H03F2203/45674 , H03K5/2418 , H03K5/2481
摘要： A circuit for evaluating the asymmetric antenna effect of a transistor pair is provided, which can be implemented by using bipolar or complementary metal oxide semiconductor (CMOS) transistors to implement a differential amplifier, with which a pair of transistors Q1 and Q2 having similar characteristics are connected. The transistors Q1 and Q2 have a structure of, for example, one polysilicon layer and three metal layers, in which a second metal layer M2 and a third metal layer M3 are used for signal input, and metal layer M1 close to the gate oxide layer of both the transistors Q1 and Q2 are used to obtain a differential antenna ratio. The differential amplifier comprises transistors Q3 and Q4 serving as an active load, and transistor Q5, which is used for adjusting the voltage gain.
摘要翻译：提供了一种用于评估晶体管对的不对称天线效应的电路，其可以通过使用双极或互补金属氧化物半导体（CMOS）晶体管来实现差分放大器来实现，其中具有相似特性的一对晶体管Q1和Q2具有连接的。晶体管Q1和Q2具有例如一个多晶硅层和三个金属层的结构，其中第二金属层M2和第三金属层M3用于信号输入，并且金属层M1靠近栅极氧化物层使用晶体管Q1和Q2两者来获得差分天线比。差分放大器包括用作有源负载的晶体管Q3和Q4以及用于调整电压增益的晶体管Q5。

4. 发明授权

US06291285B1 Method for protecting gate oxide layer and monitoring damage 有权
标题翻译：保护栅极氧化层和监测损伤的方法
公开(公告)号：US06291285B1
公开(公告)日：2001-09-18
申请号：US09215884
申请日：1998-12-16
申请人： Mu-Chun Wang , Shiang Huang-Lu
发明人： Mu-Chun Wang , Shiang Huang-Lu
IPC分类号： H01L218234
CPC分类号： H01L21/28123 , H01L23/552 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： A method for protecting the gate oxide layer of a MOS device. The method can also be used to monitor the intensity of radiation and charged particles falling on the gate oxide layer. The method includes the provision of a substrate having a gate structure thereon and an inter-layer dielectric layer over the gate structure, wherein the gate structure further includes a gate oxide layer and a gate electrode. Thereafter, a shielding layer is formed over the inter-layer dielectric layer, and then a protection diode is formed to link the shielding to the substrate.
摘要翻译：一种用于保护MOS器件的栅极氧化物层的方法。该方法还可用于监测落在栅极氧化物层上的辐射强度和带电粒子的强度。该方法包括提供其上具有栅极结构的衬底和栅极结构上的层间电介质层，其中栅极结构还包括栅极氧化物层和栅电极。此后，在层间电介质层上形成屏蔽层，然后形成保护二极管以将屏蔽连接到基板。

5. 发明授权

US06245610B1 Method of protecting a well at a floating stage 失效
标题翻译：在浮动阶段保护井的方法
公开(公告)号：US06245610B1
公开(公告)日：2001-06-12
申请号：US09406517
申请日：1999-09-28
申请人： Mu-Chun Wang , Tzung-Han Lee , Shiang Huang-Lu
发明人： Mu-Chun Wang , Tzung-Han Lee , Shiang Huang-Lu
IPC分类号： H01L218234
CPC分类号： H01L21/823475 , H01L21/76892 , H01L21/8234 , H01L21/823493
摘要： A method of protecting a well at a floating stage. In a first conductive type substrate, a second conductive type well is formed. A first conductive type heavily doped region and a second conductive type heavily doped region are respectively formed in the first conductive type substrate and the second conductive type well. These two heavily doped regions are electrically connected with each at an early stage of fabrication process to provide a protection from being damaged during subsequent plasma process or other processes. While forming a top metal layer of a multi-level interconnect, these two heavily doped regions are disconnected, that is, open to each other, to obtain a better electrical characteristic of the device or the integrated circuit formed on the substrate.
摘要翻译：在浮动阶段保护井的方法。在第一导电型衬底中，形成第二导电型阱。第一导电型重掺杂区和第二导电型重掺杂区分别形成在第一导电类型衬底和第二导电类型阱中。这两个重掺杂区域在制造工艺的早期阶段与每一个电连接以提供保护以防止在随后的等离子体处理或其它工艺期间损坏。当形成多层互连的顶层金属层时，这两个重掺杂区域被断开，即彼此开放，以获得器件或形成在衬底上的集成电路的更好的电特性。

6. 发明授权

US5990519A Electrostatic discharge structure 有权
标题翻译：静电放电结构
公开(公告)号：US5990519A
公开(公告)日：1999-11-23
申请号：US200891
申请日：1998-11-27
申请人： Shiang Huang-Lu , Tien-Hao Tang , Kuan-Yu Fu
发明人： Shiang Huang-Lu , Tien-Hao Tang , Kuan-Yu Fu
IPC分类号： H01L23/60 , H01L23/62
CPC分类号： H01L23/60 , H01L2924/0002
摘要： A spike electrostatic discharge (ESD) cavity structure includes an etching stop layer including, for example, polysilicon or metal material. The etching stop layer is used as the etching stop to form an opening in the dielectric layer, inside of which a number of discharging layer pairs are formed. The opening exposes the end portions of the discharge layer pairs. The opening is a cavity and can be vacuumed or filled with air.
摘要翻译：尖峰静电放电（ESD）腔结构包括例如包括多晶硅或金属材料的蚀刻停止层。蚀刻停止层用作蚀刻停止层以在电介质层中形成开口，其内部形成有多个放电层对。开口露出放电层对的端部。开口是一个空腔，可以被抽真空或充满空气。

7. 发明授权

US06479870B1 ESD device with salicide layer isolated by shallow trench isolation for saving one salicide block photomask 有权
标题翻译：具有通过浅沟槽隔离隔离的自对隔层的ESD装置用于节省一个自杀化合物块光掩模
公开(公告)号：US06479870B1
公开(公告)日：2002-11-12
申请号：US09739032
申请日：2000-11-21
申请人： Shiao-Shien Chen , Tien-Hao Tang , Shiang Huang-Lu
发明人： Shiao-Shien Chen , Tien-Hao Tang , Shiang Huang-Lu
IPC分类号： H01L2362
CPC分类号： H01L27/0251
摘要： A electrostatic discharge (ESD) device with salicide layers isolated by a shallow trench isolation in order to save one salicide block photomask. A shallow trench isolation is formed in drain region to isolate a portion of the drain region, so that the drain region is partitioned into two parts. A salicide layer is formed on the drain region. Since the salicide layer is not formed on the shallow trench isolation, without using an additional photomask, the salicide layer on the drain region is partitioned into two parts. The effect of the local thermal energy occurring to drain junction upon the contact metal of the drain region is eliminated.
摘要翻译：一种静电放电（ESD）器件，其中通过浅沟隔离隔离硅化物层，以便节省一个自杀化合物掩模光掩模。在漏极区域中形成浅沟槽隔离以隔离漏极区域的一部分，使得漏极区域被分成两部分。在漏极区域上形成自对准硅化物层。由于在浅沟槽隔离层上没有形成自对准硅层，所以在不使用额外的光掩模的情况下，将漏极区域上的自对准硅化物层分成两部分。消除了漏极结处漏极区域的接触金属所产生的局部热能的影响。

8. 发明授权

US06184122B2 Method for preventing crosstalk between conductive layers 有权
标题翻译：防止导电层之间串扰的方法
公开(公告)号：US06184122B2
公开(公告)日：2001-02-06
申请号：US09213197
申请日：1998-12-17
申请人： Kuan-Yu Fu , Shiang Huang-Lu
发明人： Kuan-Yu Fu , Shiang Huang-Lu
IPC分类号： H01L214763
CPC分类号： H01L23/5225 , H01L21/76838 , H01L2924/0002 , H01L2924/00
摘要： A method for preventing horizontal and vertical crosstalk between conductive layers forms a dummy conductive layer between conductive layers and between conductive lines within a dielectric layer. The dummy conductive layer does not connect with conductive layers or conductive lines. Because the dummy conductive layer has a shielding effect for conductive layers, the method can reduce the horizontal and vertical crosstalk between conductive layers.
摘要翻译：用于防止导电层之间的水平和垂直串扰的方法在导电层之间和介电层内的导电线之间形成虚设导电层。虚拟导电层不与导电层或导电线连接。由于虚拟导电层对导电层具有屏蔽效果，所以该方法可以减小导电层之间的水平和垂直串扰。

9. 发明授权

US6052269A Electrostatic discharge protection circuit using point discharge 有权
标题翻译：静电放电保护电路采用点放电
公开(公告)号：US6052269A
公开(公告)日：2000-04-18
申请号：US235023
申请日：1999-01-21
申请人： Tien-Hao Tang , Shiang Huang-Lu , Kuan-Yu Fu
发明人： Tien-Hao Tang , Shiang Huang-Lu , Kuan-Yu Fu
IPC分类号： H01L23/60 , H01T4/08 , H02H3/22
CPC分类号： H01L23/60 , H01T4/08 , H01L2924/0002
摘要： A protection circuit using point discharge suitable for use in an integrated circuit, protects circuit from damage by electrostatic discharge. The integrated circuit at least comprises an input/output port, a high voltage line, and a low voltage line. The protection circuit has point discharge structures at two ends of the input/output ports, respectively corresponding to the point discharge structures of the high and low voltage lines, and is suitable for use in all semiconductor fabricating processes.
摘要翻译：一种适用于集成电路的点放电保护电路，可保护电路免受静电放电损坏。集成电路至少包括输入/输出端口，高压线路和低压线路。保护电路在输入/输出端口的两端具有分别对应于高压线和低压线的点放电结构的点放电结构，并且适用于所有半导体制造工艺。

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