会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 4. 发明授权
    • Method of protecting a well at a floating stage
    • 在浮动阶段保护井的方法
    • US06245610B1
    • 2001-06-12
    • US09406517
    • 1999-09-28
    • Mu-Chun WangTzung-Han LeeShiang Huang-Lu
    • Mu-Chun WangTzung-Han LeeShiang Huang-Lu
    • H01L218234
    • H01L21/823475H01L21/76892H01L21/8234H01L21/823493
    • A method of protecting a well at a floating stage. In a first conductive type substrate, a second conductive type well is formed. A first conductive type heavily doped region and a second conductive type heavily doped region are respectively formed in the first conductive type substrate and the second conductive type well. These two heavily doped regions are electrically connected with each at an early stage of fabrication process to provide a protection from being damaged during subsequent plasma process or other processes. While forming a top metal layer of a multi-level interconnect, these two heavily doped regions are disconnected, that is, open to each other, to obtain a better electrical characteristic of the device or the integrated circuit formed on the substrate.
    • 在浮动阶段保护井的方法。 在第一导电型衬底中,形成第二导电型阱。 第一导电型重掺杂区和第二导电型重掺杂区分别形成在第一导电类型衬底和第二导电类型阱中。 这两个重掺杂区域在制造工艺的早期阶段与每一个电连接以提供保护以防止在随后的等离子体处理或其它工艺期间损坏。 当形成多层互连的顶层金属层时,这两个重掺杂区域被断开,即彼此开放,以获得器件或形成在衬底上的集成电路的更好的电特性。
    • 7. 发明授权
    • Wafer acceptance testing method and structure of a test key used in the method
    • 晶圆验收测试方法和方法中使用的测试键的结构
    • US06191602B1
    • 2001-02-20
    • US09220097
    • 1998-12-23
    • Shiang Huang-LuMu-Chun WangKun-Cho Chen
    • Shiang Huang-LuMu-Chun WangKun-Cho Chen
    • G01R3126
    • H01L22/34
    • A wafer acceptance testing (WAT) method with a test key is provided. The test key structure includes a testing structure on a substrate. An inter-layer-dielectric layer covers over the substrate to isolate the testing structure. A grounded metal layer is located on the inter-layer dielectric layer. An interconnecting structure is located on the grounded metal layer. A conductive pad layer and a passivation layer are sequentially located on the interconnecting structure. The testing structure is electrically coupled to the interconnecting structure. The interconnecting structure is also electrically coupled to the conductive pad layer. The grounded metal layer is grounded without any further coupling such that the grounded metal layer is not coupled to the testing structure and the interconnecting structure.
    • 提供了具有测试键的晶片验收测试(WAT)方法。 测试键结构包括在衬底上的测试结构。 层间电介质层覆盖在衬底上以隔离测试结构。 接地的金属层位于层间电介质层上。 互连结构位于接地的金属层上。 导电焊盘层和钝化层依次位于互连结构上。 测试结构电耦合到互连结构。 互连结构也电耦合到导电焊盘层。 接地的金属层没有任何进一步的耦合而接地,使得接地的金属层不耦合到测试结构和互连结构。
    • 9. 发明授权
    • Circuit for evaluating an asysmetric antenna effect
    • 评估非对称天线效应的电路
    • US06229347B1
    • 2001-05-08
    • US09228366
    • 1999-01-11
    • Mu-Chun WangChau-Neng WuShiang Huang-Lu
    • Mu-Chun WangChau-Neng WuShiang Huang-Lu
    • H03K522
    • H03F3/45183H03F2203/45674H03K5/2418H03K5/2481
    • A circuit for evaluating the asymmetric antenna effect of a transistor pair is provided, which can be implemented by using bipolar or complementary metal oxide semiconductor (CMOS) transistors to implement a differential amplifier, with which a pair of transistors Q1 and Q2 having similar characteristics are connected. The transistors Q1 and Q2 have a structure of, for example, one polysilicon layer and three metal layers, in which a second metal layer M2 and a third metal layer M3 are used for signal input, and metal layer M1 close to the gate oxide layer of both the transistors Q1 and Q2 are used to obtain a differential antenna ratio. The differential amplifier comprises transistors Q3 and Q4 serving as an active load, and transistor Q5, which is used for adjusting the voltage gain.
    • 提供了一种用于评估晶体管对的不对称天线效应的电路,其可以通过使用双极或互补金属氧化物半导体(CMOS)晶体管来实现差分放大器来实现,其中具有相似特性的一对晶体管Q1和Q2具有 连接的。 晶体管Q1和Q2具有例如一个多晶硅层和三个金属层的结构,其中第二金属层M2和第三金属层M3用于信号输入,并且金属层M1靠近栅极氧化物层 使用晶体管Q1和Q2两者来获得差分天线比。 差分放大器包括用作有源负载的晶体管Q3和Q4以及用于调整电压增益的晶体管Q5。