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1. 发明授权

US06472744B2 Semiconductor module including a plurality of semiconductor devices detachably 失效
标题翻译：半导体模块可拆卸地包括多个半导体器件
公开(公告)号：US06472744B2
公开(公告)日：2002-10-29
申请号：US09084097
申请日：1998-05-26
申请人： Mitsutaka Sato , Tetsuya Fujisawa , Shigeyuki Maruyama , Junichi Kasai , Toshimi Kawahara , Toshio Hamano , Yoshihiro Kubota , Mitsunada Osawa , Yoshiyuki Yoneda , Kazuto Tsuji , Hirohisa Matsuki
发明人： Mitsutaka Sato , Tetsuya Fujisawa , Shigeyuki Maruyama , Junichi Kasai , Toshimi Kawahara , Toshio Hamano , Yoshihiro Kubota , Mitsunada Osawa , Yoshiyuki Yoneda , Kazuto Tsuji , Hirohisa Matsuki
IPC分类号： H01L2500
CPC分类号： H01L25/105 , H01L2224/48227 , H01L2225/1023 , H01L2924/09701 , H01L2924/1533 , H01L2924/3025 , H01R12/82 , H05K7/1431 , H01L2924/00
摘要： A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.
摘要翻译：半导体模块包括多个半导体器件，每个半导体器件包括承载有单个存储器半导体芯片的电路衬底和用于可分离地保持半导体器件的插座。

2. 发明授权

US06696754B2 Semiconductor module including a plurality of semiconductor devices detachably 失效
标题翻译：半导体模块可拆卸地包括多个半导体器件
公开(公告)号：US06696754B2
公开(公告)日：2004-02-24
申请号：US10214306
申请日：2002-08-08
申请人： Mitsutaka Sato , Tetsuya Fujisawa , Shigeyuki Maruyama , Junichi Kasai , Toshimi Kawahara , Toshio Hamano , Yoshihiro Kubota , Mitsunada Osawa , Yoshiyuki Yoneda , Kazuto Tsuji , Hirohisa Matsuki
发明人： Mitsutaka Sato , Tetsuya Fujisawa , Shigeyuki Maruyama , Junichi Kasai , Toshimi Kawahara , Toshio Hamano , Yoshihiro Kubota , Mitsunada Osawa , Yoshiyuki Yoneda , Kazuto Tsuji , Hirohisa Matsuki
IPC分类号： H01L2334
CPC分类号： H01L25/105 , H01L2224/48227 , H01L2225/1023 , H01L2924/09701 , H01L2924/1533 , H01L2924/3025 , H01R12/82 , H05K7/1431 , H01L2924/00
摘要： A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.
摘要翻译：半导体模块包括多个半导体器件，每个半导体器件包括承载有单个存储器半导体芯片的电路衬底和用于可拆卸地保持半导体器件的插座。

3. 发明授权

US5786985A Semiconductor device and semiconductor device unit 失效
标题翻译：半导体器件和半导体器件单元
公开(公告)号：US5786985A
公开(公告)日：1998-07-28
申请号：US749734
申请日：1996-11-15
申请人： Norio Taniguchi , Junichi Kasai , Kazuto Tsuji , Michio Sono , Masanori Yoshimoto , Katsuhiro Hayashida , Mitsutaka Sato , Hiroshi Yoshimura , Tadashi Uno , Kosuke Otokita , Tetsuya Fujisawa
发明人： Norio Taniguchi , Junichi Kasai , Kazuto Tsuji , Michio Sono , Masanori Yoshimoto , Katsuhiro Hayashida , Mitsutaka Sato , Hiroshi Yoshimura , Tadashi Uno , Kosuke Otokita , Tetsuya Fujisawa
IPC分类号： H01L21/98 , H01L23/495 , H01L25/10 , H05K3/30 , H05K7/20
CPC分类号： H01L25/50 , H01L23/4951 , H01L23/49568 , H01L25/105 , H05K3/301 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73265 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L2225/1094 , Y10S269/903
摘要： A semiconductor device is adapted to be mounted on a circuit substrate in an approximate vertical position. The semiconductor device includes a semiconductor chip, a stage having a first surface and a second surface opposite to the first surface, where the semiconductor chip is mounted on the first surface, a resin package encapsulating the semiconductor chip, where the resin package has upper and lower surfaces and side surfaces, a plurality of leads respectively having one end electrically connected to the semiconductor chip and another end extending downwardly from the lower surface of the resin package, and an upper extension, provided on the stage, extending upwardly from the upper surface of the resin package.
摘要翻译：半导体器件适于以大致垂直位置安装在电路基板上。半导体器件包括半导体芯片，具有第一表面和与第一表面相对的第二表面的阶段，其中半导体芯片安装在第一表面上，树脂封装封装半导体芯片，其中树脂封装具有上部和下表面和侧表面，分别具有电连接到半导体芯片的一端和从树脂封装的下表面向下延伸的另一端的多个引线以及设置在台上的从上表面向上延伸的上延伸部的树脂包装。

4. 发明授权

US06333564B1 Surface mount type semiconductor device and method of producing the same having an interposing layer electrically connecting the semiconductor chip with protrusion electrodes 失效
标题翻译：表面贴装型半导体器件及其制造方法，具有将半导体芯片与突起电极电连接的中间层
公开(公告)号：US06333564B1
公开(公告)日：2001-12-25
申请号：US09336747
申请日：1999-06-21
申请人： Yoshitsugu Katoh , Mitsutaka Sato , Hiroshi Inoue , Seiichi Orimo , Akira Okada , Yoshihiro Kubota , Mitsuo Abe , Toshio Hamano , Yoshitaka Aiba , Tetsuya Fujisawa , Masaaki Seki , Noriaki Shiba
发明人： Yoshitsugu Katoh , Mitsutaka Sato , Hiroshi Inoue , Seiichi Orimo , Akira Okada , Yoshihiro Kubota , Mitsuo Abe , Toshio Hamano , Yoshitaka Aiba , Tetsuya Fujisawa , Masaaki Seki , Noriaki Shiba
IPC分类号： H01L2348
CPC分类号： H01L23/3107 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L2224/32145 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48465 , H01L2224/73215 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/18165 , H01L2924/3511 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2924/00015 , H01L2224/05599
摘要： A semiconductor device and a method of producing the same, the device including a semiconductor chip; balls which function as external connecting terminals; a substrate which electrically connects the semiconductor chip and the balls; a mold resin which seals at least a part of the semiconductor chip; and a connecting portion sealing resin which seals the connecting portion between the substrate and the semiconductor chip. The semiconductor device is mounted onto a printed circuit board via the balls. The thermal expansion coefficient of the mold resin is matched with the thermal expansion coefficient of the printed circuit board. A side surface holding portion for the holding the side surfaces of the semiconductor chip is formed in the mold resin to restrict thermal deformation of the semiconductor chip.
摘要翻译：一种半导体器件及其制造方法，该器件包括半导体芯片; 作为外部连接端子的球; 电连接半导体芯片和滚珠的基板; 模制树脂，其密封半导体芯片的至少一部分; 以及密封基板和半导体芯片之间的连接部分的连接部密封树脂。半导体器件通过球安装到印刷电路板上。模制树脂的热膨胀系数与印刷电路板的热膨胀系数相匹配。在模制树脂中形成用于保持半导体芯片的侧表面的侧表面保持部分，以限制半导体芯片的热变形。

5. 发明授权

US06836025B2 Semiconductor device configured to be surface mountable 有权
标题翻译：配置为可表面安装的半导体器件
公开(公告)号：US06836025B2
公开(公告)日：2004-12-28
申请号：US10448444
申请日：2003-05-30
申请人： Tetsuya Fujisawa , Hirohisa Matsuki , Osamu Igawa , Yoshitaka Aiba , Masamitsu Ikumo , Mitsutaka Sato
发明人： Tetsuya Fujisawa , Hirohisa Matsuki , Osamu Igawa , Yoshitaka Aiba , Masamitsu Ikumo , Mitsutaka Sato
IPC分类号： H01L2348
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/49822 , H01L23/5383 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/48 , H01L24/82 , H01L24/83 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/50 , H01L2223/54426 , H01L2223/5446 , H01L2224/04042 , H01L2224/04105 , H01L2224/05599 , H01L2224/12105 , H01L2224/16145 , H01L2224/24137 , H01L2224/24145 , H01L2224/24155 , H01L2224/24195 , H01L2224/24226 , H01L2224/24265 , H01L2224/274 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48227 , H01L2224/4847 , H01L2224/48471 , H01L2224/73209 , H01L2224/73253 , H01L2224/73267 , H01L2224/83132 , H01L2224/83191 , H01L2224/83192 , H01L2224/83855 , H01L2224/83856 , H01L2224/85399 , H01L2224/92 , H01L2224/92244 , H01L2224/97 , H01L2225/0651 , H01L2225/06524 , H01L2225/06541 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01043 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10253 , H01L2924/12044 , H01L2924/1431 , H01L2924/1434 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19103 , H01L2924/19104 , H01L2924/19107 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： In a semiconductor device circuit formation surfaces of each of a plurality of semiconductor chips can be easily located at even level when the semiconductor chips are arranged side by side so that a process of forming rearrangement wiring is simplified. The semiconductor chips are mounted on a substrate via an adhesive layer in a two-dimensional arrangement. A resin layer is formed on the substrate and located around the semiconductor elements. The resin layer has the same thickness as a thickness of the semiconductor elements. An organic insulating layer is formed over a surface of the resin layer and circuit formation surfaces of the semiconductor elements. A rearrangement wiring layer is formed on the organic insulating layer and electrodes of the semiconductor chips. External connection terminals are electrically connected to the circuit formation surfaces of the semiconductor elements through wiring in the rearrangement wiring layer.
摘要翻译：在半导体器件中，当半导体芯片并排布置时，多个半导体芯片中的每一个的形成表面可以容易地位于均匀的水平，从而简化了布置布线的处理。半导体芯片通过二维布置的粘合剂层安装在基板上。树脂层形成在基板上并位于半导体元件周围。树脂层的厚度与半导体元件的厚度相同。在树脂层的表面和半导体元件的电路形成表面上形成有机绝缘层。在有机绝缘层和半导体芯片的电极上形成重排布线层。外部连接端子通过布线布线层中的布线电连接到半导体元件的电路形成表面。

6. 发明授权

US06784543B2 External connection terminal and semiconductor device 有权
标题翻译：外部连接端子和半导体器件
公开(公告)号：US06784543B2
公开(公告)日：2004-08-31
申请号：US10374965
申请日：2003-02-28
申请人： Hirohisa Matsuki , Yutaka Makino , Masamitsu Ikumo , Mitsutaka Sato , Tetsuya Fujisawa , Yoshitaka Aiba
发明人： Hirohisa Matsuki , Yutaka Makino , Masamitsu Ikumo , Mitsutaka Sato , Tetsuya Fujisawa , Yoshitaka Aiba
IPC分类号： H01L2352
CPC分类号： H01L24/05 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L24/94 , H01L24/96 , H01L2224/02126 , H01L2224/03462 , H01L2224/0401 , H01L2224/04026 , H01L2224/05 , H01L2224/05554 , H01L2224/05568 , H01L2224/05571 , H01L2224/05572 , H01L2224/13006 , H01L2224/13021 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/1358 , H01L2224/16 , H01L2224/274 , H01L2224/814 , H01L2924/0001 , H01L2924/00011 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/13091 , H01L2924/15787 , H01L2924/351 , H05K3/244 , H01L2924/00 , H01L2224/05552 , H01L2224/81805
摘要： A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.
摘要翻译：其中磷镍层，含有比该磷 - 镍层高的磷或硼的富磷镍层，镍锡合金层，富锡锡合金层和锡合金焊料层的结构是在电极上依次形成。因此，可以提高用作电极的金属图案，布线或焊盘和焊料之间的粘合性。

7. 发明授权

US06548898B2 External connection terminal and semiconductor device 有权
标题翻译：外部连接端子和半导体器件
公开(公告)号：US06548898B2
公开(公告)日：2003-04-15
申请号：US09895330
申请日：2001-07-02
申请人： Hirohisa Matsuki , Yutaka Makino , Masamitsu Ikumo , Mitsutaka Sato , Tetsuya Fujisawa , Yoshitaka Aiba
发明人： Hirohisa Matsuki , Yutaka Makino , Masamitsu Ikumo , Mitsutaka Sato , Tetsuya Fujisawa , Yoshitaka Aiba
IPC分类号： H01L2352
CPC分类号： H01L24/05 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L24/94 , H01L24/96 , H01L2224/02126 , H01L2224/03462 , H01L2224/0401 , H01L2224/04026 , H01L2224/05 , H01L2224/05554 , H01L2224/05568 , H01L2224/05571 , H01L2224/05572 , H01L2224/13006 , H01L2224/13021 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/1358 , H01L2224/16 , H01L2224/274 , H01L2224/814 , H01L2924/0001 , H01L2924/00011 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/13091 , H01L2924/15787 , H01L2924/351 , H05K3/244 , H01L2924/00 , H01L2224/05552 , H01L2224/81805
摘要： A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.
摘要翻译：其中磷镍层，含有比该磷 - 镍层高的磷或硼的富磷镍层，镍锡合金层，富锡锡合金层和锡合金焊料层的结构是在电极上依次形成。因此，可以提高用作电极的金属图案，布线或焊盘和焊料之间的粘合性。

8. 发明申请

US20060040532A1 Method of designing circuit board 失效
标题翻译：电路板设计方法
公开(公告)号：US20060040532A1
公开(公告)日：2006-02-23
申请号：US11019156
申请日：2004-12-23
申请人： Kaname Ozawa , Mitsutaka Sato , Tetsuya Fujisawa , Yoshiyuki Yoneda , Ryuji Nomoto , Yoshitaka Aiba
发明人： Kaname Ozawa , Mitsutaka Sato , Tetsuya Fujisawa , Yoshiyuki Yoneda , Ryuji Nomoto , Yoshitaka Aiba
IPC分类号： H01R13/648
CPC分类号： G06F17/5068 , H05K3/0005
摘要： A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.
摘要翻译：一种能够高效率地绘制高密度导线的电路板的设计方法。大鼠巢通过连接电子装置的端子的连接垫和通过线路的外部连接端子形成。然后选择大鼠巢线密度最高的区域，并且在具有最大密度的大鼠巢的区域中设置与导线的路线和尺寸相关的设计规则。然后将导体线放置在具有最高密度的大鼠巢的区域，并且确定导线是否可以放置在具有最大密度的大鼠巢的密度的区域。如果导体线不能铺设，则设计规则和布线的设置，如果可以铺设导线，则通过设定的规则布置其余区域的导体线。

9. 发明授权

US5760471A Semiconductor device having an inner lead extending over a central portion of a semiconductor device sealed in a plastic package and an outer lead exposed to the outside of a side face of the plastic package 失效
标题翻译：半导体器件具有延伸在密封在塑料封装中的半导体器件的中心部分上的内引线和暴露于塑料封装侧表面外部的外引线
公开(公告)号：US5760471A
公开(公告)日：1998-06-02
申请号：US794763
申请日：1997-02-03
申请人： Tetsuya Fujisawa , Mitsutaka Sato , Junichi Kasai , Masataka Mizukoshi , Kousuke Otokita , Hiroshi Yoshimura , Katsuhiro Hayashida , Akira Takashima , Masahiko Ishiguri , Michio Sono
发明人： Tetsuya Fujisawa , Mitsutaka Sato , Junichi Kasai , Masataka Mizukoshi , Kousuke Otokita , Hiroshi Yoshimura , Katsuhiro Hayashida , Akira Takashima , Masahiko Ishiguri , Michio Sono
IPC分类号： H01L23/495 , H01L25/10 , H01L23/48 , H01L23/02 , H01L23/12 , H01L23/50
CPC分类号： H01L23/4951 , H01L23/49551 , H01L25/105 , H01L2224/05647 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/73215 , H01L2224/8547 , H01L2225/1005 , H01L2225/1029 , H01L2225/1041 , H01L2225/107 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01079 , H01L2924/07802 , H01L2924/12042
摘要： A semiconductor device including a semiconductor element, and leads connected with the semiconductor element. Each of the leads includes an outer lead part for being connected externally. The semiconductor device further includes a plastic package sealing the semiconductor element and the leads. In the semiconductor device, the outer lead part is exposed to the outside of a side face of the plastic package, and the plastic package is mounted on any base in a standing form by the side face contacting the base.
摘要翻译：包括半导体元件的半导体器件和与半导体元件连接的引线。每个引线包括用于外部连接的外引线部分。半导体器件还包括密封半导体元件和引线的塑料封装。在半导体器件中，外部引线部分暴露于塑料封装的侧面的外侧，塑料封装通过与底座接触的侧面以立式形式安装在任何基座上。

10. 发明授权

US07251801B2 Method of designing circuit board 失效
标题翻译：电路板设计方法
公开(公告)号：US07251801B2
公开(公告)日：2007-07-31
申请号：US11019156
申请日：2004-12-23
申请人： Kaname Ozawa , Mitsutaka Sato , Tetsuya Fujisawa , Yoshiyuki Yoneda , Ryuji Nomoto , Yoshitaka Aiba
发明人： Kaname Ozawa , Mitsutaka Sato , Tetsuya Fujisawa , Yoshiyuki Yoneda , Ryuji Nomoto , Yoshitaka Aiba
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H05K3/0005
摘要： A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.
摘要翻译：一种能够高效率地绘制高密度导线的电路板的设计方法。大鼠巢通过连接电子装置的端子的连接垫和通过线路的外部连接端子形成。然后选择大鼠巢线密度最高的区域，并且在具有最大密度的大鼠巢的区域中设置与导线的路线和尺寸相关的设计规则。然后将导体线放置在具有最高密度的大鼠巢的区域，并且确定导线是否可以放置在具有最大密度的大鼠巢的密度的区域。如果导体线不能铺设，则设计规则和布线的设置，如果可以铺设导体线，则通过设定的规则布置其余区域的导体线。

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