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1. 发明授权

US06333564B1 Surface mount type semiconductor device and method of producing the same having an interposing layer electrically connecting the semiconductor chip with protrusion electrodes 失效
标题翻译：表面贴装型半导体器件及其制造方法，具有将半导体芯片与突起电极电连接的中间层
公开(公告)号：US06333564B1
公开(公告)日：2001-12-25
申请号：US09336747
申请日：1999-06-21
申请人： Yoshitsugu Katoh , Mitsutaka Sato , Hiroshi Inoue , Seiichi Orimo , Akira Okada , Yoshihiro Kubota , Mitsuo Abe , Toshio Hamano , Yoshitaka Aiba , Tetsuya Fujisawa , Masaaki Seki , Noriaki Shiba
发明人： Yoshitsugu Katoh , Mitsutaka Sato , Hiroshi Inoue , Seiichi Orimo , Akira Okada , Yoshihiro Kubota , Mitsuo Abe , Toshio Hamano , Yoshitaka Aiba , Tetsuya Fujisawa , Masaaki Seki , Noriaki Shiba
IPC分类号： H01L2348
CPC分类号： H01L23/3107 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L2224/32145 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48465 , H01L2224/73215 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/18165 , H01L2924/3511 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2924/00015 , H01L2224/05599
摘要： A semiconductor device and a method of producing the same, the device including a semiconductor chip; balls which function as external connecting terminals; a substrate which electrically connects the semiconductor chip and the balls; a mold resin which seals at least a part of the semiconductor chip; and a connecting portion sealing resin which seals the connecting portion between the substrate and the semiconductor chip. The semiconductor device is mounted onto a printed circuit board via the balls. The thermal expansion coefficient of the mold resin is matched with the thermal expansion coefficient of the printed circuit board. A side surface holding portion for the holding the side surfaces of the semiconductor chip is formed in the mold resin to restrict thermal deformation of the semiconductor chip.
摘要翻译：一种半导体器件及其制造方法，该器件包括半导体芯片; 作为外部连接端子的球; 电连接半导体芯片和滚珠的基板; 模制树脂，其密封半导体芯片的至少一部分; 以及密封基板和半导体芯片之间的连接部分的连接部密封树脂。半导体器件通过球安装到印刷电路板上。模制树脂的热膨胀系数与印刷电路板的热膨胀系数相匹配。在模制树脂中形成用于保持半导体芯片的侧表面的侧表面保持部分，以限制半导体芯片的热变形。

2. 发明授权

US06476503B1 Semiconductor device having columnar electrode and method of manufacturing same 有权
标题翻译：具有柱状电极的半导体装置及其制造方法
公开(公告)号：US06476503B1
公开(公告)日：2002-11-05
申请号：US09606196
申请日：2000-06-29
申请人： Kazuyuki Imamura , Yasunori Fujimoto , Masaaki Seki , Tetsuya Fujisawa , Mitsutaka Sato , Ryuji Nomoto , Junichi Kasai , Yoshitaka Aiba , Noriaki Shiba
发明人： Kazuyuki Imamura , Yasunori Fujimoto , Masaaki Seki , Tetsuya Fujisawa , Mitsutaka Sato , Ryuji Nomoto , Junichi Kasai , Yoshitaka Aiba , Noriaki Shiba
IPC分类号： H01L2348
CPC分类号： H01L21/568 , H01L21/561 , H01L23/3114 , H01L23/3121 , H01L23/49811 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/94 , H01L24/97 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L2224/04105 , H01L2224/05001 , H01L2224/05022 , H01L2224/05568 , H01L2224/11003 , H01L2224/1134 , H01L2224/11822 , H01L2224/12105 , H01L2224/13011 , H01L2224/1308 , H01L2224/13099 , H01L2224/131 , H01L2224/13144 , H01L2224/16145 , H01L2224/274 , H01L2224/45144 , H01L2224/73204 , H01L2224/73253 , H01L2224/73267 , H01L2224/78301 , H01L2224/85205 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06572 , H01L2225/06582 , H01L2225/06586 , H01L2225/1023 , H01L2225/1029 , H01L2225/1058 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/3011 , H01L2924/3511 , H01L2924/00014 , H01L2924/00 , H01L2224/05644 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147
摘要： A semiconductor device including a semiconductor chip sealed with an encapsulating resin. Columnar electrodes are connected to electrode pads of the semiconductor chip, and extend through the encapsulating resin. The columnar electrodes are made from bonding wires and include enlarged outer ends. Solder balls are arranged on the surface of the encapsulating resin and connected to the outer ends of the columnar electrodes. In another example, pin wires are formed by half-cutting bonding wires, bonding one end of each of the bonding wires, and cutting the bonding wires at the half-cut portions.
摘要翻译：一种半导体器件，包括用封装树脂密封的半导体芯片。柱状电极连接到半导体芯片的电极焊盘，并且延伸穿过封装树脂。柱状电极由接合线制成，并且包括扩大的外端。焊球布置在封装树脂的表面上并连接到柱状电极的外端。在另一个例子中，通过半切割接合线，接合每个接合线的一端，以及在半切部分切割接合线来形成引线。

3. 发明授权

US06348728B1 Semiconductor device having a plurality of semiconductor elements interconnected by a redistribution layer 有权
公开(公告)号：US06348728B1
公开(公告)日：2002-02-19
申请号：US09493005
申请日：2000-01-28
申请人： Yoshitaka Aiba , Mitsutaka Sato , Toshio Hamano
发明人： Yoshitaka Aiba , Mitsutaka Sato , Toshio Hamano
IPC分类号： H01L2302
CPC分类号： H01L23/49816 , H01L23/5382 , H01L24/19 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L2224/05001 , H01L2224/05023 , H01L2224/05026 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73217 , H01L2224/73267 , H01L2224/92244 , H01L2224/94 , H01L2224/97 , H01L2225/06524 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2224/83 , H01L2924/00 , H01L2224/05647 , H01L2224/05099
摘要： A plurality of semiconductor chips are incorporated in a one-piece package so as to substantially increase a mounting area of a semiconductor device so that the semiconductor device can be provided with the projection electrodes having a structure which enable the semiconductor device to be mounted by a conventional surface mounting technique. A redistribution layer interconnects and integrally holds the plurality of semiconductor elements. A plurality of projection electrodes are provided on the redistribution layer for surface mounting. The plurality of semiconductor chips are rendered to be different kinds so that the plurality of different kinds of semiconductor chips together provide a complete function. The plurality of semiconductor chips may be rendered to be the same kind so as to reduce a mounting area of the semiconductor chips as a whole.

4. 发明授权

US06627479B2 Semiconductor device having a plurality of semiconductor elements interconnected by a redistribution layer 有权
公开(公告)号：US06627479B2
公开(公告)日：2003-09-30
申请号：US10022572
申请日：2001-12-20
申请人： Yoshitaka Aiba , Mitsutaka Sato , Toshio Hamano
发明人： Yoshitaka Aiba , Mitsutaka Sato , Toshio Hamano
IPC分类号： H01L2144
CPC分类号： H01L23/49816 , H01L23/5382 , H01L24/19 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L2224/05001 , H01L2224/05023 , H01L2224/05026 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73217 , H01L2224/73267 , H01L2224/92244 , H01L2224/94 , H01L2224/97 , H01L2225/06524 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2224/83 , H01L2924/00 , H01L2224/05647 , H01L2224/05099
摘要： A plurality of semiconductor chips are incorporated in a one-piece package so as to substantially increase a mounting area of a semiconductor device so that the semiconductor device can be provided with the projection electrodes having a structure which enable the semiconductor device to be mounted by a conventional surface mounting technique. A redistribution layer interconnects and integrally holds the plurality of semiconductor elements. A plurality of projection electrodes are provided on the redistribution layer for surface mounting. The plurality of semiconductor chips are rendered to be different kinds so that the plurality of different kinds of semiconductor chips together provide a complete function. The plurality of semiconductor chips may be rendered to be the same kind so as to reduce a mounting area of the semiconductor chips as a whole.

5. 发明申请

US20060040532A1 Method of designing circuit board 失效
标题翻译：电路板设计方法
公开(公告)号：US20060040532A1
公开(公告)日：2006-02-23
申请号：US11019156
申请日：2004-12-23
申请人： Kaname Ozawa , Mitsutaka Sato , Tetsuya Fujisawa , Yoshiyuki Yoneda , Ryuji Nomoto , Yoshitaka Aiba
发明人： Kaname Ozawa , Mitsutaka Sato , Tetsuya Fujisawa , Yoshiyuki Yoneda , Ryuji Nomoto , Yoshitaka Aiba
IPC分类号： H01R13/648
CPC分类号： G06F17/5068 , H05K3/0005
摘要： A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.
摘要翻译：一种能够高效率地绘制高密度导线的电路板的设计方法。大鼠巢通过连接电子装置的端子的连接垫和通过线路的外部连接端子形成。然后选择大鼠巢线密度最高的区域，并且在具有最大密度的大鼠巢的区域中设置与导线的路线和尺寸相关的设计规则。然后将导体线放置在具有最高密度的大鼠巢的区域，并且确定导线是否可以放置在具有最大密度的大鼠巢的密度的区域。如果导体线不能铺设，则设计规则和布线的设置，如果可以铺设导线，则通过设定的规则布置其余区域的导体线。

6. 发明授权

US06836025B2 Semiconductor device configured to be surface mountable 有权
标题翻译：配置为可表面安装的半导体器件
公开(公告)号：US06836025B2
公开(公告)日：2004-12-28
申请号：US10448444
申请日：2003-05-30
申请人： Tetsuya Fujisawa , Hirohisa Matsuki , Osamu Igawa , Yoshitaka Aiba , Masamitsu Ikumo , Mitsutaka Sato
发明人： Tetsuya Fujisawa , Hirohisa Matsuki , Osamu Igawa , Yoshitaka Aiba , Masamitsu Ikumo , Mitsutaka Sato
IPC分类号： H01L2348
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/49822 , H01L23/5383 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/48 , H01L24/82 , H01L24/83 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/50 , H01L2223/54426 , H01L2223/5446 , H01L2224/04042 , H01L2224/04105 , H01L2224/05599 , H01L2224/12105 , H01L2224/16145 , H01L2224/24137 , H01L2224/24145 , H01L2224/24155 , H01L2224/24195 , H01L2224/24226 , H01L2224/24265 , H01L2224/274 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48227 , H01L2224/4847 , H01L2224/48471 , H01L2224/73209 , H01L2224/73253 , H01L2224/73267 , H01L2224/83132 , H01L2224/83191 , H01L2224/83192 , H01L2224/83855 , H01L2224/83856 , H01L2224/85399 , H01L2224/92 , H01L2224/92244 , H01L2224/97 , H01L2225/0651 , H01L2225/06524 , H01L2225/06541 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01043 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10253 , H01L2924/12044 , H01L2924/1431 , H01L2924/1434 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19103 , H01L2924/19104 , H01L2924/19107 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： In a semiconductor device circuit formation surfaces of each of a plurality of semiconductor chips can be easily located at even level when the semiconductor chips are arranged side by side so that a process of forming rearrangement wiring is simplified. The semiconductor chips are mounted on a substrate via an adhesive layer in a two-dimensional arrangement. A resin layer is formed on the substrate and located around the semiconductor elements. The resin layer has the same thickness as a thickness of the semiconductor elements. An organic insulating layer is formed over a surface of the resin layer and circuit formation surfaces of the semiconductor elements. A rearrangement wiring layer is formed on the organic insulating layer and electrodes of the semiconductor chips. External connection terminals are electrically connected to the circuit formation surfaces of the semiconductor elements through wiring in the rearrangement wiring layer.
摘要翻译：在半导体器件中，当半导体芯片并排布置时，多个半导体芯片中的每一个的形成表面可以容易地位于均匀的水平，从而简化了布置布线的处理。半导体芯片通过二维布置的粘合剂层安装在基板上。树脂层形成在基板上并位于半导体元件周围。树脂层的厚度与半导体元件的厚度相同。在树脂层的表面和半导体元件的电路形成表面上形成有机绝缘层。在有机绝缘层和半导体芯片的电极上形成重排布线层。外部连接端子通过布线布线层中的布线电连接到半导体元件的电路形成表面。

7. 发明授权

US07251801B2 Method of designing circuit board 失效
标题翻译：电路板设计方法
公开(公告)号：US07251801B2
公开(公告)日：2007-07-31
申请号：US11019156
申请日：2004-12-23
申请人： Kaname Ozawa , Mitsutaka Sato , Tetsuya Fujisawa , Yoshiyuki Yoneda , Ryuji Nomoto , Yoshitaka Aiba
发明人： Kaname Ozawa , Mitsutaka Sato , Tetsuya Fujisawa , Yoshiyuki Yoneda , Ryuji Nomoto , Yoshitaka Aiba
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H05K3/0005
摘要： A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.
摘要翻译：一种能够高效率地绘制高密度导线的电路板的设计方法。大鼠巢通过连接电子装置的端子的连接垫和通过线路的外部连接端子形成。然后选择大鼠巢线密度最高的区域，并且在具有最大密度的大鼠巢的区域中设置与导线的路线和尺寸相关的设计规则。然后将导体线放置在具有最高密度的大鼠巢的区域，并且确定导线是否可以放置在具有最大密度的大鼠巢的密度的区域。如果导体线不能铺设，则设计规则和布线的设置，如果可以铺设导体线，则通过设定的规则布置其余区域的导体线。

8. 发明授权

US06784543B2 External connection terminal and semiconductor device 有权
标题翻译：外部连接端子和半导体器件
公开(公告)号：US06784543B2
公开(公告)日：2004-08-31
申请号：US10374965
申请日：2003-02-28
申请人： Hirohisa Matsuki , Yutaka Makino , Masamitsu Ikumo , Mitsutaka Sato , Tetsuya Fujisawa , Yoshitaka Aiba
发明人： Hirohisa Matsuki , Yutaka Makino , Masamitsu Ikumo , Mitsutaka Sato , Tetsuya Fujisawa , Yoshitaka Aiba
IPC分类号： H01L2352
CPC分类号： H01L24/05 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L24/94 , H01L24/96 , H01L2224/02126 , H01L2224/03462 , H01L2224/0401 , H01L2224/04026 , H01L2224/05 , H01L2224/05554 , H01L2224/05568 , H01L2224/05571 , H01L2224/05572 , H01L2224/13006 , H01L2224/13021 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/1358 , H01L2224/16 , H01L2224/274 , H01L2224/814 , H01L2924/0001 , H01L2924/00011 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/13091 , H01L2924/15787 , H01L2924/351 , H05K3/244 , H01L2924/00 , H01L2224/05552 , H01L2224/81805
摘要： A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.
摘要翻译：其中磷镍层，含有比该磷 - 镍层高的磷或硼的富磷镍层，镍锡合金层，富锡锡合金层和锡合金焊料层的结构是在电极上依次形成。因此，可以提高用作电极的金属图案，布线或焊盘和焊料之间的粘合性。

9. 发明授权

US06548898B2 External connection terminal and semiconductor device 有权
标题翻译：外部连接端子和半导体器件
公开(公告)号：US06548898B2
公开(公告)日：2003-04-15
申请号：US09895330
申请日：2001-07-02
申请人： Hirohisa Matsuki , Yutaka Makino , Masamitsu Ikumo , Mitsutaka Sato , Tetsuya Fujisawa , Yoshitaka Aiba
发明人： Hirohisa Matsuki , Yutaka Makino , Masamitsu Ikumo , Mitsutaka Sato , Tetsuya Fujisawa , Yoshitaka Aiba
IPC分类号： H01L2352
CPC分类号： H01L24/05 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L24/94 , H01L24/96 , H01L2224/02126 , H01L2224/03462 , H01L2224/0401 , H01L2224/04026 , H01L2224/05 , H01L2224/05554 , H01L2224/05568 , H01L2224/05571 , H01L2224/05572 , H01L2224/13006 , H01L2224/13021 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/1358 , H01L2224/16 , H01L2224/274 , H01L2224/814 , H01L2924/0001 , H01L2924/00011 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/13091 , H01L2924/15787 , H01L2924/351 , H05K3/244 , H01L2924/00 , H01L2224/05552 , H01L2224/81805
摘要： A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.
摘要翻译：其中磷镍层，含有比该磷 - 镍层高的磷或硼的富磷镍层，镍锡合金层，富锡锡合金层和锡合金焊料层的结构是在电极上依次形成。因此，可以提高用作电极的金属图案，布线或焊盘和焊料之间的粘合性。

10. 发明授权

US07084513B2 Semiconductor device having a plurality of semiconductor chips and method for manufacturing the same 失效
标题翻译：具有多个半导体芯片的半导体装置及其制造方法
公开(公告)号：US07084513B2
公开(公告)日：2006-08-01
申请号：US10860657
申请日：2004-06-04
申请人： Hirohisa Matsuki , Yoshitaka Aiba , Mitsutaka Sato , Tadahiro Okamato
发明人： Hirohisa Matsuki , Yoshitaka Aiba , Mitsutaka Sato , Tadahiro Okamato
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/02 , H01L23/34
CPC分类号： H01L24/11 , H01L23/3114 , H01L23/5389 , H01L24/16 , H01L24/24 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/82 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/12105 , H01L2224/13099 , H01L2224/16145 , H01L2224/16225 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/73209 , H01L2224/73217 , H01L2224/73265 , H01L2224/73267 , H01L2224/82039 , H01L2224/92 , H01L2224/92244 , H01L2224/94 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06586 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12041 , H01L2924/12042 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/00014 , H01L2224/82 , H01L2224/48227 , H01L2924/00 , H01L2924/00012 , H01L2924/00011 , H01L2224/85 , H01L2224/83 , H01L2224/81 , H01L2224/05124 , H01L2224/05147 , H01L2224/03
摘要： A semiconductor device includes a first semiconductor chip (5) having a first terminal (7) on one surface, a second semiconductor chip (1a) which is larger than the first semiconductor chip (5) and on which the first semiconductor chip (5) is stacked and which has a second terminal (3) on one surface, an insulating layer (10) formed on a second semiconductor chip (1a) to cover the first semiconductor chip (5), a plurality of holes (10a) formed in the insulating layer (10) on at least a peripheral area of the first semiconductor chip (5), a via (11a) formed like a film on inner peripheral surfaces and bottom surfaces of the holes (10a) and connected electrically to the second terminal (3) of the second semiconductor chip (1a), a wiring pattern (11b) formed on an upper surface of the insulating layer (10), and an external terminal (14) formed on the wiring pattern (11b).
摘要翻译：半导体器件包括在一个表面上具有第一端子（7）的第一半导体芯片（5），大于第一半导体芯片（5）的第二半导体芯片（1a），并且第一半导体芯片（5）），并且在一个表面上具有第二端子（3），形成在第二半导体芯片（1a）上以覆盖第一半导体芯片（5）的绝缘层（10），多个孔（10a）形成在第一半导体芯片（5）的至少周边区域上的绝缘层（10）中，在孔（10a）的内周表面和底表面上形成为类似于膜的通孔（11a），并且电连接到第二半导体芯片（1a）的第二端子（3），形成在绝缘层（10）的上表面上的布线图案（11b）和形成在布线图案上的外部端子（14） 11 b）。

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