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1. 发明授权

US6049845A System and method for providing speculative arbitration for transferring data 失效
标题翻译：提供传输数据的投机仲裁的系统和方法
公开(公告)号：US6049845A
公开(公告)日：2000-04-11
申请号：US964630
申请日：1997-11-05
申请人： Mitchell A. Bauman , Joseph S. Schibinger , Donald R. Kalvestrand , Douglas E. Morrissey
发明人： Mitchell A. Bauman , Joseph S. Schibinger , Donald R. Kalvestrand , Douglas E. Morrissey
IPC分类号： G06F13/18 , G06F12/08 , G06F13/16 , G06F13/362 , G06F15/167 , G06F13/00
CPC分类号： G06F13/1605
摘要： A system and method for optimizing the amount of time it takes for a requestor (device) to receive data from a memory storage unit in a multi-requestor bus environment. The present invention provides a unidirectional response signal, referred to as an early warning signal, sent from a memory storage unit to a device, sometime after that device has executed a fetch request for data, to alert the device that the data is forthcoming. This early warning signal allows the device to arbitrate for the data bus so that when the data arrives, the device will have exclusive ownership of the data bus to accept the data immediately. The present invention comprises a main memory, a cache memory, one or more processor modules, one or more I/O modules, and an early warning bus. The cache memory is connected to the main memory via an interface bus. The processor modules are connected to the cache memory via a processor interface bus. The I/O modules are connected to the main memory via an I/O interface bus. Both the processor modules and the I/O modules include means for requesting a data unit from the main memory. The early warning bus is connected between the main memory, the cache memory, and the I/O module.
摘要翻译：一种用于优化请求者（设备）从多请求者总线环境中的存储器存储单元接收数据所需的时间量的系统和方法。本发明提供了一种从存储器存储单元发送到设备的称为早期警告信号的单向响应信号，该设备在该设备执行了对数据的取出请求之后的某个时刻向该设备通知数据即将到来。该预警信号允许设备对数据总线进行仲裁，以便当数据到达时，设备将具有数据总线的独占所有权以立即接受数据。本发明包括主存储器，高速缓冲存储器，一个或多个处理器模块，一个或多个I / O模块和预警总线。高速缓存通过接口总线连接到主存储器。处理器模块通过处理器接口总线连接到高速缓冲存储器。 I / O模块通过I / O接口总线连接到主存储器。处理器模块和I / O模块都包括用于从主存储器请求数据单元的装置。预警总线连接在主存储器，高速缓冲存储器和I / O模块之间。

2. 发明授权

US06477620B1 Cache-level return data by-pass system for a hierarchical memory 有权
标题翻译：用于分层存储器的缓存级返回数据旁路系统
公开(公告)号：US06477620B1
公开(公告)日：2002-11-05
申请号：US09467190
申请日：1999-12-20
申请人： Mitchell A. Bauman , Roger L. Gilbertson , Donald R. Kalvestrand , Joseph S. Schibinger , Daniel S. Tokoly
发明人： Mitchell A. Bauman , Roger L. Gilbertson , Donald R. Kalvestrand , Joseph S. Schibinger , Daniel S. Tokoly
IPC分类号： G06F1208
CPC分类号： G06F12/0813 , G06F12/0811
摘要： A data by-pass system for a hierarchical, multi-level, memory is disclosed. The by-pass system provides by-pass interfaces between storage devices located at predetermined levels within the memory hierarchy. The hierarchical memory system of the preferred embodiment includes a main memory coupled to multiple first storage devices that each stores addressable portions of data signals retrieved from the main memory. To facilitate a more efficient transfer of data between the various storage devices in the memory system, at least one by-pass interface coupling associated ones of the first storage devices is provided. Data retrieved from a target one of the first storage devices in response to a main memory request can be routed to a different requesting one of the first storage devices via the by-pass system without requiring the use of the main memory data interfaces.
摘要翻译：公开了一种用于分级，多级存储器的数据旁路系统。旁路系统在位于存储器层级内的预定级别的存储设备之间提供旁路接口。优选实施例的分级存储器系统包括耦合到多个第一存储设备的主存储器，每个存储器件存储从主存储器检索的数据信号的可寻址部分。为了便于在存储器系统中的各种存储设备之间更有效地传输数据，提供了耦合相关联的第一存储设备的至少一个旁路接口。可以响应于主存储器请求从第一存储设备中的目标一个检索的数据经由旁路系统路由到第一存储设备中的不同请求的一个，而不需要使用主存储器数据接口。

3. 发明授权

US06457101B1 System and method for providing the speculative return of cached data within a hierarchical memory system 有权
标题翻译：用于在分层存储器系统内提供缓存数据的推测返回的系统和方法
公开(公告)号：US06457101B1
公开(公告)日：2002-09-24
申请号：US09468050
申请日：1999-12-20
申请人： Mitchell A. Bauman , Roger L. Gilbertson , Donald R. Kalvestrand , Joseph S. Schibinger , Daniel S. Tokoly
发明人： Mitchell A. Bauman , Roger L. Gilbertson , Donald R. Kalvestrand , Joseph S. Schibinger , Daniel S. Tokoly
IPC分类号： G06F1208
CPC分类号： G06F12/0817 , G06F12/0811 , G06F12/0862 , G06F2212/507
摘要： A hierarchical memory structure includes a directory-based main memory coupled to multiple first storage devices, each to store data signals retrieved from the main memory. Ones of the first storage devices are further respectively coupled to second storage devices, each to store data signals retrieved from the respectively coupled first storage devices. Fetch requests to retrieve data signals are issued by ones of the storage devices to the main memory. In response, the main memory determines where the most recent data copy resides, and issues a return request, if necessary to retrieve that copy for the requesting storage device. A speculative return generation logic circuit is coupled to at least two of the first storage devices to intercept the fetch requests. In response to an intercepted request, the speculative return generation logic circuit generates a speculative return request directly to one or more of the other coupled first storage devices. This speculative return request causes any updated copies of the requested data signals that may be stored at a lower level in the hierarchical memory, to be transferred to the first storage device. If a return request for the data is then issued by the main memory in response to the fetch request, the requested data signals are resident in a first storage device, and are readily available to the main memory.
摘要翻译：分层存储器结构包括耦合到多个第一存储设备的基于目录的主存储器，每个存储器件用于存储从主存储器检索的数据信号。第一存储设备的另外分别耦合到第二存储设备，每个存储设备存储从分别耦合的第一存储设备检索的数据信号。获取数据信号的请求由存储设备中的一个发送到主存储器。作为响应，主存储器确定最近的数据副本所在的位置，并且如果需要检索请求存储设备的该副本，则发出返回请求。推测返回生成逻辑电路耦合到至少两个第一存储设备以拦截提取请求。响应于被截取的请求，推测返回产生逻辑电路直接向一个或多个其它耦合的第一存储设备产生推测返回请求。该推测返回请求使得可以存储在分层存储器中的较低级的所请求的数据信号的任何更新的副本被传送到第一存储设备。如果主存储器响应于提取请求发出对数据的返回请求，则所请求的数据信号驻留在第一存储设备中，并且容易对主存储器可用。

4. 发明授权

US07213109B1 System and method for providing speculative ownership of cached data based on history tracking 有权
标题翻译：基于历史跟踪提供缓存数据的投机所有权的系统和方法
公开(公告)号：US07213109B1
公开(公告)日：2007-05-01
申请号：US10304919
申请日：2002-11-26
申请人： Mitchell A. Bauman , Joseph S. Schibinger
发明人： Mitchell A. Bauman , Joseph S. Schibinger
IPC分类号： G06F13/00 , G06F12/00 , G06F3/00 , G06F13/18
CPC分类号： G06F12/0817 , G06F2212/507
摘要： A system and method for managing memory data is provided. Data stored within a main memory may be requested by multiple requesters that may include one or more cache memories. When the data is provided by the main memory to a requester, it will be provided in a state that is based on the way the data was recently used by the requesters. For example, if a pattern of read-only usage has been established for the data, the data will be returned to a requester in a shared state. If data that was provided in a shared state must be updated such that the requester is required return to main memory to obtain read/write privileges, the main memory will thereafter provide the data in an exclusive state that allows write operations to be completed. This will continue until a pattern of read-only usage is again established.
摘要翻译：提供了一种用于管理存储器数据的系统和方法。存储在主存储器内的数据可以由可能包括一个或多个高速缓存存储器的多个请求者请求。当主存储器向请求者提供数据时，将以基于请求者最近使用数据的方式提供数据。例如，如果为数据建立了只读使用模式，则数据将以共享状态返回给请求者。如果必须更新在共享状态下提供的数据，以便需要请求者返回到主存储器以获得读/写权限，则主存储器此后将以允许写操作完成的独占状态提供数据。这将继续，直到再次建立只读使用模式。

5. 发明授权

US06389515B1 System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations 有权
标题翻译：用于避免死锁的系统和方法，利用分裂锁定操作在非原子操作期间提供对存储器的独占访问
公开(公告)号：US06389515B1
公开(公告)日：2002-05-14
申请号：US09597621
申请日：2000-06-20
申请人： Joseph S. Schibinger , Douglas E. Morrissey
发明人： Joseph S. Schibinger , Douglas E. Morrissey
IPC分类号： G06F1314
CPC分类号： G06F9/524 , G06F12/0817
摘要： A system and method are provided to avoid deadlocks when performing non-atomic operations on data in a shared memory accessed by multiple processors, whereby the shared memory sends messages to implement a split lock. Via the messages, the requesting processor is granted exclusive access to the shared memory so that no other processor may access the same data until after the non-atomic operation has completed. The messages used to avoid the deadlock include a split lock request, a lock message, a grant message, a gone idle message and a release idle message. By using the above messages, the system accepts requests from multiple processors for exclusive access to memory, orders all of the requests, and awards exclusive access to the first processor to make a request. The system can include a cache memory, associated with a requesting processor, which sends a lock request to the main memory in response to a split lock request from a requesting processor.
摘要翻译：提供了一种系统和方法，以便在由多个处理器访问的共享存储器中的数据执行非原子操作时避免死锁，由此共享存储器发送消息以实现拆分锁。通过消息，请求处理器被授予对共享存储器的独占访问，使得在非原子操作完成之后，没有其他处理器可以访问相同的数据。用于避免死锁的消息包括拆分锁定请求，锁定消息，授权消息，未完成的空闲消息和释放空闲消息。通过使用上述消息，系统接受来自多个处理器的请求，用于对存储器的独占访问，订购所有请求，并授予对第一处理器的独占访问以进行请求。该系统可以包括与请求处理器相关联的高速缓冲存储器，其响应于来自请求处理器的分离锁定请求向主存储器发送锁定请求。

6. 发明授权

US6092156A System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations 失效
标题翻译：用于避免死锁的系统和方法，利用分裂锁定操作在非原子操作期间提供对存储器的独占访问
公开(公告)号：US6092156A
公开(公告)日：2000-07-18
申请号：US964623
申请日：1997-11-05
申请人： Joseph S. Schibinger , Douglas E. Morrissey
发明人： Joseph S. Schibinger , Douglas E. Morrissey
IPC分类号： G06F12/08 , G06F9/46 , G06F9/52 , G06F12/00 , G06F15/167 , G06F13/364
CPC分类号： G06F9/524 , G06F12/0817
摘要： A system and method for avoiding deadlocks when performing non-atomic operations on data in a shared memory accessed by multiple processors that sends messages to implement a split lock. Via the messages, the requesting processor is granted exclusive access to the shared memory so that no other processor may access the same data until after the non-atomic operation has completed. The messages used to avoid the deadlock include a split lock request, a lock message, a grant message, a gone idle message and a release idle message. By using the above messages, the system and method of the present invention accepts requests from multiple processors for exclusive access to memory, orders all of the requests, and awards exclusive access to the first processor to make a request. The system can include a cache memory, associated with a requesting processor, which sends a lock request to the main memory in response to a split lock request from a requesting processor.
摘要翻译：一种系统和方法，用于在由发送消息以实现分裂锁的多个处理器访问的共享存储器中的数据执行非原子操作时避免死锁。通过消息，请求处理器被授予对共享存储器的独占访问，使得在非原子操作完成之后，没有其他处理器可以访问相同的数据。用于避免死锁的消息包括拆分锁定请求，锁定消息，授权消息，未完成的空闲消息和释放空闲消息。通过使用上述消息，本发明的系统和方法接受来自多个处理器的请求，用于对存储器的独占访问，对所有请求进行排序，并授予对第一处理器的独占访问以进行请求。该系统可以包括与请求处理器相关联的高速缓冲存储器，其响应于来自请求处理器的分离锁定请求向主存储器发送锁定请求。

7. 发明授权

US5280615A Out of order job processing method and apparatus 失效
标题翻译：乱序工作处理方法和装置
公开(公告)号：US5280615A
公开(公告)日：1994-01-18
申请号：US787676
申请日：1991-11-04
申请人： Craig R. Church , Joseph S. Schibinger , Andrew T. Jennings
发明人： Craig R. Church , Joseph S. Schibinger , Andrew T. Jennings
IPC分类号： G06F9/38 , G06F9/46 , G06F9/06
CPC分类号： G06F9/3804 , G06F9/384 , G06F9/3851 , G06F9/3853 , G06F9/3863
摘要： A computer system executes steps to provide results in an order different from an intended order. Instructions are concatenated into a plurality of jobs. Different invocations of a variable within the computer instruction stream may be assigned respectively different storage locations and each storage location may correspond to a different job. When all the storage locations associated with a particular job indicate available resources (e.g. valid variable input), the job may be executed. A mechanism allows for job re-execution, if needed, due to interrupt or error.
摘要翻译：计算机系统执行步骤以提供不同于预期订单的顺序的结果。指令被连接成多个作业。计算机指令流中的变量的不同调用可以被分配不同的存储位置，并且每个存储位置可以对应于不同的作业。当与特定作业相关联的所有存储位置指示可用资源（例如有效变量输入）时，可以执行作业。如果需要，机制允许由于中断或错误而重新执行作业。

8. 发明授权

US4466061A Concurrent processing elements for using dependency free code 失效
标题翻译：并行处理元素使用依赖关系的代码
公开(公告)号：US4466061A
公开(公告)日：1984-08-14
申请号：US386336
申请日：1982-06-08
申请人： Alfred J. DeSantis , Joseph S. Schibinger
发明人： Alfred J. DeSantis , Joseph S. Schibinger
IPC分类号： G06F9/48 , G06F15/16 , G06F9/06
CPC分类号： G06F9/4881
摘要： A data processor having a plurality of processing elements and a mechanism to receive strings of object code, form them into higher level tasks and to determine sequences of such tasks which are logically independent so that they may be separately and concurrently executed by the plurality of processing elements. The mechanism makes all memory accesses required by the various tasks and stores those tasks along with corresponding pointers or references to local memory in which the various data items have now been stored. The mechanism employs a symbol translation table in which the tasks are stored in forms of queues along with symbols representing the various references or pointers to local memory. In this manner, various data items can be assigned different symbols or symbolic names for use with different tasks thus further limiting dependency between various tasks and controlling data changes.
摘要翻译：具有多个处理元件的数据处理器和用于接收目标代码串的机制，将它们形成更高级别的任务并且确定逻辑上独立的这些任务的序列，使得它们可以被多个处理单独并行地执行元素。该机制使得各种任务所需的所有存储器访问和存储这些任务以及相应的指针或对本地存储器的引用，其中现在已经存储了各种数据项。该机制采用符号转换表，其中任务以队列形式存储，以及表示各种引用或指向本地存储器的指针的符号。以这种方式，可以为各种数据项分配不同的符号或符号名称以用于不同的任务，从而进一步限制各种任务之间的依赖性并控制数据改变。

9. 发明授权

US5696936A Low latency message processor interface using memory mapped Read/Write Windows 失效
标题翻译：低延迟消息处理器接口使用内存映射读/写Windows
公开(公告)号：US5696936A
公开(公告)日：1997-12-09
申请号：US428054
申请日：1995-04-25
申请人： Craig R. Church , Duane J. McCrory , Joseph S. Schibinger , Laurence P. Flora
发明人： Craig R. Church , Duane J. McCrory , Joseph S. Schibinger , Laurence P. Flora
IPC分类号： G06F12/08
CPC分类号： G06F12/0879 , G06F12/0897
摘要： A low latency software and hardware interface between a microprocessor and Network Interface Unit is disclosed. The Network Interface Unit interfaces to the microprocessor's Level 2 cache interface, which provides burst transfers of cache lines between the microprocessor and Network Interface Unit. The Network Interface Unit is memory mapped into the microprocessor's address space. Two memory mapped cache lines are used to write commands to the Network Interface Unit's Write Window and another two cache lines are used to read results of the commands from the Network Interface Unit's Read Window. The Write Window is a three port register file. Data is written into one write port and read simultaneously from two read ports. One read port is used during read operations to the Write Window while the other is used during command execution to move data to the Internal Structures block. The Read Window is a 2-1 multiplexor that is 128 bits wide. On a read operation data may be selected from the Write Window or the Internal Structures.
摘要翻译：公开了微处理器和网络接口单元之间的低延迟软件和硬件接口。网络接口单元连接到微处理器的2级缓存接口，该接口在微处理器和网络接口单元之间提供高速缓存线的突发传输。网络接口单元被存储器映射到微处理器的地址空间。两个内存映射缓存行用于将命令写入网络接口单元的写入窗口，另外两条缓存行用于从网络接口单元的“读取窗口”读取命令的结果。写入窗口是一个三端口寄存器文件。将数据写入一个写入端口，并从两个读取端口同时读取。在写入窗口的读取操作期间使用一个读取端口，而在命令执行期间使用另一个读取端口将数据移动到“内部结构”块。读窗口是128位宽的2-1多路复用器。在读取操作数据可以从写入窗口或内部结构中选择。

10. 发明授权

US4819150A Array for simulating computer functions for large computer systems 失效
标题翻译：用于模拟大型计算机系统的计算机功能的阵列
公开(公告)号：US4819150A
公开(公告)日：1989-04-04
申请号：US720573
申请日：1985-04-05
申请人： Andrew T. Jennings , Joseph S. Schibinger , Ronald J. Kalemba
发明人： Andrew T. Jennings , Joseph S. Schibinger , Ronald J. Kalemba
IPC分类号： G06F11/25 , G06F17/50 , G06F19/00 , G06F1/00
CPC分类号： G06F17/5022
摘要： An array of various types of processors for the purpose of simulating computer functions for large computer systems. These functions may vary from simple AND, OR and other functions to large arithmetic logic units and even random access memories. The simulation array is a tree-type array where the leaves of the tree are the actual logic simulation processors with the other processors serving as nodes which route change of value notices among the various logic simulation processors.
摘要翻译：用于模拟大型计算机系统的计算机功能的各种类型的处理器阵列。这些功能可以从简单的AND，OR和其他功能变化到大的算术逻辑单元，甚至是随机存取存储器。仿真阵列是一种树型阵列，其中树的叶是实际的逻辑模拟处理器，其他处理器用作各种逻辑模拟处理器之间的价值通知变化的节点。

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