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1. 发明授权

US07343515B1 System and method for performing error recovery in a data processing system having multiple processing partitions 有权
标题翻译：用于在具有多个处理分区的数据处理系统中执行错误恢复的系统和方法
公开(公告)号：US07343515B1
公开(公告)日：2008-03-11
申请号：US10954842
申请日：2004-09-30
申请人： R. Lee Gilbertson , Mitchell A. Bauman , Penny L. Svenkeson
发明人： R. Lee Gilbertson , Mitchell A. Bauman , Penny L. Svenkeson
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0712 , G06F11/0724
摘要： A system and method is disclosed for performing error recovery in a data processing system that supports multiple processing partitions. One or more processors and I/O modules, as well as a portion of the address space of a main memory, is allocated to each partition. In this type of configuration, requests generated by units of multiple partitions are processed by the same queue and state logic of the main memory. When a failure occurs within one processing partition, one or more units are identified as being directly affected by the fault. All requests and responses from, and to, the affected units, as well as any logical residue of these requests and responses are removed from the shared memory queue and state logic in a manner that allows the other partition to continue issuing requests and responses to the memory in a normal manner that does not involve recovery operations.
摘要翻译：公开了一种用于在支持多个处理分区的数据处理系统中执行错误恢复的系统和方法。一个或多个处理器和I / O模块以及主存储器的地址空间的一部分被分配给每个分区。在这种类型的配置中，由多个分区的单元生成的请求由主存储器的相同队列和状态逻辑处理。当在一个处理分区内发生故障时，一个或多个单元被识别为直接受故障影响。受影响单位的所有请求和响应以及这些请求和响应的任何逻辑残差都以共享内存队列和状态逻辑的方式被删除，从而允许其他分区继续发出请求和响应记忆以不涉及恢复操作的正常方式。

2. 发明授权

US07167955B1 System and method for testing and initializing directory store memory 有权
标题翻译：用于测试和初始化目录存储器的系统和方法
公开(公告)号：US07167955B1
公开(公告)日：2007-01-23
申请号：US10745372
申请日：2003-12-23
申请人： Justin S. Neils , John S. Jensen , Mitchell A. Bauman , Eugene A. Rodi , Bart E. Reigstad
发明人： Justin S. Neils , John S. Jensen , Mitchell A. Bauman , Eugene A. Rodi , Bart E. Reigstad
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F11/1008 , G06F2212/1032
摘要： A system and method for testing and/or initializing a Directory Store in a directory-based coherent memory. In one illustrative embodiment, the directory-based coherent memory includes a Main Store for storing a number of data entries, a Directory Store for storing the directory state for at least some of the data entries in the Main Store, and a next state block for determining a next directory state for a requested data entry in response to a memory request. To provide access to the Directory Store, and in one illustrative embodiment, a selector is provided for selecting either the next directory state value provided by the next state block or another predetermined value. The other predetermined value may be, for example, a fixed data pattern, a variable data pattern, a specified value, or any other value suitable for initializing and/or testing the Directory Store. The output of the selector may be written to the Directory Store.
摘要翻译：用于在基于目录的连贯内存中测试和/或初始化目录存储的系统和方法。在一个说明性实施例中，基于目录的相干存储器包括用于存储多个数据条目的主存储器，用于存储主存储器中的至少一些数据条目的目录状态的目录存储器，以及下一个状态块响应于存储器请求确定所请求的数据条目的下一目录状态。为了提供对目录存储的访问，并且在一个说明性实施例中，提供了选择器，用于选择由下一个状态块提供的下一个目录状态值或另一个预定值。另一个预定值可以是例如固定数据模式，可变数据模式，指定值或适用于初始化和/或测试目录库的任何其他值。选择器的输出可能会写入目录存储。

3. 发明授权

US06594785B1 System and method for fault handling and recovery in a multi-processing system having hardware resources shared between multiple partitions 有权
标题翻译：具有在多个分区之间共享的硬件资源的多处理系统中的故障处理和恢复的系统和方法
公开(公告)号：US06594785B1
公开(公告)日：2003-07-15
申请号：US09561270
申请日：2000-04-28
申请人： Roger L. Gilbertson , Mitchell A. Bauman , Penny L. Svenkeson , James L. DePenning , Michael L. Haupt , Donald Kalvestrand , Daniel S. Tokoly , Frederick G. Fellenser , Maria A. Liedman
发明人： Roger L. Gilbertson , Mitchell A. Bauman , Penny L. Svenkeson , James L. DePenning , Michael L. Haupt , Donald Kalvestrand , Daniel S. Tokoly , Frederick G. Fellenser , Maria A. Liedman
IPC分类号： H02H305
CPC分类号： G06F11/0772 , G06F11/0712 , G06F11/0724 , G06F11/0793
摘要： Poisoning of specific memory locations as a process when a part of a multiprocessor computer system becomes faulty leads to ability to isolate specific data owned by individual failing units even in a shared memory area. Also continuous processing by non-failing units is allowable. A support processor handles non-immediate problems and allows resetting of memory locations formerly owned by failed units.
摘要翻译：当多处理器计算机系统的一部分变得有故障时，将特定存储器位置中毒作为过程导致即使在共享存储器区域中也能够分离由单个故障单元拥有的特定数据的能力。也可以由非故障单元进行连续处理。支持处理器处理非直接问题，并允许重置以前由故障单元拥有的存储器位置。

4. 发明授权

US06587931B1 Directory-based cache coherency system supporting multiple instruction processor and input/output caches 失效
标题翻译：基于目录的高速缓存一致性系统支持多指令处理器和输入/输出缓存
公开(公告)号：US06587931B1
公开(公告)日：2003-07-01
申请号：US09001598
申请日：1997-12-31
申请人： Mitchell A. Bauman , Eugene A. Rodi , Douglas E. Morrissey
发明人： Mitchell A. Bauman , Eugene A. Rodi , Douglas E. Morrissey
IPC分类号： G06F1208
CPC分类号： G06F12/0817 , G06F12/0886 , G06F2212/621
摘要： A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/O) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more IPs and to the shared main memory for caching units of data referred to as cache lines. The system further includes one or more I/O memories within ones of the I/O units, each I/O memory being coupled to the shared main memory for storing cache lines retrieved from the shared main memory. Coherency is maintained through the use of a central directory which stores status for each of the cache lines in the system. The status indicates the identity of the IP caches and the I/O memories having valid copies of a given cache line, and further identifies a set of access privileges, that is, the cache line “state”, associated with the cache line. The cache line states are used to implement a state machine which tracks the cache lines and ensures only valid copies of are maintained within the memory system. According to another aspect of the system, the main memory performs continuous tracking and control functions for all cache lines residing in the IP caches. In contrast, the system maintains tracking and control functions for only predetermined cache lines provided to the I/O units so that system overhead may be reduced. The coherency system further supports multiple heterogeneous instruction processors which operate on cache lines of different sizes.
摘要翻译：公开了一种基于目录的高速缓存一致性系统，用于具有通过共享主存储器耦合的多个指令处理器（IP）和多个输入/输出（I / O）单元的数据处理系统。该系统包括一个或多个IP高速缓冲存储器，每个IP缓存存储器分别耦合到一个或多个IP和共享主存储器，用于高速缓存被称为高速缓存线的数据单元。该系统还包括一个或多个I / O单元内的I / O存储器，每个I / O存储器耦合到共享主存储器，用于存储从共享主存储器检索的高速缓存线。通过使用存储系统中每个缓存行的状态的中央目录来维护一致性。该状态表示IP高速缓存和具有给定高速缓存行的有效副本的I / O存储器的身份，并进一步标识与高速缓存行相关联的一组访问权限，即高速缓存行“状态”。高速缓存行状态用于实现跟踪高速缓存行的状态机，并且仅确保在存储器系统内维护的有效副本。根据系统的另一方面，主存储器对驻留在IP高速缓存中的所有高速缓存行执行连续跟踪和控制功能。相比之下，系统仅为提供给I / O单元的预定高速缓存行维护跟踪和控制功能，从而可以减少系统开销。一致性系统还支持在不同大小的高速缓存线上运行的多个异构指令处理器。

5. 发明授权

US06477620B1 Cache-level return data by-pass system for a hierarchical memory 有权
标题翻译：用于分层存储器的缓存级返回数据旁路系统
公开(公告)号：US06477620B1
公开(公告)日：2002-11-05
申请号：US09467190
申请日：1999-12-20
申请人： Mitchell A. Bauman , Roger L. Gilbertson , Donald R. Kalvestrand , Joseph S. Schibinger , Daniel S. Tokoly
发明人： Mitchell A. Bauman , Roger L. Gilbertson , Donald R. Kalvestrand , Joseph S. Schibinger , Daniel S. Tokoly
IPC分类号： G06F1208
CPC分类号： G06F12/0813 , G06F12/0811
摘要： A data by-pass system for a hierarchical, multi-level, memory is disclosed. The by-pass system provides by-pass interfaces between storage devices located at predetermined levels within the memory hierarchy. The hierarchical memory system of the preferred embodiment includes a main memory coupled to multiple first storage devices that each stores addressable portions of data signals retrieved from the main memory. To facilitate a more efficient transfer of data between the various storage devices in the memory system, at least one by-pass interface coupling associated ones of the first storage devices is provided. Data retrieved from a target one of the first storage devices in response to a main memory request can be routed to a different requesting one of the first storage devices via the by-pass system without requiring the use of the main memory data interfaces.
摘要翻译：公开了一种用于分级，多级存储器的数据旁路系统。旁路系统在位于存储器层级内的预定级别的存储设备之间提供旁路接口。优选实施例的分级存储器系统包括耦合到多个第一存储设备的主存储器，每个存储器件存储从主存储器检索的数据信号的可寻址部分。为了便于在存储器系统中的各种存储设备之间更有效地传输数据，提供了耦合相关联的第一存储设备的至少一个旁路接口。可以响应于主存储器请求从第一存储设备中的目标一个检索的数据经由旁路系统路由到第一存储设备中的不同请求的一个，而不需要使用主存储器数据接口。

6. 发明授权

US06356991B1 Programmable address translation system 失效
标题翻译：可编程地址转换系统
公开(公告)号：US06356991B1
公开(公告)日：2002-03-12
申请号：US09001390
申请日：1997-12-31
申请人： Mitchell A. Bauman , Roger L. Gilbertson
发明人： Mitchell A. Bauman , Roger L. Gilbertson
IPC分类号： G06F1206
CPC分类号： G06F12/0607 , G06F12/0292
摘要： A programmable address translation system for a modular main memory is provided. The system is implemented using one or more General Register Arrays (GRAs), wherein each GRA performs logical-to-physical address translation for a predetermined address range within the system. Predetermined bits of a logical address are used to address a GRA associated with the logical address range. Data bits read from the GRA are then substituted for the predetermined bits of the logical address to form the physical address. In this manner, non-contiguous addressable banks of physical memory may be mapped to a selectable contiguous address range. By including within the GRA Address a number N of logical address bits used to address contiguous logical addresses, an address translation mechanism is provided which may be programmed to perform between 2-way and 2N-way address interleaving. Each GRA may be re-programmed dynamically to accommodate changing memory conditions as may occur, for example, when a range of memory is logically removed from a system because of errors. Furthermore, GRA reprogramming may occur while memory operations continue within other non-associated address ranges. Additionally, address interleaving may be selected for certain ones of the address ranges, whereas a non-interleaving scheme may be selected for other address ranges.
摘要翻译：提供了一种用于模块化主存储器的可编程地址转换系统。该系统使用一个或多个通用寄存器阵列（GRA）实现，其中每个GRA对系统内的预定地址范围进行逻辑到物理地址转换。使用逻辑地址的预定比特来寻址与逻辑地址范围相关联的GRA。然后将从GRA读取的数据位代替逻辑地址的预定位以形成物理地址。以这种方式，物理存储器的不连续可寻址组可以被映射到可选择的相邻地址范围。通过在GRA地址内包含用于寻址连续逻辑地址的N个逻辑地址位，提供地址转换机制，其可被编程为在2路和2N路地址交错之间执行。可以动态地重新编程每个GRA以适应可能发生的变化的存储器条件，例如当由于错误而从系统逻辑地移除存储器的范围时。此外，当存储器操作在其他非关联地址范围内继续时，可能会发生GRA重新编程。另外，可以针对某些地址范围来选择地址交织，而对于其他地址范围可以选择非交织方案。

7. 发明授权

US5960455A Scalable cross bar type storage controller 失效
标题翻译：可扩展横杆式存储控制器
公开(公告)号：US5960455A
公开(公告)日：1999-09-28
申请号：US777038
申请日：1996-12-30
申请人： Mitchell A. Bauman
发明人： Mitchell A. Bauman
IPC分类号： G06F12/08
CPC分类号： G06F12/0811
摘要： Method and apparatus for a computer system to efficiently operate with multiple instruction processors and input/output subsystem in a symmetrical multi-processing environment. The computer system uses a new storage controller having a high performance interconnect scheme that scales in system performance as additional common storage controller modules are added. The interconnect scheme has the cost advantage of a bus connected system while achieving the performance characteristics of a crossbar connected system.
摘要翻译：一种计算机系统的方法和装置，用于在对称的多处理环境中有效地操作多个指令处理器和输入/输出子系统。计算机系统使用具有高性能互连方案的新的存储控制器，其增加了附加的公共存储控制器模块来扩展系统性能。互连方案具有总线连接系统的成本优势，同时实现了交叉连接系统的性能特征。

8. 发明授权

US06868482B1 Method and apparatus for parallel store-in second level caching 有权
标题翻译：并行存储二级缓存的方法和装置
公开(公告)号：US06868482B1
公开(公告)日：2005-03-15
申请号：US09506038
申请日：2000-02-17
申请人： Donald W. Mackenthun , Mitchell A. Bauman , Donald C. Englin
发明人： Donald W. Mackenthun , Mitchell A. Bauman , Donald C. Englin
IPC分类号： G06F12/08 , G06F11/16
CPC分类号： G06F12/0804 , G06F12/0811 , G06F12/0891
摘要： Each dual multi-processing system has a number of processors, with each processor having a store in first-level write through cache to a second-level cache. A third-level memory is shared by the dual system with the first-level and second-level caches being globally addressable to all of the third-level memory. Processors can write through to the local second-level cache and have access to the remote second-level cache via the local storage controller. A coherency scheme for the dual system provides each second-level cache with indicators for each cache line showing which ones are valid and which ones have been modified or are different than what is reflected in the corresponding third level memory. The flush apparatus uses these two indicators to transfer all cache lines that are within the remote memory address range and have been modified, back to the remote memory prior to dynamically removing the local cache resources due to either system maintenance or dynamic partitioning.
摘要翻译：每个双重多处理系统具有多个处理器，每个处理器具有通过缓存的第一级写入到第二级缓存的存储。第三级存储器由双系统共享，第一级和第二级高速缓存可全局寻址到所有第三级存储器。处理器可以写入本地二级缓存，并通过本地存储控制器访问远程二级缓存。双系统的一致性方案为每个二级缓存提供每个高速缓存行的指示符，其中显示哪些是有效的，哪些已被修改或不同于相应的第三级存储器中反映的指示。冲洗装置使用这两个指示器将在远程存储器地址范围内的所有高速缓存行传送到远程存储器，然后由于系统维护或动态分区而动态地删除本地缓存资源。

9. 发明授权

US06799252B1 High-performance modular memory system with crossbar connections 有权
标题翻译：具有交叉连接的高性能模块化存储系统
公开(公告)号：US06799252B1
公开(公告)日：2004-09-28
申请号：US09774833
申请日：2001-01-31
申请人： Mitchell A. Bauman
发明人： Mitchell A. Bauman
IPC分类号： G06F1200
CPC分类号： G06F12/0817 , G06F12/0813 , G06F13/4022
摘要： A modular, expandable, multi-port main memory system that includes multiple point-to-point switch interconnections and a highly-parallel data path structure that allows multiple memory operations to occur simultaneously. The main memory system includes an expandable number of modular Memory Storage Units, each of which are mapped to a portion of the total address space of the main memory system, and may be accessed simultaneously. Each of the Memory Storage Units includes a predetermined number of memory ports, and an expandable number of memory banks, wherein each of the memory banks may be accessed simultaneously. Each of the memory banks is also modular, and includes an expandable number of memory devices each having a selectable memory capacity. All of the memory devices in the system may be performing different memory read or write operations substantially simultaneously and in parallel. Multiple data paths within each of the Memory Storage Units allow data transfer operations to occur to each of the multiple memory ports in parallel. Simultaneously with the transfer operations occurring to the memory ports, unrelated data transfer operations may occur to multiple ones of the memory devices within all memory banks in parallel. The main memory system further incorporates independent storage devices and control logic to implement a directory-based coherency protocol. Thus the main memory system is adapted to providing the flexibility, bandpass, and memory coherency needed to support a high-speed multiprocessor environment.
摘要翻译：一种模块化，可扩展的多端口主存储系统，包括多个点对点交换机互连以及允许多个存储器操作同时发生的高度并行数据路径结构。主存储器系统包括可扩展数量的模块化存储器单元，每个存储单元被映射到主存储器系统的总地址空间的一部分，并且可以被同时访问。每个存储器存储单元包括预定数量的存储器端口和可扩展数量的存储器组，其中可以同时访问每个存储器组。每个存储体也是模块化的，并且包括每个具有可选存储器容量的可扩展数量的存储器件。系统中的所有存储器件可以基本同时并行地执行不同的存储器读或写操作。每个内存存储单元内的多个数据路径允许数据传输操作并行地发生到多个存储器端口中的每一个。与存储器端口发生的传送操作同时，并行地在所有存储器组中的多个存储器件中可能发生不相关的数据传输操作。主存储系统还包括独立的存储设备和控制逻辑，以实现基于目录的一致性协议。因此，主存储器系统适于提供支持高速多处理器环境所需的灵活性，带通和存储器一致性。

10. 发明授权

US06457101B1 System and method for providing the speculative return of cached data within a hierarchical memory system 有权
标题翻译：用于在分层存储器系统内提供缓存数据的推测返回的系统和方法
公开(公告)号：US06457101B1
公开(公告)日：2002-09-24
申请号：US09468050
申请日：1999-12-20
申请人： Mitchell A. Bauman , Roger L. Gilbertson , Donald R. Kalvestrand , Joseph S. Schibinger , Daniel S. Tokoly
发明人： Mitchell A. Bauman , Roger L. Gilbertson , Donald R. Kalvestrand , Joseph S. Schibinger , Daniel S. Tokoly
IPC分类号： G06F1208
CPC分类号： G06F12/0817 , G06F12/0811 , G06F12/0862 , G06F2212/507
摘要： A hierarchical memory structure includes a directory-based main memory coupled to multiple first storage devices, each to store data signals retrieved from the main memory. Ones of the first storage devices are further respectively coupled to second storage devices, each to store data signals retrieved from the respectively coupled first storage devices. Fetch requests to retrieve data signals are issued by ones of the storage devices to the main memory. In response, the main memory determines where the most recent data copy resides, and issues a return request, if necessary to retrieve that copy for the requesting storage device. A speculative return generation logic circuit is coupled to at least two of the first storage devices to intercept the fetch requests. In response to an intercepted request, the speculative return generation logic circuit generates a speculative return request directly to one or more of the other coupled first storage devices. This speculative return request causes any updated copies of the requested data signals that may be stored at a lower level in the hierarchical memory, to be transferred to the first storage device. If a return request for the data is then issued by the main memory in response to the fetch request, the requested data signals are resident in a first storage device, and are readily available to the main memory.
摘要翻译：分层存储器结构包括耦合到多个第一存储设备的基于目录的主存储器，每个存储器件用于存储从主存储器检索的数据信号。第一存储设备的另外分别耦合到第二存储设备，每个存储设备存储从分别耦合的第一存储设备检索的数据信号。获取数据信号的请求由存储设备中的一个发送到主存储器。作为响应，主存储器确定最近的数据副本所在的位置，并且如果需要检索请求存储设备的该副本，则发出返回请求。推测返回生成逻辑电路耦合到至少两个第一存储设备以拦截提取请求。响应于被截取的请求，推测返回产生逻辑电路直接向一个或多个其它耦合的第一存储设备产生推测返回请求。该推测返回请求使得可以存储在分层存储器中的较低级的所请求的数据信号的任何更新的副本被传送到第一存储设备。如果主存储器响应于提取请求发出对数据的返回请求，则所请求的数据信号驻留在第一存储设备中，并且容易对主存储器可用。

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