专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6049845A System and method for providing speculative arbitration for transferring data 失效
标题翻译：提供传输数据的投机仲裁的系统和方法
公开(公告)号：US6049845A
公开(公告)日：2000-04-11
申请号：US964630
申请日：1997-11-05
申请人： Mitchell A. Bauman , Joseph S. Schibinger , Donald R. Kalvestrand , Douglas E. Morrissey
发明人： Mitchell A. Bauman , Joseph S. Schibinger , Donald R. Kalvestrand , Douglas E. Morrissey
IPC分类号： G06F13/18 , G06F12/08 , G06F13/16 , G06F13/362 , G06F15/167 , G06F13/00
CPC分类号： G06F13/1605
摘要： A system and method for optimizing the amount of time it takes for a requestor (device) to receive data from a memory storage unit in a multi-requestor bus environment. The present invention provides a unidirectional response signal, referred to as an early warning signal, sent from a memory storage unit to a device, sometime after that device has executed a fetch request for data, to alert the device that the data is forthcoming. This early warning signal allows the device to arbitrate for the data bus so that when the data arrives, the device will have exclusive ownership of the data bus to accept the data immediately. The present invention comprises a main memory, a cache memory, one or more processor modules, one or more I/O modules, and an early warning bus. The cache memory is connected to the main memory via an interface bus. The processor modules are connected to the cache memory via a processor interface bus. The I/O modules are connected to the main memory via an I/O interface bus. Both the processor modules and the I/O modules include means for requesting a data unit from the main memory. The early warning bus is connected between the main memory, the cache memory, and the I/O module.
摘要翻译：一种用于优化请求者（设备）从多请求者总线环境中的存储器存储单元接收数据所需的时间量的系统和方法。本发明提供了一种从存储器存储单元发送到设备的称为早期警告信号的单向响应信号，该设备在该设备执行了对数据的取出请求之后的某个时刻向该设备通知数据即将到来。该预警信号允许设备对数据总线进行仲裁，以便当数据到达时，设备将具有数据总线的独占所有权以立即接受数据。本发明包括主存储器，高速缓冲存储器，一个或多个处理器模块，一个或多个I / O模块和预警总线。高速缓存通过接口总线连接到主存储器。处理器模块通过处理器接口总线连接到高速缓冲存储器。 I / O模块通过I / O接口总线连接到主存储器。处理器模块和I / O模块都包括用于从主存储器请求数据单元的装置。预警总线连接在主存储器，高速缓冲存储器和I / O模块之间。

2. 发明授权

US06477620B1 Cache-level return data by-pass system for a hierarchical memory 有权
标题翻译：用于分层存储器的缓存级返回数据旁路系统
公开(公告)号：US06477620B1
公开(公告)日：2002-11-05
申请号：US09467190
申请日：1999-12-20
申请人： Mitchell A. Bauman , Roger L. Gilbertson , Donald R. Kalvestrand , Joseph S. Schibinger , Daniel S. Tokoly
发明人： Mitchell A. Bauman , Roger L. Gilbertson , Donald R. Kalvestrand , Joseph S. Schibinger , Daniel S. Tokoly
IPC分类号： G06F1208
CPC分类号： G06F12/0813 , G06F12/0811
摘要： A data by-pass system for a hierarchical, multi-level, memory is disclosed. The by-pass system provides by-pass interfaces between storage devices located at predetermined levels within the memory hierarchy. The hierarchical memory system of the preferred embodiment includes a main memory coupled to multiple first storage devices that each stores addressable portions of data signals retrieved from the main memory. To facilitate a more efficient transfer of data between the various storage devices in the memory system, at least one by-pass interface coupling associated ones of the first storage devices is provided. Data retrieved from a target one of the first storage devices in response to a main memory request can be routed to a different requesting one of the first storage devices via the by-pass system without requiring the use of the main memory data interfaces.
摘要翻译：公开了一种用于分级，多级存储器的数据旁路系统。旁路系统在位于存储器层级内的预定级别的存储设备之间提供旁路接口。优选实施例的分级存储器系统包括耦合到多个第一存储设备的主存储器，每个存储器件存储从主存储器检索的数据信号的可寻址部分。为了便于在存储器系统中的各种存储设备之间更有效地传输数据，提供了耦合相关联的第一存储设备的至少一个旁路接口。可以响应于主存储器请求从第一存储设备中的目标一个检索的数据经由旁路系统路由到第一存储设备中的不同请求的一个，而不需要使用主存储器数据接口。

3. 发明授权

US06457101B1 System and method for providing the speculative return of cached data within a hierarchical memory system 有权
标题翻译：用于在分层存储器系统内提供缓存数据的推测返回的系统和方法
公开(公告)号：US06457101B1
公开(公告)日：2002-09-24
申请号：US09468050
申请日：1999-12-20
申请人： Mitchell A. Bauman , Roger L. Gilbertson , Donald R. Kalvestrand , Joseph S. Schibinger , Daniel S. Tokoly
发明人： Mitchell A. Bauman , Roger L. Gilbertson , Donald R. Kalvestrand , Joseph S. Schibinger , Daniel S. Tokoly
IPC分类号： G06F1208
CPC分类号： G06F12/0817 , G06F12/0811 , G06F12/0862 , G06F2212/507
摘要： A hierarchical memory structure includes a directory-based main memory coupled to multiple first storage devices, each to store data signals retrieved from the main memory. Ones of the first storage devices are further respectively coupled to second storage devices, each to store data signals retrieved from the respectively coupled first storage devices. Fetch requests to retrieve data signals are issued by ones of the storage devices to the main memory. In response, the main memory determines where the most recent data copy resides, and issues a return request, if necessary to retrieve that copy for the requesting storage device. A speculative return generation logic circuit is coupled to at least two of the first storage devices to intercept the fetch requests. In response to an intercepted request, the speculative return generation logic circuit generates a speculative return request directly to one or more of the other coupled first storage devices. This speculative return request causes any updated copies of the requested data signals that may be stored at a lower level in the hierarchical memory, to be transferred to the first storage device. If a return request for the data is then issued by the main memory in response to the fetch request, the requested data signals are resident in a first storage device, and are readily available to the main memory.
摘要翻译：分层存储器结构包括耦合到多个第一存储设备的基于目录的主存储器，每个存储器件用于存储从主存储器检索的数据信号。第一存储设备的另外分别耦合到第二存储设备，每个存储设备存储从分别耦合的第一存储设备检索的数据信号。获取数据信号的请求由存储设备中的一个发送到主存储器。作为响应，主存储器确定最近的数据副本所在的位置，并且如果需要检索请求存储设备的该副本，则发出返回请求。推测返回生成逻辑电路耦合到至少两个第一存储设备以拦截提取请求。响应于被截取的请求，推测返回产生逻辑电路直接向一个或多个其它耦合的第一存储设备产生推测返回请求。该推测返回请求使得可以存储在分层存储器中的较低级的所请求的数据信号的任何更新的副本被传送到第一存储设备。如果主存储器响应于提取请求发出对数据的返回请求，则所请求的数据信号驻留在第一存储设备中，并且容易对主存储器可用。

4. 发明授权

US4376976A Overlapped macro instruction control system 失效
标题翻译：重叠宏指令控制系统
公开(公告)号：US4376976A
公开(公告)日：1983-03-15
申请号：US174035
申请日：1980-07-31
申请人： Archie E. Lahti , Kenneth L. Engelbrecht , Donald R. Kalvestrand
发明人： Archie E. Lahti , Kenneth L. Engelbrecht , Donald R. Kalvestrand
IPC分类号： G06F9/22 , G06F9/28 , G06F9/38
CPC分类号： G06F9/28
摘要： A system for overlapping macro instruction execution is described for use in a data processing system. A pair of control storage devices each store the micro instruction sets required to execute all macro instructions in the repertoire and are used for alternate macro instructions. Each of the controlled storage devices is addressable to entry addresses by the macro instructions. After entry, addressing is by the contents of the micro instructions with provision made for conditional branching. An overlap count storage device is provided for storing overlap counts for all possible sequences of macro instructions. These overlap counts define the number of micro instructions of the current macro instruction that must be executed before the next macro instruction can proceed. Micro instruction execution is by clock cycle and are counted as they are executed. The count is compared to the stored overlap count for the current sequence of macro instructions and overlap execution is enabled when comparison is found. Overlap of macro instruction execution is allowed to occur when the current remaining micro instructions for the current macro instruction define functions that are mutually exclusive with the functions controlled by the next macro instruction. During overlap, micro instructions are loaded in an execution register from both control storage devices. Overlapping instructions that have variable execution sequences is controlled by halting the count of micro instruction executions until the variable sequence has been completed.
摘要翻译：描述用于重叠宏指令执行的系统用于数据处理系统。一对控制存储设备每个存储执行所有所有宏指令所需的微指令集，并用于备用宏指令。每个受控存储设备可通过宏指令对入口地址进行寻址。进入后，通过微指令的内容进行寻址，并提供条件分支。提供重叠计数存储装置用于存储所有可能的宏指令序列的重叠计数。这些重叠计数定义了在下一个宏指令可以进行之前必须执行的当前宏指令的微指令数。微指令执行是按时钟周期进行的，并在执行时进行计数。将计数与当前宏指令序列的存储重叠计数进行比较，并且在发现比较时启用重叠执行。当当前宏指令的当前剩余微指令定义与下一个宏指令控制的功能相互排斥的功能时，允许执行宏指令执行重叠。在重叠期间，微指令从两个控制存储设备加载到执行寄存器中。具有可变执行序列的重叠指令通过停止微指令执行的计数直到变量序列完成为止来控制。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式