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1. 发明授权

US06438659B1 Directory based cache coherency system supporting multiple instruction processor and input/output caches 有权
标题翻译：基于目录的高速缓存一致性系统支持多指令处理器和输入/输出缓存
公开(公告)号：US06438659B1
公开(公告)日：2002-08-20
申请号：US09645233
申请日：2000-08-24
申请人： Mitchell A. Bauman , Eugene A. Rodi , Douglas E. Morrissey
发明人： Mitchell A. Bauman , Eugene A. Rodi , Douglas E. Morrissey
IPC分类号： G06F1208
CPC分类号： G06F12/0817 , G06F12/0886 , G06F2212/621
摘要： A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/0) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more IPs and to the shared main memory for caching units of data referred to as cache lines. The system further includes one or more I/O memories within ones of the I/O units, each I/O memory being coupled to the shared main memory for storing cache lines retrieved from the shared main memory. Coherency is maintained through the use of a central directory which stores status for each of the cache lines in the system. The status indicates the identity of the IP caches and the I/O memories having valid copies of a given cache line, and further identifies a set of access privileges, that is, the cache line “state”, associated with the cache line. The cache line states are used to implement a state machine which tracks the cache lines and ensures only valid copies of are maintained within the memory system. According to another aspect of the system, the main memory performs continuous tracking and control functions for all cache lines residing in the IP caches. In contrast, the system maintains tracking and control functions for only predetermined cache lines provided to the I/O units so that system overhead may be reduced. The coherency system further supports multiple heterogeneous instruction processors which operate on cache lines of different sizes.
摘要翻译：公开了一种基于目录的高速缓存一致性系统，用于具有通过共享主存储器耦合的多个指令处理器（IP）和多个输入/输出（I / O）单元的数据处理系统。该系统包括一个或多个IP高速缓冲存储器，每个IP缓存存储器分别耦合到一个或多个IP和共享主存储器，用于高速缓存被称为高速缓存线的数据单元。该系统还包括一个或多个I / O单元内的I / O存储器，每个I / O存储器耦合到共享主存储器，用于存储从共享主存储器检索的高速缓存线。通过使用存储系统中每个缓存行的状态的中央目录来维护一致性。该状态表示IP高速缓存和具有给定高速缓存行的有效副本的I / O存储器的身份，并进一步标识与高速缓存行相关联的一组访问权限，即高速缓存行“状态”。高速缓存行状态用于实现跟踪高速缓存行的状态机，并且仅确保在存储器系统内维护的有效副本。根据系统的另一方面，主存储器对驻留在IP高速缓存中的所有高速缓存行执行连续跟踪和控制功能。相比之下，系统仅为提供给I / O单元的预定高速缓存行维护跟踪和控制功能，从而可以减少系统开销。一致性系统还支持在不同大小的高速缓存线上运行的多个异构指令处理器。

2. 发明授权

US06587931B1 Directory-based cache coherency system supporting multiple instruction processor and input/output caches 失效
标题翻译：基于目录的高速缓存一致性系统支持多指令处理器和输入/输出缓存
公开(公告)号：US06587931B1
公开(公告)日：2003-07-01
申请号：US09001598
申请日：1997-12-31
申请人： Mitchell A. Bauman , Eugene A. Rodi , Douglas E. Morrissey
发明人： Mitchell A. Bauman , Eugene A. Rodi , Douglas E. Morrissey
IPC分类号： G06F1208
CPC分类号： G06F12/0817 , G06F12/0886 , G06F2212/621
摘要： A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/O) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more IPs and to the shared main memory for caching units of data referred to as cache lines. The system further includes one or more I/O memories within ones of the I/O units, each I/O memory being coupled to the shared main memory for storing cache lines retrieved from the shared main memory. Coherency is maintained through the use of a central directory which stores status for each of the cache lines in the system. The status indicates the identity of the IP caches and the I/O memories having valid copies of a given cache line, and further identifies a set of access privileges, that is, the cache line “state”, associated with the cache line. The cache line states are used to implement a state machine which tracks the cache lines and ensures only valid copies of are maintained within the memory system. According to another aspect of the system, the main memory performs continuous tracking and control functions for all cache lines residing in the IP caches. In contrast, the system maintains tracking and control functions for only predetermined cache lines provided to the I/O units so that system overhead may be reduced. The coherency system further supports multiple heterogeneous instruction processors which operate on cache lines of different sizes.
摘要翻译：公开了一种基于目录的高速缓存一致性系统，用于具有通过共享主存储器耦合的多个指令处理器（IP）和多个输入/输出（I / O）单元的数据处理系统。该系统包括一个或多个IP高速缓冲存储器，每个IP缓存存储器分别耦合到一个或多个IP和共享主存储器，用于高速缓存被称为高速缓存线的数据单元。该系统还包括一个或多个I / O单元内的I / O存储器，每个I / O存储器耦合到共享主存储器，用于存储从共享主存储器检索的高速缓存线。通过使用存储系统中每个缓存行的状态的中央目录来维护一致性。该状态表示IP高速缓存和具有给定高速缓存行的有效副本的I / O存储器的身份，并进一步标识与高速缓存行相关联的一组访问权限，即高速缓存行“状态”。高速缓存行状态用于实现跟踪高速缓存行的状态机，并且仅确保在存储器系统内维护的有效副本。根据系统的另一方面，主存储器对驻留在IP高速缓存中的所有高速缓存行执行连续跟踪和控制功能。相比之下，系统仅为提供给I / O单元的预定高速缓存行维护跟踪和控制功能，从而可以减少系统开销。一致性系统还支持在不同大小的高速缓存线上运行的多个异构指令处理器。

3. 发明授权

US6049845A System and method for providing speculative arbitration for transferring data 失效
标题翻译：提供传输数据的投机仲裁的系统和方法
公开(公告)号：US6049845A
公开(公告)日：2000-04-11
申请号：US964630
申请日：1997-11-05
申请人： Mitchell A. Bauman , Joseph S. Schibinger , Donald R. Kalvestrand , Douglas E. Morrissey
发明人： Mitchell A. Bauman , Joseph S. Schibinger , Donald R. Kalvestrand , Douglas E. Morrissey
IPC分类号： G06F13/18 , G06F12/08 , G06F13/16 , G06F13/362 , G06F15/167 , G06F13/00
CPC分类号： G06F13/1605
摘要： A system and method for optimizing the amount of time it takes for a requestor (device) to receive data from a memory storage unit in a multi-requestor bus environment. The present invention provides a unidirectional response signal, referred to as an early warning signal, sent from a memory storage unit to a device, sometime after that device has executed a fetch request for data, to alert the device that the data is forthcoming. This early warning signal allows the device to arbitrate for the data bus so that when the data arrives, the device will have exclusive ownership of the data bus to accept the data immediately. The present invention comprises a main memory, a cache memory, one or more processor modules, one or more I/O modules, and an early warning bus. The cache memory is connected to the main memory via an interface bus. The processor modules are connected to the cache memory via a processor interface bus. The I/O modules are connected to the main memory via an I/O interface bus. Both the processor modules and the I/O modules include means for requesting a data unit from the main memory. The early warning bus is connected between the main memory, the cache memory, and the I/O module.
摘要翻译：一种用于优化请求者（设备）从多请求者总线环境中的存储器存储单元接收数据所需的时间量的系统和方法。本发明提供了一种从存储器存储单元发送到设备的称为早期警告信号的单向响应信号，该设备在该设备执行了对数据的取出请求之后的某个时刻向该设备通知数据即将到来。该预警信号允许设备对数据总线进行仲裁，以便当数据到达时，设备将具有数据总线的独占所有权以立即接受数据。本发明包括主存储器，高速缓冲存储器，一个或多个处理器模块，一个或多个I / O模块和预警总线。高速缓存通过接口总线连接到主存储器。处理器模块通过处理器接口总线连接到高速缓冲存储器。 I / O模块通过I / O接口总线连接到主存储器。处理器模块和I / O模块都包括用于从主存储器请求数据单元的装置。预警总线连接在主存储器，高速缓冲存储器和I / O模块之间。

4. 发明授权

US6052760A Computer system including plural caches and utilizing access history or patterns to determine data ownership for efficient handling of software locks 失效
标题翻译：计算机系统包括多个高速缓存，并且利用访问历史或模式来确定用于有效处理软件锁的数据所有权
公开(公告)号：US6052760A
公开(公告)日：2000-04-18
申请号：US964626
申请日：1997-11-05
申请人： Mitchell A. Bauman , Arthur J. Nilson , Douglas E. Morrissey
发明人： Mitchell A. Bauman , Arthur J. Nilson , Douglas E. Morrissey
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0811 , G06F12/0817
摘要： A system and method for enabling a multiprocessor system employing a memory hierarchy to identify data units or locations being used as software locks. The memory hierarchy comprises a main memory having a plurality of data units, a plurality of caches that operate independently of each other, and at least one coherent domain interfaced to each cache. Each coherent domain comprises at least two processors. The main memory maintains coherency of data among the plurality of caches using a directory that maintains information about each data line. The system of the present invention allows a requesting agent, such as a processor or cache, to request a data unit without specifying the type of ownership, where ownership may be exclusive or shared. The directory includes history information that defines the previous access pattern of the requested data unit. Prior to forwarding the requested data unit to the requesting agent, the main memory checks, using a conditional fetch command, the history information to determine what type of ownership to associate with the requested data unit. The requested data unit is then delivered to the requesting agent with ownership rights specified by the history information. The processors may utilize a directory-based protocol such as MESI (modified, exclusive, shared, invalid) to maintain coherence among the processors, with each processor snooping a shared bus to track the status of caches lines in the other processors.
摘要翻译：一种用于使得采用存储器层次结构的多处理器系统能够识别用作软件锁的数据单元或位置的系统和方法。存储器层级包括具有多个数据单元的主存储器，彼此独立地操作的多个高速缓存以及与每个高速缓存接口的至少一个相干域。每个相干域包括至少两个处理器。主存储器使用维护关于每个数据线的信息的目录来保持多个高速缓存之间的数据的一致性。本发明的系统允许诸如处理器或高速缓存的请求代理请求数据单元而不指定所有权的类型，其中所有权可以是独占的或共享的。该目录包括定义所请求数据单元的先前访问模式的历史信息。在将所请求的数据单元转发到请求代理之前，主存储器使用条件获取命令来检查历史信息以确定与请求的数据单元相关联的所有权类型。所请求的数据单元然后被传递给具有由历史信息指定的所有权的请求代理。处理器可以使用诸如MESI（经修改，排他，共享，无效）的基于目录的协议来维持处理器之间的一致性，每个处理器窥探共享总线以跟踪其他处理器中的高速缓存行的状态。

5. 发明授权

US6014709A Message flow protocol for avoiding deadlocks 失效
标题翻译：用于避免死锁的消息流协议
公开(公告)号：US6014709A
公开(公告)日：2000-01-11
申请号：US964606
申请日：1997-11-05
申请人： Robert C. Gulick , Mitchell A. Bauman , Douglas E. Morrissey
发明人： Robert C. Gulick , Mitchell A. Bauman , Douglas E. Morrissey
IPC分类号： G06F12/08 , G06F15/167 , G06F15/173 , G06F13/00
CPC分类号： G06F15/17375
摘要： System and method for controlling the flow of messages in a computer system to minimize congestion and prevent deadlocks in communications. The computer system includes a main memory, a plurality of crossbar switches, a plurality of third level caches, and a plurality of input/output modules, which are interconnected via the communications network of the computer system. System and method prevents deadlocks between input/output modules and main memory, and between processors and main memory caused by data needed for making forward progress in processing being trapped behind messages. System and method utilize control signals and auxiliary buffers to hold and redirect messages out of the path of data so that data may flow to the input/output modules and processors when needed, and messages may flow when convenient.
摘要翻译：用于控制计算机系统中的消息流的系统和方法，以最小化拥塞并防止通信中的死锁。计算机系统包括经由计算机系统的通信网络互连的主存储器，多个交叉开关，多个第三级高速缓存和多个输入/输出模块。系统和方法可以防止输入/输出模块与主存储器之间以及处理器与主存储器之间的死锁，这些数据是由处理中被捕获的信息所需的数据所需的。系统和方法利用控制信号和辅助缓冲器来保存和重定向数据路径中的消息，以便在需要时数据可能流向输入/输出模块和处理器，并且消息可以在方便时流动。

6. 发明授权

US06389515B1 System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations 有权
标题翻译：用于避免死锁的系统和方法，利用分裂锁定操作在非原子操作期间提供对存储器的独占访问
公开(公告)号：US06389515B1
公开(公告)日：2002-05-14
申请号：US09597621
申请日：2000-06-20
申请人： Joseph S. Schibinger , Douglas E. Morrissey
发明人： Joseph S. Schibinger , Douglas E. Morrissey
IPC分类号： G06F1314
CPC分类号： G06F9/524 , G06F12/0817
摘要： A system and method are provided to avoid deadlocks when performing non-atomic operations on data in a shared memory accessed by multiple processors, whereby the shared memory sends messages to implement a split lock. Via the messages, the requesting processor is granted exclusive access to the shared memory so that no other processor may access the same data until after the non-atomic operation has completed. The messages used to avoid the deadlock include a split lock request, a lock message, a grant message, a gone idle message and a release idle message. By using the above messages, the system accepts requests from multiple processors for exclusive access to memory, orders all of the requests, and awards exclusive access to the first processor to make a request. The system can include a cache memory, associated with a requesting processor, which sends a lock request to the main memory in response to a split lock request from a requesting processor.
摘要翻译：提供了一种系统和方法，以便在由多个处理器访问的共享存储器中的数据执行非原子操作时避免死锁，由此共享存储器发送消息以实现拆分锁。通过消息，请求处理器被授予对共享存储器的独占访问，使得在非原子操作完成之后，没有其他处理器可以访问相同的数据。用于避免死锁的消息包括拆分锁定请求，锁定消息，授权消息，未完成的空闲消息和释放空闲消息。通过使用上述消息，系统接受来自多个处理器的请求，用于对存储器的独占访问，订购所有请求，并授予对第一处理器的独占访问以进行请求。该系统可以包括与请求处理器相关联的高速缓冲存储器，其响应于来自请求处理器的分离锁定请求向主存储器发送锁定请求。

7. 发明授权

US6092156A System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations 失效
标题翻译：用于避免死锁的系统和方法，利用分裂锁定操作在非原子操作期间提供对存储器的独占访问
公开(公告)号：US6092156A
公开(公告)日：2000-07-18
申请号：US964623
申请日：1997-11-05
申请人： Joseph S. Schibinger , Douglas E. Morrissey
发明人： Joseph S. Schibinger , Douglas E. Morrissey
IPC分类号： G06F12/08 , G06F9/46 , G06F9/52 , G06F12/00 , G06F15/167 , G06F13/364
CPC分类号： G06F9/524 , G06F12/0817
摘要： A system and method for avoiding deadlocks when performing non-atomic operations on data in a shared memory accessed by multiple processors that sends messages to implement a split lock. Via the messages, the requesting processor is granted exclusive access to the shared memory so that no other processor may access the same data until after the non-atomic operation has completed. The messages used to avoid the deadlock include a split lock request, a lock message, a grant message, a gone idle message and a release idle message. By using the above messages, the system and method of the present invention accepts requests from multiple processors for exclusive access to memory, orders all of the requests, and awards exclusive access to the first processor to make a request. The system can include a cache memory, associated with a requesting processor, which sends a lock request to the main memory in response to a split lock request from a requesting processor.
摘要翻译：一种系统和方法，用于在由发送消息以实现分裂锁的多个处理器访问的共享存储器中的数据执行非原子操作时避免死锁。通过消息，请求处理器被授予对共享存储器的独占访问，使得在非原子操作完成之后，没有其他处理器可以访问相同的数据。用于避免死锁的消息包括拆分锁定请求，锁定消息，授权消息，未完成的空闲消息和释放空闲消息。通过使用上述消息，本发明的系统和方法接受来自多个处理器的请求，用于对存储器的独占访问，对所有请求进行排序，并授予对第一处理器的独占访问以进行请求。该系统可以包括与请求处理器相关联的高速缓冲存储器，其响应于来自请求处理器的分离锁定请求向主存储器发送锁定请求。

8. 发明授权

US06314501B1 Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory 有权
标题翻译：用于在计算机系统的不同分区中操作多个操作系统并允许不同分区通过共享存储器彼此通信的计算机系统和方法
公开(公告)号：US06314501B1
公开(公告)日：2001-11-06
申请号：US09215424
申请日：1998-12-18
申请人： Robert C. Gulick , Douglas E. Morrissey , Charles Raymond Caldarale , Hans Christian Mikkelsen , Bruce Alan Vessey , Sharon M Mauer , Craig F. Russ , Eugene W. Troxell , Maureen P. Connell , James R. Hunter
发明人： Robert C. Gulick , Douglas E. Morrissey , Charles Raymond Caldarale , Hans Christian Mikkelsen , Bruce Alan Vessey , Sharon M Mauer , Craig F. Russ , Eugene W. Troxell , Maureen P. Connell , James R. Hunter
IPC分类号： G06F1206
CPC分类号： G06F9/544 , G06F9/54
摘要： A computer system comprises a plurality of processing modules that can be configured into different partitions within the computer system, and a main memory. Each partition operates under the control of a separate operating system. At least one shared memory window is defined within the main memory to which multiple partitions have shared access, and each partition may also be assigned an exclusive memory window. Program code executing on different partitions enables those partitions to communicate with each other through the shared memory window. Means are also provided for mapping the physical address space of the processors in each partition to the respective exclusive memory windows assigned to each partition, so that the exclusive memory windows assigned to each partition appear to the respective operating systems executing on those partitions as if they all start at the same base address.
摘要翻译：计算机系统包括可以被配置成计算机系统内的不同分区的多个处理模块和主存储器。每个分区在独立的操作系统的控制下运行。在主存储器内定义至少一个共享存储器窗口，多个分区具有共享访问权限，并且每个分区也可以被分配独占存储器窗口。在不同分区上执行的程序代码使这些分区能够通过共享存储器窗口相互通信。还提供了用于将每个分区中的处理器的物理地址空间映射到分配给每个分区的相应独占存储器窗口的装置，使得分配给每个分区的排他存储器窗口对于在这些分区上执行的相应操作系统似乎如都从同一个基地址开始。

9. 发明授权

US5832310A Serial I/O channel having dependent and synchronous sources of control data and user defined data 失效
标题翻译：具有依赖和同步控制数据源和用户定义数据的串行I / O通道
公开(公告)号：US5832310A
公开(公告)日：1998-11-03
申请号：US795457
申请日：1997-02-04
申请人： Douglas E. Morrissey , Edward T. Cavanagh, Jr. , Gene T. Wieder , Kin H. Ng , William E. Oldham
发明人： Douglas E. Morrissey , Edward T. Cavanagh, Jr. , Gene T. Wieder , Kin H. Ng , William E. Oldham
IPC分类号： G06F13/12 , G06F13/00
CPC分类号： G06F13/122
摘要： Apparatus is provided for transferring user defined data from a parallel storage medium to a serial link driver in an I/O channel subsystem of a processor or I/O device controller. The serial link driver transmits a frame of user defined data over a serial data transfer medium. A data buffer receives and stores user defined data from the parallel storage medium. A control data facility that is distinct from the data buffer forms and transmits control data from the sender of the frame to the recipient of the frame via a path that does not include the data buffer. The control data facility includes respectively different dedicated logic for asynchronously generating each of the following: special character sequences, frame delimiters, headers, and cyclic redundancy checksums. A switching facility receives the user defined data from the data buffer. The switching facility also receives control data from the control data facility. The switching facility provides either the user defined data or the control data to the serial link driver. A data path control mechanism signals the switching facility to alternately provide the control data and the user defined data to the serial link driver, thereby forming frames.
摘要翻译：提供了用于将用户定义的数据从并行存储介质传送到处理器或I / O设备控制器的I / O通道子系统中的串行链路驱动器的装置。串行链路驱动器通过串行数据传输介质发送用户定义的数据帧。数据缓冲器从并行存储介质接收并存储用户定义的数据。与数据缓冲器不同的控制数据设施形成并通过不包括数据缓冲器的路径将控制数据从帧的发送者发送到帧的接收者。控制数据设备分别包括不同的专用逻辑，用于异步地产生以下各项：特殊字符序列，帧分隔符，报头和循环冗余校验和。交换设备从数据缓冲器接收用户定义的数据。交换设备还从控制数据设备接收控制数据。交换设备向用户定义的数据或控制数据提供给串行链路驱动程序。数据路径控制机构发信号通知切换设备，以交替地向串行链路驱动器提供控制数据和用户定义的数据，从而形成帧。

10. 发明授权

US5553302A Serial I/O channel having independent and asynchronous facilities with sequence recognition, frame recognition, and frame receiving mechanism for receiving control and user defined data 失效
标题翻译：串行I / O通道具有独立和异步的设备，具有序列识别，帧识别和用于接收控制和用户定义数据的帧接收机制
公开(公告)号：US5553302A
公开(公告)日：1996-09-03
申请号：US176805
申请日：1993-12-30
申请人： Douglas E. Morrissey , Edward T. Cavanagh, Jr. , Gene T. Wieder , Kin H. Ng , William E. Oldham
发明人： Douglas E. Morrissey , Edward T. Cavanagh, Jr. , Gene T. Wieder , Kin H. Ng , William E. Oldham
IPC分类号： G06F13/12 , H04L12/56 , H04L29/08 , G06F13/00
CPC分类号： H04L49/901 , G06F13/128 , H04L49/90 , H04L49/9057 , H04L69/324
摘要： An Input/Output (I/O) subsystem is provided for transferring frames containing frame control data from a serial data transfer medium to a parallel storage medium. The subsystem includes independent components for processing different portions of the received character stream. The subsystem includes a sequence recognition mechanism for receiving and identifying any of a plurality of digital data bit sequences. The sequences represent channel status information from the data transfer medium. The sequence recognition mechanism provides an interrupt signal derived from the sequences. A frame recognition mechanism responds to the interrupt signal. The frame recognition mechanism receives and identifies a start-of-frame delimiter or an end-of-frame delimiter from the data transfer medium. The frame recognition mechanism provides a frame status signal. A frame receiving mechanism responds to the frame status signal. The frame receiving mechanism receives and identifies a frame header from the data transfer medium. The frame receiving mechanism also verifies link and device level I/O protocol compliance asynchronously while any user defined data included in the frame are being received. The frame receiving mechanism also stores the user defined data in the parallel storage medium concurrently with the verification, if any user defined data are included.
摘要翻译：提供输入/输出（I / O）子系统，用于将包含帧控制数据的帧从串行数据传输介质传送到并行存储介质。子系统包括用于处理接收到的字符流的不同部分的独立组件。子系统包括用于接收和识别多个数字数据位序列中的任一个的序列识别机制。这些序列表示来自数据传送介质的信道状态信息。序列识别机制提供从序列导出的中断信号。帧识别机制响应中断信号。帧识别机制从数据传输介质接收并识别帧起始定界符或帧结束定界符。帧识别机制提供帧状态信号。帧接收机制响应帧状态信号。帧接收机构从数据传送介质接收并识别帧头。帧接收机制还在接收到帧中包含的任何用户定义的数据的同时异步地验证链路和设备级I / O协议的合规性。如果包括任何用户定义的数据，帧接收机构也将用户定义的数据与验证同时存储在并行存储介质中。

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