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1. 发明授权

US5875201A Second level cache having instruction cache parity error control 失效
标题翻译：具有指令缓存奇偶校验错误控制的二级缓存
公开(公告)号：US5875201A
公开(公告)日：1999-02-23
申请号：US777037
申请日：1996-12-30
申请人： Mitchell A. Bauman , Donald W. Mackenthun , Gary J. Lucas , James L. Federici
发明人： Mitchell A. Bauman , Donald W. Mackenthun , Gary J. Lucas , James L. Federici
IPC分类号： G06F11/10 , G06F11/00 , G11C29/00
CPC分类号： G06F11/1008 , G06F11/1064
摘要： Method and apparatus for detecting and correcting memory storage data errors in a system utilizing parity error detection. An error detected in the memory storage device results in a parity error being reported, thereby causing the corresponding address location to be deactivated. Once deactivated, no further reading or writing is performed at that address location for a predetermined time period. The parity error reporting and address deactivation is accomplished without an access time penalty and requires a reduced number of I/O pins.
摘要翻译：用于检测和校正使用奇偶校验错误检测的系统中的存储器存储数据错误的方法和装置。在存储器存储装置中检测到的错误导致正在报告奇偶校验错误，从而导致对应的地址位置被去激活。一旦停用，在该地址位置不进行进一步的读取或写入达预定的时间段。奇偶校验错误报告和地址禁用在没有访问时间损失的情况下完成，并且需要减少I / O引脚数。

2. 发明授权

US6122711A Method of and apparatus for store-in second level cache flush 失效
标题翻译：存储二级缓存刷新的方法和设备
公开(公告)号：US6122711A
公开(公告)日：2000-09-19
申请号：US779472
申请日：1997-01-07
申请人： Donald W. Mackenthun , Mitchell A. Bauman , Donald C. Englin
发明人： Donald W. Mackenthun , Mitchell A. Bauman , Donald C. Englin
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0804 , G06F12/0811 , G06F12/0891
摘要： Flush apparatus for a dual multi-processing system. Each dual multi-processing system has a number of processors, with each processor having a store in first-level write through cache to a second-level cache. A third-level memory is shared by the dual system with the first-level and second-level caches being globally addressable to all of the third-level memory. Processors can write through to the local second-level cache and have access to the remote second-level cache via the local storage controller. A coherency scheme for the dual system provides each second-level cache with indicators for each cache line showing which ones are valid and which ones have been modified or are different than what is reflected in the corresponding third level memory. The flush apparatus uses these two indicators to transfer all cache lines that are within the remote memory address range and have been modified, back to the remote memory prior to dynamically removing the local cache resources due to either system maintenance or dynamic partitioning. The flush apparatus prevents the loss of system data during such a process due to the inherent nature of a store in second level cache.
摘要翻译：用于双重多处理系统的冲洗装置。每个双重多处理系统具有多个处理器，每个处理器具有通过缓存的第一级写入到第二级缓存的存储。第三级存储器由双系统共享，第一级和第二级高速缓存可全局寻址到所有第三级存储器。处理器可以写入本地二级缓存，并通过本地存储控制器访问远程二级缓存。双系统的一致性方案为每个二级缓存提供每个高速缓存行的指示符，其中显示哪些是有效的，哪些已被修改或不同于相应的第三级存储器中反映的指示。冲洗装置使用这两个指示器将在远程存储器地址范围内的所有高速缓存行传送到远程存储器，然后由于系统维护或动态分区而动态地删除本地缓存资源。由于第二级高速缓存中的存储的固有特性，冲洗装置在这种处理期间防止了系统数据的丢失。

3. 发明授权

US06868482B1 Method and apparatus for parallel store-in second level caching 有权
标题翻译：并行存储二级缓存的方法和装置
公开(公告)号：US06868482B1
公开(公告)日：2005-03-15
申请号：US09506038
申请日：2000-02-17
申请人： Donald W. Mackenthun , Mitchell A. Bauman , Donald C. Englin
发明人： Donald W. Mackenthun , Mitchell A. Bauman , Donald C. Englin
IPC分类号： G06F12/08 , G06F11/16
CPC分类号： G06F12/0804 , G06F12/0811 , G06F12/0891
摘要： Each dual multi-processing system has a number of processors, with each processor having a store in first-level write through cache to a second-level cache. A third-level memory is shared by the dual system with the first-level and second-level caches being globally addressable to all of the third-level memory. Processors can write through to the local second-level cache and have access to the remote second-level cache via the local storage controller. A coherency scheme for the dual system provides each second-level cache with indicators for each cache line showing which ones are valid and which ones have been modified or are different than what is reflected in the corresponding third level memory. The flush apparatus uses these two indicators to transfer all cache lines that are within the remote memory address range and have been modified, back to the remote memory prior to dynamically removing the local cache resources due to either system maintenance or dynamic partitioning.
摘要翻译：每个双重多处理系统具有多个处理器，每个处理器具有通过缓存的第一级写入到第二级缓存的存储。第三级存储器由双系统共享，第一级和第二级高速缓存可全局寻址到所有第三级存储器。处理器可以写入本地二级缓存，并通过本地存储控制器访问远程二级缓存。双系统的一致性方案为每个二级缓存提供每个高速缓存行的指示符，其中显示哪些是有效的，哪些已被修改或不同于相应的第三级存储器中反映的指示。冲洗装置使用这两个指示器将在远程存储器地址范围内的所有高速缓存行传送到远程存储器，然后由于系统维护或动态分区而动态地删除本地缓存资源。

4. 发明授权

US5450578A Method and apparatus for automatically routing around faults within an interconnect system 失效
标题翻译：用于自动路由互连系统内的故障的方法和装置
公开(公告)号：US5450578A
公开(公告)日：1995-09-12
申请号：US172647
申请日：1993-12-23
申请人： Donald W. Mackenthun
发明人： Donald W. Mackenthun
IPC分类号： G06F11/20 , G06F11/00 , G06F15/173 , G11C29/00
CPC分类号： G06F11/2017 , G06F11/2007 , G11C29/006
摘要： A computer architecture for providing enhanced reliability while mitigating the high costs of total redundancy. The HUB and Street architecture couples a plurality of commonly shared busses called streets with a plurality of smart switching elements called HUBs. The streets are busses for transferring data between HUB elements. The HUB elements are capable of directing data across the street structures and deliver said data to a desired destination. The system designer can either increase or decrease the number of HUB elements and streets to either increase or decrease the reliability and cost of the particular computer system. In addition, the HUB elements have a built in priority scheme for allowing high priority data to be transferred before low priority data. Finally, the HUB elements have the capability of automatically detecting faults within the system and can redirect the data around said faults. This automatic rerouting capability is the subject of the present invention.
摘要翻译：一种用于提高可靠性同时降低总冗余成本的计算机架构。 HUB和街道结构将多个共享公共汽车称为街道，其中多个智能交换元件称为HUB。街道是用于在HUB元素之间传输数据的总线。 HUB元素能够将数据导向街道结构并将所述数据传送到期望的目的地。系统设计人员可以增加或减少HUB元素和街道的数量，以提高或降低特定计算机系统的可靠性和成本。此外，HUB元件具有内置优先级方案，用于允许在低优先级数据之前传输高优先级数据。最后，HUB元件具有自动检测系统中的故障的能力，并可以围绕所述故障重定向数据。这种自动重路由能力是本发明的主题。

5. 发明授权

US5471482A VLSI embedded RAM test 失效
标题翻译： VLSI嵌入式RAM测试
公开(公告)号：US5471482A
公开(公告)日：1995-11-28
申请号：US223435
申请日：1994-04-05
申请人： Larry L. Byers , Donald W. Mackenthun , Philip J. Fye , Gerald J. Maciona , Jeff A. Engel , Ferris T. Price, deceased , Dale K. Seppa
发明人： Larry L. Byers , Donald W. Mackenthun , Philip J. Fye , Gerald J. Maciona , Jeff A. Engel , Ferris T. Price, deceased , Dale K. Seppa
IPC分类号： G11C29/10 , G01R31/28 , G01R31/26 , G11C29/00
CPC分类号： G11C29/10
摘要： A method for comprehensively testing embedded RAM devices and a means for detecting if any of the cells within the embedded RAM devices have a slow write recovery time. The preferred mode of the present invention utilizes built-in self-test (BIST) techniques for testing the embedded RAM's within a VLSI device. In accordance with the present invention, a modified 5N march test sequence is performed on the embedded RAM devices. The modified 5N March test sequence is a simple algorithm implemented in programmable hardware that has the capability of ensuring that the embedded RAM devices are functional and that they meet the recovery time requirements. The preferred mode of the present invention uses this algorithm to determine if the embedded RAMs are operating properly before the VLSI devices are used in card assembly. However, this method can also be used after card assembly to monitor the embedded RAM's integrity.
摘要翻译：一种全面测试嵌入式RAM设备的方法和用于检测嵌入式RAM设备中的任何单元是否具有缓慢的写入恢复时间的装置。本发明的优选方式利用内置的自检（BIST）技术来测试VLSI设备内的嵌入式RAM。根据本发明，对嵌入式RAM设备执行修改后的5N行进测试序列。修改后的5N March测试序列是一种在可编程硬件中实现的简单算法，具有确保嵌入式RAM设备功能并满足恢复时间要求的能力。本发明的优选方式是在VLSI设备在卡组合中使用之前，使用该算法来确定嵌入式RAM是否正常工作。但是，这种方法也可以在卡组合后使用来监视嵌入式RAM的完整性。

6. 发明授权

US4528665A Gray code counter with error detector in a memory system 失效
标题翻译：带有错误检测器的格雷码计数器
公开(公告)号：US4528665A
公开(公告)日：1985-07-09
申请号：US491464
申请日：1983-05-04
申请人： Gary D. Burns , Donald W. Mackenthun , Scott D. Schaber
发明人： Gary D. Burns , Donald W. Mackenthun , Scott D. Schaber
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F11/1076
摘要： An improved dynamic memory system including through-checking and error detection of the refresh counter is described. A refresh counter that provides parity of the refresh count for through-checking, of refresh addresses is shown. Error detecting circuitry is utilized in conjunction with the refresh counter and the parity generating circuitry to detect errors in functionality of the refresh counter. The refresh counter is a Gray code counter constructed of a double rank of latches operable with code generating logic circuits for determining the sequence of generation of Gray code groupings.
摘要翻译：描述了包括刷新计数器的检查和错误检测的改进的动态存储器系统。显示一个刷新计数器，提供刷新计数的奇偶校验，用于刷新地址的通过检查。错误检测电路与刷新计数器和奇偶校验生成电路结合使用，以检测刷新计数器功能的错误。刷新计数器是由可以与代码生成逻辑电路一起使用的双重锁存器构成的格雷码计数器，用于确定格雷码分组生成的顺序。

7. 发明授权

US5495589A Architecture for smart control of bi-directional transfer of data 失效
标题翻译：用于智能控制数据双向传输的架构
公开(公告)号：US5495589A
公开(公告)日：1996-02-27
申请号：US173429
申请日：1993-12-23
申请人： Donald W. Mackenthun , Larry L. Byers , Gregory B. Wiedenman , Ferris T. Price, deceased
发明人： Donald W. Mackenthun , Larry L. Byers , Gregory B. Wiedenman , Ferris T. Price, deceased
IPC分类号： G06F11/20 , G06F13/00 , G06F15/173 , G06F15/76
CPC分类号： G06F15/17381
摘要： A computer architecture for providing enhanced reliability by coupling a plurality of commonly shared busses called streets with a plurality of smart switching elements called HUBs. The streets are bi-directional busses for transferring data between HUB elements. The HUB elements are capable of directing data across the street structures to the desired destination. The HUB elements have a built in priority scheme for allowing high priority data to be transferred before low priority data. The either increase or decrease the number of HUB elements and streets can be.
摘要翻译：一种用于通过将称为街道的多个公共共享总线与多个称为HUB的智能交换元件耦合来提供增强的可靠性的计算机体系结构。街道是用于在HUB元件之间传输数据的双向总线。 HUB元素能够将街道结构上的数据引导到所需的目的地。 HUB元件具有内置优先级方案，用于允许在低优先级数据之前传输高优先级数据。可以增加或减少HUB元素和街道的数量。

8. 发明授权

US4697233A Partial duplication of pipelined stack with data integrity checking 失效
标题翻译：流水线堆栈的部分重复与数据完整性检查
公开(公告)号：US4697233A
公开(公告)日：1987-09-29
申请号：US595864
申请日：1984-04-02
申请人： James H. Scheuneman , Joseph H. Meyer , Donald W. Mackenthun
发明人： James H. Scheuneman , Joseph H. Meyer , Donald W. Mackenthun
IPC分类号： G06F7/00 , G06F11/16 , G06F13/16 , G06F11/08 , G06F12/00
CPC分类号： G06F11/167 , G06F13/1615 , G06F7/00
摘要： An improved partially duplicated stack structure for ensuring data integrity through a pipelined stack is described. An improved virtual first-in first-out stack structure having a plurality of parallel stacks, each for storing predetermined segments of data signals from a total data word is described in conjunction with one or more associated compare stack structures which are commonly accessed during loading and reading the stack. The compare stack is arranged for storing predetermined selected bit groupings associated with each of the segments of data signals. The bit groupings from the compare stack are compared with like-situated bit groupings from the associated segments of data signals at readout. Failure of the bit-by-bit comparison results in an indication that a stack address decode error has occurred, thereby providing through-checking of the integrity of the functioning of the stack structures.
摘要翻译：描述了改进的部分重复的栈结构，用于通过流水线栈来确保数据完整性。结合一个或多个相关联的比较堆叠结构描述了具有多个并行堆栈的改进的虚拟先进先出堆栈结构，每个并行堆栈用于从总数据字存储预定段的数据信号，所述一个或多个相关联的比较堆栈结构在加载期间通常被访问，阅读堆栈比较堆栈被布置用于存储与数据信号的每个段相关联的预定选择的位分组。将来自比较堆栈的位分组与来自相关联的数据信号段的相似位分组进行比较。逐位比较的失败导致发生堆栈地址解码错误的指示，从而提供堆栈结构的功能的完整性的通过检查。

9. 发明授权

US06928517B1 Method for avoiding delays during snoop requests 失效
标题翻译：在窥探请求期间避免延迟的方法
公开(公告)号：US06928517B1
公开(公告)日：2005-08-09
申请号：US09651597
申请日：2000-08-30
申请人： Donald C. Englin , Donald W. Mackenthun , Kelvin S. Vartti
发明人： Donald C. Englin , Donald W. Mackenthun , Kelvin S. Vartti
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0811
摘要： A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from enhancing the response to SNOOP requests. To accomplish this, the system memory bus is provided separate and independent paths to the level two cache and tag memories. Therefore, SNOOP requests are permitted to directly access the tag memories without reference to the cache memory. Secondly, the SNOOP requests are given a higher priority than operations associated with local processor data requests. Though this may slow down the local processor, the remote processors have less wait time for SNOOP operations improving overall system performance.
摘要翻译：一种用于提高采用多级高速缓冲存储器系统的数据处理系统的效率的方法和装置。提高效率是由于增强了对SNOOP请求的响应。为了实现这一点，系统存储器总线被提供到二级高速缓存和标签存储器的独立和独立的路径。因此，SNOOP请求被允许直接访问标签存储器而不参考高速缓冲存储器。其次，SNOOP请求的优先级高于与本地处理器数据请求相关的操作。虽然这可能会减慢本地处理器的速度，但是远程处理器的SNOOP操作的等待时间较少，从而提高了系统的整体性能。

10. 发明授权

US06374332B1 Cache control system for performing multiple outstanding ownership requests 有权
公开(公告)号：US06374332B1
公开(公告)日：2002-04-16
申请号：US09409756
申请日：1999-09-30
申请人： Donald W. Mackenthun , Kelvin S. Vartti
发明人： Donald W. Mackenthun , Kelvin S. Vartti
IPC分类号： G06F1300
CPC分类号： G06F12/0828
摘要： An improved directory-based, hierarchical memory system is disclosed that is capable of simultaneously processing multiple ownership requests initiated by a processor that is coupled to the memory. An ownership request is initiated on behalf of a processor to obtain an exclusive copy of memory data that may then be modified by the processor. In the data processing system of the preferred embodiment, multiple processors are each coupled to a respective cache memory. These cache memories are further coupled to a hierarchical memory structure including a main memory and one or more additional intermediate levels of cache memory. As is known in the art, copies of addressable portions of the main memory may reside in one or more of the cache memories within the hierarchical memory system. A memory directory records the location and status of each addressable portion of memory so that coherency may be maintained. Prior to updating an addressable portion of memory in a respectively coupled cache, a processor must acquire an exclusively “owned” copy of the requested memory portion from the hierarchical memory. This is accomplished by issuing a request for ownership to the hierarchical memory. Return of ownership may impose memory latency for write requests. To reduce this latency, the current invention allows multiple requests for ownership to be initiated by a processor simultaneously. In the preferred embodiment, write request logic receives two pending write requests from a processor. For each request that is associated with an addressable memory location that is not yet owned by the processor, an associated ownership request is issued to the hierarchical memory. The requests are not processed in the respective cache memory until after the associated ownership grant is returned from the hierarchical memory system. Because ownership is not necessarily granted by the hierarchical memory in the order ownership requests are issued, control logic is provided to ensure that a local cache processes all write requests in time-order so that memory consistency is maintained. According to another aspect of the invention, read request logic is provided to allow a memory read request to by-pass all pending write requests previously issued by the same processor. In this manner, read operations are not affected by delays associated with ownership requests.

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