专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07853747B2 Method and system for using an external bus controller in embedded disk controllers 有权
标题翻译：在嵌入式磁盘控制器中使用外部总线控制器的方法和系统
公开(公告)号：US07853747B2
公开(公告)日：2010-12-14
申请号：US11803458
申请日：2007-05-15
申请人： Larry L. Byers , Joseba M. Desubijana , Gary R. Robeck , Fredarico E. Dutton
发明人： Larry L. Byers , Joseba M. Desubijana , Gary R. Robeck , Fredarico E. Dutton
IPC分类号： G06F13/14
CPC分类号： G06F3/0674 , G06F3/0626 , G06F3/0658 , G06F2213/0038
摘要： An embedded disk controller comprises a first processor in communication with a first bus and a second processor in communication with a second bus. An external bus controller (“EBC”) is located on the embedded disk controller, is coupled to an external bus and to at least one of the first bus and the second bus, and manages a plurality of memory devices external to the embedded disk controller via the external bus. A first one of the plurality of memory devices has at least one of different timing characteristics and a different data width than a second one of the plurality of memory devices.
摘要翻译：嵌入式盘控制器包括与第一总线通信的第一处理器和与第二总线通信的第二处理器。外部总线控制器（“EBC”）位于嵌入式磁盘控制器上，耦合到外部总线和第一总线和第二总线中的至少一个，并管理嵌入式磁盘控制器外部的多个存储器件通过外部总线。多个存储器件中的第一个具有与多个存储器件中的第二个不同的定时特性和不同数据宽度中的至少一个。

2. 发明授权

US07080188B2 Method and system for embedded disk controllers 有权
标题翻译：嵌入式磁盘控制器的方法和系统
公开(公告)号：US07080188B2
公开(公告)日：2006-07-18
申请号：US10385022
申请日：2003-03-10
申请人： Larry L. Byers , Paul B. Ricci , Joseph G. Kriscunas , Joseba M. Desubijana , Gary R. Robeck , Michael R. Spaur , David M. Purdham
发明人： Larry L. Byers , Paul B. Ricci , Joseph G. Kriscunas , Joseba M. Desubijana , Gary R. Robeck , Michael R. Spaur , David M. Purdham
IPC分类号： G06F13/36 , G06F13/24
CPC分类号： G06F3/0674 , G06F3/0626 , G06F3/0658 , G06F2213/0038
摘要： A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.
摘要翻译：提供了一种嵌入式磁盘控制器的系统。该系统包括可操作地耦合到高性能总线的第一主处理器; 操作地耦合到外围总线的第二处理器; 高性能和外设总线之间的接口桥; 外部总线控制器，耦合到高性能总线，并通过外部总线接口可操作地耦合到外部设备; 中断控制器模块，其可以向第一主处理器产生快速中断; 耦合到高性能和外围总线的历史模块，用于监视总线活动; 以及伺服控制器，其通过伺服控制器接口耦合到第二处理器，并向第二处理器提供实时伺服控制器信息。第二处理器可以是通过接口可操作地耦合到第一主处理器的数字信号处理器。

3. 发明授权

US5784712A Method and apparatus for locally generating addressing information for a memory access 失效
标题翻译：用于本地生成用于存储器访问的寻址信息的方法和装置
公开(公告)号：US5784712A
公开(公告)日：1998-07-21
申请号：US396677
申请日：1995-03-01
申请人： Larry L. Byers , Gary R. Robeck , Terry J. Brunmeier
发明人： Larry L. Byers , Gary R. Robeck , Terry J. Brunmeier
IPC分类号： G06F9/312 , G06F9/345 , G06F13/16 , G06F9/32
CPC分类号： G06F9/30043 , G06F13/1631 , G06F9/345 , G06F9/3861
摘要： A method and apparatus for efficiently reading or writing a number of successive address locations within a memory. In an exemplary embodiment, a processor or the like may not be required to provide an address to a memory unit for each read and/or write operation when successive address locations are accessed. That is, for multiple memory accesses which access successive address locations, the processor or the like may provide an initial address but thereafter may not be required to provide subsequent addresses to the memory unit. The subsequent addresses may be automatically generated by an automatic-increment block.
摘要翻译：一种用于有效地读取或写入存储器内的多个连续地址位置的方法和装置。在示例性实施例中，当访问连续的地址位置时，可能不需要处理器等来为每个读取和/或写入操作向存储器单元提供地址。也就是说，对于访问连续地址位置的多个存储器访问，处理器等可以提供初始地址，但此后可能不需要向存储器单元提供后续地址。随后的地址可以由自动增量块自动生成。

4. 发明授权

US5784393A Method and apparatus for providing fault detection to a bus within a computer system 失效
标题翻译：用于向计算机系统内的总线提供故障检测的方法和装置
公开(公告)号：US5784393A
公开(公告)日：1998-07-21
申请号：US396680
申请日：1995-03-01
申请人： Larry L. Byers , Gary R. Robeck , Ronald W. Splett
发明人： Larry L. Byers , Gary R. Robeck , Ronald W. Splett
IPC分类号： G06F11/10
CPC分类号： G06F11/10
摘要： A method and apparatus for providing fault detection to a corresponding bus when one or more of the users connected to the bus does not have a fault detection capability provided therein. Further, the present invention may provide a method and apparatus for performing fault detection on a corresponding bus when the width of the bus is insufficient to accommodate a number of parity bits. In an exemplary embodiment, a selected one of the number of users may validate all bus transmissions via a number of transceivers, regardless of which user has a fault detection capability provided therein. In another exemplary embodiment of the present invention, a transmitting user may provide a data word and a number of corresponding parity bits. The transmitting user may provide the data word to the bus while storing the corresponding number of parity bits therein. The data word may be provided back to the transmitting user via the corresponding transceivers wherein the transmitting user may check the data word against the number of parity bits previously generated by the transmitting user.
摘要翻译：当连接到总线的一个或多个用户不具有其中提供的故障检测能力时，向相应总线提供故障检测的方法和装置。此外，本发明可以提供一种用于当总线的宽度不足以容纳多个奇偶校验位时在相应总线上执行故障检测的方法和装置。在示例性实施例中，所选择的一个用户可以经由多个收发器验证所有总线传输，而不管哪个用户具有其中提供的故障检测能力。在本发明的另一示例性实施例中，发送用户可以提供数据字和多个对应的奇偶校验位。发送用户可以在存储相应数量的奇偶校验位的同时向总线提供数据字。数据字可以经由相应的收发器提供给发送用户，其中发送用户可以根据发送用户先前生成的奇偶校验位的数量来检查数据字。

5. 发明授权

US5680537A Method and apparatus for isolating an error within a computer system that transfers data via an interface device 失效
标题翻译：用于隔离通过接口设备传送数据的计算机系统内的错误的方法和装置
公开(公告)号：US5680537A
公开(公告)日：1997-10-21
申请号：US396678
申请日：1995-03-01
申请人： Larry L. Byers , Gary R. Robeck , Terry J. Brunmeier , John A. Miller
发明人： Larry L. Byers , Gary R. Robeck , Terry J. Brunmeier , John A. Miller
IPC分类号： G06F11/22 , G06F13/00
CPC分类号： G06F11/2268
摘要： A method and apparatus for isolating an error in a system having a controller or the like which access a user via an interface device. The controller or the like may be coupled to the interface device via a first bus and the interface device may be coupled to the user via a second bus. The controller or the like may detect an error in a data transfer from the user to the controller via the interface device, and may isolate the error to the second bus/interface device or the first bus/controller. This up-front error isolation may reduce the amount of analysis required by a service technician after a corresponding PC board or the like is removed from the system, thereby reducing the cost thereof.
摘要翻译：一种用于隔离具有通过接口设备访问用户的控制器等的系统中的错误的方法和装置。控制器等可以经由第一总线耦合到接口设备，并且接口设备可以经由第二总线耦合到用户。控制器等可以通过接口设备检测从用户到控制器的数据传输中的错误，并且可以将错误与第二总线/接口设备或第一总线/控制器隔离。这种前期错误隔离可以减少在从系统移除相应的PC板等之后服务技术人员所需的分析量，从而降低其成本。

6. 发明授权

US5422915A Fault tolerant clock distribution system 失效
标题翻译：容错时钟分配系统
公开(公告)号：US5422915A
公开(公告)日：1995-06-06
申请号：US172661
申请日：1993-12-23
申请人： Larry L. Byers , Thomas T. Kubista , Gregory B. Wiedenman
发明人： Larry L. Byers , Thomas T. Kubista , Gregory B. Wiedenman
IPC分类号： G06F1/12 , G06F11/16 , H02J9/06 , H04J3/06 , H04L7/04 , H04L7/00
CPC分类号： G06F11/1604 , G06F1/12 , H02J9/06 , G06F11/20 , H04J3/0688 , Y10T307/62
摘要： A fault tolerant multiple phase clock distribution system for providing synchronized clock signals to multiple circuit loads. Multiple electrically isolated power domains are powered by redundant AC and DC power sourcing circuits to ensure continued operation upon partial failure of the AC or DC power sourcing circuits. Multiple oscillators from the multiple power domains are synchronized to produce a group of simultaneously synchronized clock signals. Multiple synchronized clock signals from this group are then selected by selection circuitry and selection control circuitry, and are distributed to multiple circuit loads requiring simultaneous synchronization. The oscillator circuitry, synchronization circuitry, selection circuitry, and distribution circuitry is all provided in redundant form, so that the partial failure of any of the circuitry will not result in a system stop. Error recovery circuitry monitors for proper synchronization of the synchronized clock signals, and provides for automatic or manual error recovery upon detection of a synchronization error. A single phase synchronized clock signal is generated to minimize synchronization complexities, and circuitry exists at the circuit loads to generate multiple phase enable signals to emulate a multiple phase clock.
摘要翻译：一种用于向多个电路负载提供同步时钟信号的容错多相时钟分配系统。多个电隔离的电源域由冗余的交流和直流电源电路供电，以确保在交流或直流电源电路部分故障时持续运行。来自多个电源域的多个振荡器被同步以产生一组同时同步的时钟信号。然后由选择电路和选择控制电路选择来自该组的多个同步时钟信号，并分配给需要同步同步的多个电路负载。振荡器电路，同步电路，选择电路和分配电路都以冗余形式提供，使得任何电路的部分故障不会导致系统停止。错误恢复电路监视同步时钟信号的正确同步，并在检测到同步错误时提供自动或手动错误恢复。生成单相同步时钟信号以最小化同步复杂度，并且在电路负载处存在电路以产生多相启动信号以仿真多相时钟。

7. 发明授权

US5142629A System for interconnecting MSUs to a computer system 失效
标题翻译：将MSU与计算机系统相互连接的系统
公开(公告)号：US5142629A
公开(公告)日：1992-08-25
申请号：US403640
申请日：1989-09-06
申请人： Larry L. Byers , Joseba M. Desubijana
发明人： Larry L. Byers , Joseba M. Desubijana
IPC分类号： G06F13/40 , G06F15/173
CPC分类号： G06F15/17368 , G06F13/4022
摘要： An improved system for interconnecting main storage units is provided wherein each main storage unit is provided with a support control card and each support control card is provided with interface connection means comprising X-1 number of interfaces where X is a value equal to the number of MSUs. And means for enabling the connection of the interfaces between different pairs of MSUs to operably connect any number of said X number of MSUs to a plurality of data processors employing X(X-1)/2 pairs of cables.
摘要翻译：提供了一种用于互连主存储单元的改进的系统，其中每个主存储单元设置有支持控制卡，并且每个支持控制卡设置有包括X-1个接口的接口连接装置，其中X等于 MSU。以及用于使得能够连接不同成对MSU之间的接口的装置可操作地将任何数量的所述X个数量的MSU连接到采用X（X-1）/ 2对电缆的多个数据处理器。

8. 发明授权

US08788641B1 Small form factor interface module 有权
标题翻译：小尺寸接口模块
公开(公告)号：US08788641B1
公开(公告)日：2014-07-22
申请号：US11936631
申请日：2007-11-07
申请人： Joseba M. Desubijana , Larry L. Byers , Gary R. Robeck
发明人： Joseba M. Desubijana , Larry L. Byers , Gary R. Robeck
IPC分类号： G06F15/173
CPC分类号： G06F13/126 , Y02D10/14
摘要： Systems, apparatuses, and methods for an interface module to interface with an enclosure services processor are described herein. The interface module may include one or more state machines configured to provide an enclosure service operation. Provision of this enclosure service operation may be at least partially unsupervised by a control processor requesting the enclosure service operation. Other embodiments may be described and claimed.
摘要翻译：本文描述了用于接口模块与机箱服务处理器接口的系统，设备和方法。接口模块可以包括被配置为提供机箱服务操作的一个或多个状态机。可以由控制处理器至少部分地提供这种机箱服务操作，该控制处理器请求机箱服务操作。可以描述和要求保护其他实施例。

9. 发明授权

US07219182B2 Method and system for using an external bus controller in embedded disk controllers 有权
标题翻译：在嵌入式磁盘控制器中使用外部总线控制器的方法和系统
公开(公告)号：US07219182B2
公开(公告)日：2007-05-15
申请号：US10385056
申请日：2003-03-10
申请人： Larry L. Byers , Joseba M. Desubijana , Gary R. Robeck , Fredarico E. Dutton
发明人： Larry L. Byers , Joseba M. Desubijana , Gary R. Robeck , Fredarico E. Dutton
IPC分类号： G06F13/14
CPC分类号： G06F3/0674 , G06F3/0626 , G06F3/0658 , G06F2213/0038
摘要： A system and method for an embedded disk controller is provided. The embedded disk controller includes a main processor in communication with a first bus. A second processor communicates with a second bus. An external bus interface controller (“EBC”) located on the embedded disk controller manages a plurality of memory devices external to the system embedded disk controller via an external bus interface and coupled to the first bus and an external bus. Each of the plurality of memory devices has at least one of different timing characteristics and different data widths. The EBC is coupled to the first bus and stores at least one of a segment descriptor register and at least a device range register.
摘要翻译：提供了一种用于嵌入式磁盘控制器的系统和方法。嵌入式盘控制器包括与第一总线通信的主处理器。第二处理器与第二总线进行通信。位于嵌入式磁盘控制器上的外部总线接口控制器（“EBC”）通过外部总线接口管理系统嵌入式磁盘控制器外部的多个存储器件，并耦合到第一总线和外部总线。多个存储器件中的每一个具有不同的定时特性和不同的数据宽度中的至少一个。 EBC耦合到第一总线并且存储段描述符寄存器和至少一个器件范围寄存器中的至少一个。

10. 发明授权

US07080174B1 System and method for managing input/output requests using a fairness throttle 失效
标题翻译：使用公平节流管理输入/输出请求的系统和方法
公开(公告)号：US07080174B1
公开(公告)日：2006-07-18
申请号：US10028161
申请日：2001-12-21
申请人： Lloyd E. Thorsbakken , Larry L. Byers
发明人： Lloyd E. Thorsbakken , Larry L. Byers
IPC分类号： G06F13/00 , G06F13/36 , G06F13/362
CPC分类号： G06F13/364
摘要： A system and method for providing a desired degree of fairness of access to data transfer resources by a plurality of command-initiating bus agents. A bus arbiter allocates general ownership of the bus to one of a plurality of bus agents, and a fairness module imposes a desired degree of fairness to the data transfer resources by mandating data transfer resource access to bus agents whose commands have been subjected to a retry response. The degree of fairness is controllable, in order to appropriately balance the desired throughput and data transfer resource allocation for a particular application.
摘要翻译：一种用于通过多个命令发起总线代理提供对数据传输资源的访问的期望程度的公平性的系统和方法。总线仲裁器将总线的一般所有权分配给多个总线代理之一，并且公平模块通过强制数据传输资源访问其命令已经经过重试的总线代理向数据传输资源施加期望的公平性响应。公平性是可控的，以便适当平衡特定应用的期望吞吐量和数据传输资源分配。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式