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1. 发明授权

US06868482B1 Method and apparatus for parallel store-in second level caching 有权
标题翻译：并行存储二级缓存的方法和装置
公开(公告)号：US06868482B1
公开(公告)日：2005-03-15
申请号：US09506038
申请日：2000-02-17
申请人： Donald W. Mackenthun , Mitchell A. Bauman , Donald C. Englin
发明人： Donald W. Mackenthun , Mitchell A. Bauman , Donald C. Englin
IPC分类号： G06F12/08 , G06F11/16
CPC分类号： G06F12/0804 , G06F12/0811 , G06F12/0891
摘要： Each dual multi-processing system has a number of processors, with each processor having a store in first-level write through cache to a second-level cache. A third-level memory is shared by the dual system with the first-level and second-level caches being globally addressable to all of the third-level memory. Processors can write through to the local second-level cache and have access to the remote second-level cache via the local storage controller. A coherency scheme for the dual system provides each second-level cache with indicators for each cache line showing which ones are valid and which ones have been modified or are different than what is reflected in the corresponding third level memory. The flush apparatus uses these two indicators to transfer all cache lines that are within the remote memory address range and have been modified, back to the remote memory prior to dynamically removing the local cache resources due to either system maintenance or dynamic partitioning.
摘要翻译：每个双重多处理系统具有多个处理器，每个处理器具有通过缓存的第一级写入到第二级缓存的存储。第三级存储器由双系统共享，第一级和第二级高速缓存可全局寻址到所有第三级存储器。处理器可以写入本地二级缓存，并通过本地存储控制器访问远程二级缓存。双系统的一致性方案为每个二级缓存提供每个高速缓存行的指示符，其中显示哪些是有效的，哪些已被修改或不同于相应的第三级存储器中反映的指示。冲洗装置使用这两个指示器将在远程存储器地址范围内的所有高速缓存行传送到远程存储器，然后由于系统维护或动态分区而动态地删除本地缓存资源。

2. 发明授权

US6122711A Method of and apparatus for store-in second level cache flush 失效
标题翻译：存储二级缓存刷新的方法和设备
公开(公告)号：US6122711A
公开(公告)日：2000-09-19
申请号：US779472
申请日：1997-01-07
申请人： Donald W. Mackenthun , Mitchell A. Bauman , Donald C. Englin
发明人： Donald W. Mackenthun , Mitchell A. Bauman , Donald C. Englin
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0804 , G06F12/0811 , G06F12/0891
摘要： Flush apparatus for a dual multi-processing system. Each dual multi-processing system has a number of processors, with each processor having a store in first-level write through cache to a second-level cache. A third-level memory is shared by the dual system with the first-level and second-level caches being globally addressable to all of the third-level memory. Processors can write through to the local second-level cache and have access to the remote second-level cache via the local storage controller. A coherency scheme for the dual system provides each second-level cache with indicators for each cache line showing which ones are valid and which ones have been modified or are different than what is reflected in the corresponding third level memory. The flush apparatus uses these two indicators to transfer all cache lines that are within the remote memory address range and have been modified, back to the remote memory prior to dynamically removing the local cache resources due to either system maintenance or dynamic partitioning. The flush apparatus prevents the loss of system data during such a process due to the inherent nature of a store in second level cache.
摘要翻译：用于双重多处理系统的冲洗装置。每个双重多处理系统具有多个处理器，每个处理器具有通过缓存的第一级写入到第二级缓存的存储。第三级存储器由双系统共享，第一级和第二级高速缓存可全局寻址到所有第三级存储器。处理器可以写入本地二级缓存，并通过本地存储控制器访问远程二级缓存。双系统的一致性方案为每个二级缓存提供每个高速缓存行的指示符，其中显示哪些是有效的，哪些已被修改或不同于相应的第三级存储器中反映的指示。冲洗装置使用这两个指示器将在远程存储器地址范围内的所有高速缓存行传送到远程存储器，然后由于系统维护或动态分区而动态地删除本地缓存资源。由于第二级高速缓存中的存储的固有特性，冲洗装置在这种处理期间防止了系统数据的丢失。

3. 发明授权

US5946710A Selectable two-way, four-way double cache interleave scheme 失效
标题翻译：可选双向，四路双缓存交错方案
公开(公告)号：US5946710A
公开(公告)日：1999-08-31
申请号：US748772
申请日：1996-11-14
申请人： Mitchell A. Bauman , Donald C. Englin
发明人： Mitchell A. Bauman , Donald C. Englin
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F12/0851
摘要： Method and apparatus for maximizing cache memory throughput in a system where a plurality of requesters may contend for access to a same memory simultaneously. The memory utilizes an interleaved addressing scheme wherein each memory segment is associated with a separate queuing structure and the memory is mapped noncontiguously within the same segment so that all segments are accessed equally. Throughput is maximized as the plurality of requesters are queued evenly throughout the system.
摘要翻译：用于在多个请求者可能竞争同时访问相同存储器的系统中最大化高速缓冲存储器吞吐量的方法和装置。存储器利用交错寻址方案，其中每个存储器段与单独的排队结构相关联，并且存储器被不连续地映射在相同的段内，使得所有段被平等地访问。吞吐量最大化，因为多个请求者在整个系统中均匀排队。

4. 发明授权

US5875462A Multi-processor data processing system with multiple second level caches mapable to all of addressable memory 失效
标题翻译：具有多个二级缓存的多处理器数据处理系统可映射到所有可寻址存储器
公开(公告)号：US5875462A
公开(公告)日：1999-02-23
申请号：US579897
申请日：1995-12-28
申请人： Mitchell A. Bauman , Donald C. Englin , Mark L. Balding
发明人： Mitchell A. Bauman , Donald C. Englin , Mark L. Balding
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0811 , G06F12/0813 , G06F12/0822
摘要： A cache architecture for a multiprocessor data processing system. The cache architecture includes multiple first-level caches, two second-level caches, and main storage that is addressable by each of the processors. Each first-level cache is dedicated to a respective one of the processors. Each of the second-level caches is coupled to the other second-level cache, coupled to the main storage, and coupled to predetermined ones of the first-level caches. The range of cacheable addresses for both of the second-level caches encompasses the entire address space of the main storage. Each of the second-level caches may be viewed as dedicated for write access to the set of processors associated with the predetermined set of first-level caches, and shared for read access to the other set of processors. The dedicated and shared nature enhances system efficiency. The cache architecture includes coherency control that filters invalidation traffic between the second-level caches. The filtering of invalidation traffic enhances system efficiency and is accomplished by tracking which second-level cache has the most recent version of the cached data.
摘要翻译：用于多处理器数据处理系统的高速缓存架构。缓存架构包括多个第一级高速缓存，两个二级高速缓存和可由每个处理器寻址的主存储器。每个第一级缓存专用于相应的一个处理器。每个第二级高速缓存耦合到另一个二级高速缓存，耦合到主存储器，并且耦合到第一级高速缓存中的预定的高速缓存。二级缓存的可缓存地址的范围包括主存储器的整个地址空间。每个二级高速缓存可以被视为专用于对与预定的一级高速缓存集合相关联的一组处理器的写入访问，并且被共享用于对另一组处理器的读取访问。专用和共享的性质提高了系统效率。缓存体系结构包括一致性控制，用于过滤二级缓存之间的无效流量。无效流量的过滤增强了系统效率，并且通过跟踪哪个二级缓存具有最新版本的缓存数据来实现。

5. 发明授权

US5860093A Reduced instruction processor/storage controller interface 失效
标题翻译：减少指令处理器/存储控制器接口
公开(公告)号：US5860093A
公开(公告)日：1999-01-12
申请号：US785873
申请日：1997-01-21
申请人： Donald C. Englin , Mitchell A. Bauman
发明人： Donald C. Englin , Mitchell A. Bauman
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0877 , G06F12/0851
摘要： Method and apparatus for reducing address/function transfer pins in a system where cache memories in a system controller are accessed by a number of instruction processors. The reduction of pins is obtained by using two data transfers. The increase in data addressing time, which would otherwise occur using two data transfers, is reduced to nearly the time of the data transfers themselves by responding to the first data transfer while the second data transfer is taking place.
摘要翻译：用于减少系统控制器中的高速缓存存储器被多个指令处理器访问的系统中的地址/功能传输引脚的方法和装置。通过使用两个数据传输来获得引脚的减少。数据寻址时间的增加，否则将使用两个数据传输发生，在第二次数据传输发生时，通过响应第一次数据传输，自身数据传输的时间减少到几乎接近时间。

6. 发明授权

US5875201A Second level cache having instruction cache parity error control 失效
标题翻译：具有指令缓存奇偶校验错误控制的二级缓存
公开(公告)号：US5875201A
公开(公告)日：1999-02-23
申请号：US777037
申请日：1996-12-30
申请人： Mitchell A. Bauman , Donald W. Mackenthun , Gary J. Lucas , James L. Federici
发明人： Mitchell A. Bauman , Donald W. Mackenthun , Gary J. Lucas , James L. Federici
IPC分类号： G06F11/10 , G06F11/00 , G11C29/00
CPC分类号： G06F11/1008 , G06F11/1064
摘要： Method and apparatus for detecting and correcting memory storage data errors in a system utilizing parity error detection. An error detected in the memory storage device results in a parity error being reported, thereby causing the corresponding address location to be deactivated. Once deactivated, no further reading or writing is performed at that address location for a predetermined time period. The parity error reporting and address deactivation is accomplished without an access time penalty and requires a reduced number of I/O pins.
摘要翻译：用于检测和校正使用奇偶校验错误检测的系统中的存储器存储数据错误的方法和装置。在存储器存储装置中检测到的错误导致正在报告奇偶校验错误，从而导致对应的地址位置被去激活。一旦停用，在该地址位置不进行进一步的读取或写入达预定的时间段。奇偶校验错误报告和地址禁用在没有访问时间损失的情况下完成，并且需要减少I / O引脚数。

7. 发明授权

US07343515B1 System and method for performing error recovery in a data processing system having multiple processing partitions 有权
标题翻译：用于在具有多个处理分区的数据处理系统中执行错误恢复的系统和方法
公开(公告)号：US07343515B1
公开(公告)日：2008-03-11
申请号：US10954842
申请日：2004-09-30
申请人： R. Lee Gilbertson , Mitchell A. Bauman , Penny L. Svenkeson
发明人： R. Lee Gilbertson , Mitchell A. Bauman , Penny L. Svenkeson
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0712 , G06F11/0724
摘要： A system and method is disclosed for performing error recovery in a data processing system that supports multiple processing partitions. One or more processors and I/O modules, as well as a portion of the address space of a main memory, is allocated to each partition. In this type of configuration, requests generated by units of multiple partitions are processed by the same queue and state logic of the main memory. When a failure occurs within one processing partition, one or more units are identified as being directly affected by the fault. All requests and responses from, and to, the affected units, as well as any logical residue of these requests and responses are removed from the shared memory queue and state logic in a manner that allows the other partition to continue issuing requests and responses to the memory in a normal manner that does not involve recovery operations.
摘要翻译：公开了一种用于在支持多个处理分区的数据处理系统中执行错误恢复的系统和方法。一个或多个处理器和I / O模块以及主存储器的地址空间的一部分被分配给每个分区。在这种类型的配置中，由多个分区的单元生成的请求由主存储器的相同队列和状态逻辑处理。当在一个处理分区内发生故障时，一个或多个单元被识别为直接受故障影响。受影响单位的所有请求和响应以及这些请求和响应的任何逻辑残差都以共享内存队列和状态逻辑的方式被删除，从而允许其他分区继续发出请求和响应记忆以不涉及恢复操作的正常方式。

8. 发明授权

US07167955B1 System and method for testing and initializing directory store memory 有权
标题翻译：用于测试和初始化目录存储器的系统和方法
公开(公告)号：US07167955B1
公开(公告)日：2007-01-23
申请号：US10745372
申请日：2003-12-23
申请人： Justin S. Neils , John S. Jensen , Mitchell A. Bauman , Eugene A. Rodi , Bart E. Reigstad
发明人： Justin S. Neils , John S. Jensen , Mitchell A. Bauman , Eugene A. Rodi , Bart E. Reigstad
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F11/1008 , G06F2212/1032
摘要： A system and method for testing and/or initializing a Directory Store in a directory-based coherent memory. In one illustrative embodiment, the directory-based coherent memory includes a Main Store for storing a number of data entries, a Directory Store for storing the directory state for at least some of the data entries in the Main Store, and a next state block for determining a next directory state for a requested data entry in response to a memory request. To provide access to the Directory Store, and in one illustrative embodiment, a selector is provided for selecting either the next directory state value provided by the next state block or another predetermined value. The other predetermined value may be, for example, a fixed data pattern, a variable data pattern, a specified value, or any other value suitable for initializing and/or testing the Directory Store. The output of the selector may be written to the Directory Store.
摘要翻译：用于在基于目录的连贯内存中测试和/或初始化目录存储的系统和方法。在一个说明性实施例中，基于目录的相干存储器包括用于存储多个数据条目的主存储器，用于存储主存储器中的至少一些数据条目的目录状态的目录存储器，以及下一个状态块响应于存储器请求确定所请求的数据条目的下一目录状态。为了提供对目录存储的访问，并且在一个说明性实施例中，提供了选择器，用于选择由下一个状态块提供的下一个目录状态值或另一个预定值。另一个预定值可以是例如固定数据模式，可变数据模式，指定值或适用于初始化和/或测试目录库的任何其他值。选择器的输出可能会写入目录存储。

9. 发明授权

US06594785B1 System and method for fault handling and recovery in a multi-processing system having hardware resources shared between multiple partitions 有权
标题翻译：具有在多个分区之间共享的硬件资源的多处理系统中的故障处理和恢复的系统和方法
公开(公告)号：US06594785B1
公开(公告)日：2003-07-15
申请号：US09561270
申请日：2000-04-28
申请人： Roger L. Gilbertson , Mitchell A. Bauman , Penny L. Svenkeson , James L. DePenning , Michael L. Haupt , Donald Kalvestrand , Daniel S. Tokoly , Frederick G. Fellenser , Maria A. Liedman
发明人： Roger L. Gilbertson , Mitchell A. Bauman , Penny L. Svenkeson , James L. DePenning , Michael L. Haupt , Donald Kalvestrand , Daniel S. Tokoly , Frederick G. Fellenser , Maria A. Liedman
IPC分类号： H02H305
CPC分类号： G06F11/0772 , G06F11/0712 , G06F11/0724 , G06F11/0793
摘要： Poisoning of specific memory locations as a process when a part of a multiprocessor computer system becomes faulty leads to ability to isolate specific data owned by individual failing units even in a shared memory area. Also continuous processing by non-failing units is allowable. A support processor handles non-immediate problems and allows resetting of memory locations formerly owned by failed units.
摘要翻译：当多处理器计算机系统的一部分变得有故障时，将特定存储器位置中毒作为过程导致即使在共享存储器区域中也能够分离由单个故障单元拥有的特定数据的能力。也可以由非故障单元进行连续处理。支持处理器处理非直接问题，并允许重置以前由故障单元拥有的存储器位置。

10. 发明授权

US06587931B1 Directory-based cache coherency system supporting multiple instruction processor and input/output caches 失效
标题翻译：基于目录的高速缓存一致性系统支持多指令处理器和输入/输出缓存
公开(公告)号：US06587931B1
公开(公告)日：2003-07-01
申请号：US09001598
申请日：1997-12-31
申请人： Mitchell A. Bauman , Eugene A. Rodi , Douglas E. Morrissey
发明人： Mitchell A. Bauman , Eugene A. Rodi , Douglas E. Morrissey
IPC分类号： G06F1208
CPC分类号： G06F12/0817 , G06F12/0886 , G06F2212/621
摘要： A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/O) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more IPs and to the shared main memory for caching units of data referred to as cache lines. The system further includes one or more I/O memories within ones of the I/O units, each I/O memory being coupled to the shared main memory for storing cache lines retrieved from the shared main memory. Coherency is maintained through the use of a central directory which stores status for each of the cache lines in the system. The status indicates the identity of the IP caches and the I/O memories having valid copies of a given cache line, and further identifies a set of access privileges, that is, the cache line “state”, associated with the cache line. The cache line states are used to implement a state machine which tracks the cache lines and ensures only valid copies of are maintained within the memory system. According to another aspect of the system, the main memory performs continuous tracking and control functions for all cache lines residing in the IP caches. In contrast, the system maintains tracking and control functions for only predetermined cache lines provided to the I/O units so that system overhead may be reduced. The coherency system further supports multiple heterogeneous instruction processors which operate on cache lines of different sizes.
摘要翻译：公开了一种基于目录的高速缓存一致性系统，用于具有通过共享主存储器耦合的多个指令处理器（IP）和多个输入/输出（I / O）单元的数据处理系统。该系统包括一个或多个IP高速缓冲存储器，每个IP缓存存储器分别耦合到一个或多个IP和共享主存储器，用于高速缓存被称为高速缓存线的数据单元。该系统还包括一个或多个I / O单元内的I / O存储器，每个I / O存储器耦合到共享主存储器，用于存储从共享主存储器检索的高速缓存线。通过使用存储系统中每个缓存行的状态的中央目录来维护一致性。该状态表示IP高速缓存和具有给定高速缓存行的有效副本的I / O存储器的身份，并进一步标识与高速缓存行相关联的一组访问权限，即高速缓存行“状态”。高速缓存行状态用于实现跟踪高速缓存行的状态机，并且仅确保在存储器系统内维护的有效副本。根据系统的另一方面，主存储器对驻留在IP高速缓存中的所有高速缓存行执行连续跟踪和控制功能。相比之下，系统仅为提供给I / O单元的预定高速缓存行维护跟踪和控制功能，从而可以减少系统开销。一致性系统还支持在不同大小的高速缓存线上运行的多个异构指令处理器。

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