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1. 发明授权

US5471482A VLSI embedded RAM test 失效
标题翻译： VLSI嵌入式RAM测试
公开(公告)号：US5471482A
公开(公告)日：1995-11-28
申请号：US223435
申请日：1994-04-05
申请人： Larry L. Byers , Donald W. Mackenthun , Philip J. Fye , Gerald J. Maciona , Jeff A. Engel , Ferris T. Price, deceased , Dale K. Seppa
发明人： Larry L. Byers , Donald W. Mackenthun , Philip J. Fye , Gerald J. Maciona , Jeff A. Engel , Ferris T. Price, deceased , Dale K. Seppa
IPC分类号： G11C29/10 , G01R31/28 , G01R31/26 , G11C29/00
CPC分类号： G11C29/10
摘要： A method for comprehensively testing embedded RAM devices and a means for detecting if any of the cells within the embedded RAM devices have a slow write recovery time. The preferred mode of the present invention utilizes built-in self-test (BIST) techniques for testing the embedded RAM's within a VLSI device. In accordance with the present invention, a modified 5N march test sequence is performed on the embedded RAM devices. The modified 5N March test sequence is a simple algorithm implemented in programmable hardware that has the capability of ensuring that the embedded RAM devices are functional and that they meet the recovery time requirements. The preferred mode of the present invention uses this algorithm to determine if the embedded RAMs are operating properly before the VLSI devices are used in card assembly. However, this method can also be used after card assembly to monitor the embedded RAM's integrity.
摘要翻译：一种全面测试嵌入式RAM设备的方法和用于检测嵌入式RAM设备中的任何单元是否具有缓慢的写入恢复时间的装置。本发明的优选方式利用内置的自检（BIST）技术来测试VLSI设备内的嵌入式RAM。根据本发明，对嵌入式RAM设备执行修改后的5N行进测试序列。修改后的5N March测试序列是一种在可编程硬件中实现的简单算法，具有确保嵌入式RAM设备功能并满足恢复时间要求的能力。本发明的优选方式是在VLSI设备在卡组合中使用之前，使用该算法来确定嵌入式RAM是否正常工作。但是，这种方法也可以在卡组合后使用来监视嵌入式RAM的完整性。

2. 发明授权

US5416362A Transparent flip-flop 失效
标题翻译：透明触发器
公开(公告)号：US5416362A
公开(公告)日：1995-05-16
申请号：US119957
申请日：1993-09-10
申请人： Larry L. Byers , Fernando W. Arraut , Dale K. Seppa
发明人： Larry L. Byers , Fernando W. Arraut , Dale K. Seppa
IPC分类号： H03K3/037 , H03K3/289
CPC分类号： H03K3/0372
摘要： An apparatus for a transparent master/slave flip-flop logic circuit including a single line connected to the transparency input of the logic macro so that when the line is active input data will pass through the flip-flop, unless the scan signal is also active, in which case the flip-flop will return to a clocked (latching) status.
摘要翻译：一种用于透明主/从触发器逻辑电路的装置，包括连接到逻辑宏的透明度输入的单线，使得当线是有源时，输入数据将通过触发器，除非扫描信号也是有效的在这种情况下，触发器将返回到时钟（锁存）状态。

3. 发明授权

US4209846A Memory error logger which sorts transient errors from solid errors 失效
标题翻译：内存错误记录器，它从固体错误中排除瞬态错误
公开(公告)号：US4209846A
公开(公告)日：1980-06-24
申请号：US856706
申请日：1977-12-02
申请人： Dale K. Seppa
发明人： Dale K. Seppa
IPC分类号： G06F12/16 , G06F11/00 , G06F11/07 , G06F11/10 , G06F11/34
CPC分类号： G06F11/1024 , G06F11/073 , G06F11/0751 , G06F11/076
摘要： A method of and an apparatus for distinguishing between transient and solid errors within a single-error-correcting semiconductor memory storage unit (MSU) comprised of a plurality of large scale integrated (LSI) bit planes and for notifying the associated data processing system of required maintenance action. The method utilizes an error logging store (ELS) that is comprised of a plurality of memory error registers one for each separately associated word group within the MSU. Each memory error register contains storage for: (1) the Error Correction Code (ECC) defined, failing bit position; (2) the single bit error counter; (3) the multiple single bit error tag; and (4) the multiple bit error tag. Upon detection of an error within a word group, the associated memory error register is accessed to determine the history of previously detected errors within that word group. The central processing unit (CPU) is notified by a priority interrupt of the error status of that word group if:(1) the number of consecutive errors within a word group at the same bit position reaches a set threshold indicating the high probability of a solid single bit error; or(2) the error detected is in a different bit position from that previously identified as a solid single bit error indicating the high probability of a future uncorrectable multiple-bit error.This method and apparatus notifies the CPU of the likelihood of imminent uncorrectable errors and maintains a history of the error indications that lead to that conclusion.
摘要翻译：一种用于区分由多个大规模集成（LSI）位平面组成的单错误校正半导体存储器存储单元（MSU）内的瞬态和固态误差的方法和装置，并用于将相关联的数据处理系统通知所需的维护行动。该方法利用由多个存储器错误寄存器组成的错误记录存储器（ELS），每个存储器错误寄存器用于MSU内的每个单独关联的字组。每个存储器错误寄存器包含以下存储器：（1）定义的纠错码（ECC），故障位位置; （2）单位错误计数器; （3）多个单位错误标签; 和（4）多位错误标签。在检测到字组内的错误之后，访问相关联的存储器错误寄存器以确定该字组中先前检测到的错误的历史。如果：（1）在相同比特位置的单词组内的连续错误的数量达到设定的阈值，表示高字节的概率，中央处理单元（CPU）通过该字组的错误状态的优先中断被通知固体单位错误; 或者（2）检测到的错误与先前识别为固体单位错误的位置不同，表示未来不可纠正的多位错误的高概率。该方法和装置向CPU通报即将发生的不可纠正错误的可能性，并保持导致该结论的错误指示的历史。

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