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1. 发明授权

US08367493B1 Void free interlayer dielectric 有权
标题翻译：无空隙层间电介质
公开(公告)号：US08367493B1
公开(公告)日：2013-02-05
申请号：US11109719
申请日：2005-04-20
申请人： Minh Van Ngo , Hirokazu Tokuno , Angela T. Hui , Wenmei Li , Hsiao-Han Thio
发明人： Minh Van Ngo , Hirokazu Tokuno , Angela T. Hui , Wenmei Li , Hsiao-Han Thio
IPC分类号： H01L21/8238
CPC分类号： H01L23/291 , H01L21/823425 , H01L21/823475 , H01L27/11521 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.
摘要翻译：一种制造非易失性存储器件的方法包括形成多个存储单元。该方法还包括在存储器单元上沉积第一介电层，其中第一介电层是具有基本均匀厚度的共形层。该方法还包括在第一介电层上沉积第二电介质层。第一和第二电介质层一起形成没有空隙的层间电介质。

2. 发明授权

US08658496B2 Etch stop layer for memory cell reliability improvement 有权
标题翻译：蚀刻停止层，提高记忆体的可靠性
公开(公告)号：US08658496B2
公开(公告)日：2014-02-25
申请号：US13617291
申请日：2012-09-14
申请人： Hiroyuki Kinoshita , Angela Hui , Hsiao-Han Thio , Kuo-Tung Chang , Minh Van Ngo , Hiroyuki Ogawa
发明人： Hiroyuki Kinoshita , Angela Hui , Hsiao-Han Thio , Kuo-Tung Chang , Minh Van Ngo , Hiroyuki Ogawa
IPC分类号： H01L21/336
CPC分类号： H01L21/0217 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.
摘要翻译：提供存储器件和制造存储器件的方法。在基板上形成第一电介质层，在第一电介质层上形成浮栅，在浮栅上形成第二电介质层，在第二电介质层上形成控制栅，还包括至少一层，保形膜形成在存储器件的表面上。

3. 发明授权

US08319266B1 Etch stop layer for memory cell reliability improvement 有权
标题翻译：蚀刻停止层，提高记忆体的可靠性
公开(公告)号：US08319266B1
公开(公告)日：2012-11-27
申请号：US11008240
申请日：2004-12-10
申请人： Hiroyuki Kinoshita , Angela Hui , Hsiao-Han Thio , Kuo-Tung Chang , Minh Van Ngo , Hiroyuki Ogawa
发明人： Hiroyuki Kinoshita , Angela Hui , Hsiao-Han Thio , Kuo-Tung Chang , Minh Van Ngo , Hiroyuki Ogawa
IPC分类号： H01L29/788
CPC分类号： H01L21/0217 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.
摘要翻译：提供存储器件和制造存储器件的方法。在基板上形成第一电介质层，在第一电介质层上形成浮栅，在浮栅上形成第二电介质层，在第二电介质层上形成控制栅，还包括至少一层，保形膜形成在存储器件的表面上。

4. 发明授权

US06670227B1 Method for fabricating devices in core and periphery semiconductor regions using dual spacers 有权
标题翻译：使用双间隔物在芯部和外围半导体区域中制造器件的方法
公开(公告)号：US06670227B1
公开(公告)日：2003-12-30
申请号：US10361455
申请日：2003-02-10
申请人： Hsiao-Han Thio , Kei-Leong Ho
发明人： Hsiao-Han Thio , Kei-Leong Ho
IPC分类号： H01L218238
CPC分类号： H01L27/11534 , H01L21/823418 , H01L21/823468 , H01L27/105 , H01L27/11526 , H01L29/6653
摘要： For fabricating a first device within a core region and a second device within a periphery region, of a semiconductor substrate, disposable spacers having a first width are formed at sidewalls of a first gate stack of the core region and a second gate stack of the periphery region. Drain and source junctions of the second device are formed in the periphery region to the sides of the disposable spacers of the second gate stack. The disposable spacers are removed and permanent spacers having a second width are formed at the sidewalls of the first and second gate stacks, with the second width being less than the first width. Silicide is formed with an exposed portion of a drain bit line junction within the core region after forming the permanent spacers.
摘要翻译：为了在芯区域内的第一器件和周边区域内的第二器件的半导体衬底中制造具有第一宽度的一次性间隔物，形成在芯区域的第一栅极堆叠的侧壁和周边的第二栅极堆叠地区。第二器件的漏极和源极结形成在第二栅极堆叠的一次性间隔物的边缘的周边区域中。去除一次性间隔件，并且在第一和第二栅极堆叠的侧壁处形成具有第二宽度的永久性间隔物，其中第二宽度小于第一宽度。在形成永久间隔物之后，在芯区域内形成硅化物与漏极位线结的露出部分。

5. 发明授权

US06696331B1 Method of protecting a stacked gate structure during fabrication 有权
标题翻译：在制造期间保护堆叠栅极结构的方法
公开(公告)号：US06696331B1
公开(公告)日：2004-02-24
申请号：US10217807
申请日：2002-08-12
申请人： Nian Yang , Zhigang Wang , Hsiao-Han Thio
发明人： Nian Yang , Zhigang Wang , Hsiao-Han Thio
IPC分类号： H01L218238
CPC分类号： H01L21/28273 , H01L29/42324
摘要： A method of protecting a stacked gate structure of a flash memory device during fabrication is disclosed. Additionally, the manner of protecting the stacked gate structure during fabrication is simple to implement and is cost-effective. In particular, a protective layer is deposited on the stacked gate structure to protect the stacked gate structure before a resist removal process is performed a second time. Despite undergoing two resist removal processes, the stacked gate structure suffers less damage than the convention fabrication techniques, increasing the yield and reliability of the flash memory device.
摘要翻译：公开了一种在制造期间保护闪存器件的堆叠栅极结构的方法。此外，在制造期间保护堆叠栅极结构的方式易于实现并且是成本有效的。特别地，在堆叠的栅极结构上沉积保护层，以在第二次执行抗蚀剂去除处理之前保护堆叠的栅极结构。尽管经历了两次抗蚀剂去除工艺，堆叠的栅极结构比常规的制造技术遭受的损坏更小，从而提高了闪存器件的产量和可靠性。

6. 发明申请

US20070052002A1 Junction leakage suppression in memory devices 有权
标题翻译：存储器件中的结漏电抑制
公开(公告)号：US20070052002A1
公开(公告)日：2007-03-08
申请号：US11152375
申请日：2005-06-15
申请人： Shibly Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
发明人： Shibly Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
IPC分类号： H01L29/788
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.
摘要翻译：存储器件包括衬底和形成在衬底中的源区和漏区。源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

7. 发明授权

US08536011B2 Junction leakage suppression in memory devices 有权
标题翻译：存储器件中的结漏电抑制
公开(公告)号：US08536011B2
公开(公告)日：2013-09-17
申请号：US13074836
申请日：2011-03-29
申请人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
发明人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
IPC分类号： H01L21/336 , H01L21/44 , H01L29/788
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.
摘要翻译：存储器件包括衬底和形成在衬底中的源区和漏区。源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

8. 发明授权

US06716710B1 Using a first liner layer as a spacer in a semiconductor device 有权
标题翻译：在半导体器件中使用第一衬垫层作为间隔物
公开(公告)号：US06716710B1
公开(公告)日：2004-04-06
申请号：US10126207
申请日：2002-04-19
申请人： Hsiao-Han Thio , Nian Yang , Zhigang Wang
发明人： Hsiao-Han Thio , Nian Yang , Zhigang Wang
IPC分类号： H01L21336
CPC分类号： H01L29/6656 , H01L21/76224 , H01L21/823468 , H01L21/823481
摘要： A method of fabricating a semiconductor device. A first layer comprising a first material is deposited to a first thickness on a sidewall of a stacked gate. A second layer comprising a second material is deposited over the first layer. The second layer is deposited without the first layer being etched; hence, the first thickness is unchanged along the sidewall. The second layer is reduced to a second thickness along the sidewall. The first layer and the second layer in combination form a spacer along the sidewall that has a thickness corresponding to the first thickness and the second thickness. Thus, the spacer can be formed using a single etch, reducing the number of processing steps. In addition, the first layer protects shallow trench filler material from gouging during the etch.
摘要翻译：一种制造半导体器件的方法。包括第一材料的第一层在堆叠栅极的侧壁上沉积到第一厚度。包含第二材料的第二层沉积在第一层上。沉积第二层，而不蚀刻第一层; 因此，第一厚度沿侧壁不变。第二层沿着侧壁被还原成第二厚度。第一层和第二层组合形成沿着侧壁的间隔物，其具有对应于第一厚度和第二厚度的厚度。因此，间隔物可以使用单一蚀刻形成，减少了处理步骤的数量。此外，第一层在蚀刻期间保护浅沟槽填料材料免于气刨。

9. 发明授权

US07939440B2 Junction leakage suppression in memory devices 有权
标题翻译：存储器件中的结漏电抑制
公开(公告)号：US07939440B2
公开(公告)日：2011-05-10
申请号：US11152375
申请日：2005-06-15
申请人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
发明人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
IPC分类号： H01L21/425 , H01L21/44
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.
摘要翻译：存储器件包括衬底和形成在衬底中的源区和漏区。源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

10. 发明授权

US06689666B1 Replacing a first liner layer with a thicker oxide layer when forming a semiconductor device 有权
标题翻译：在形成半导体器件时，用较厚的氧化物层代替第一衬里层
公开(公告)号：US06689666B1
公开(公告)日：2004-02-10
申请号：US10126841
申请日：2002-04-19
申请人： Hsiao-Han Thio , Nian Yang , Zhigang Wang
发明人： Hsiao-Han Thio , Nian Yang , Zhigang Wang
IPC分类号： H01L21336
CPC分类号： H01L29/66553 , H01L21/28247 , H01L21/823468 , H01L21/823481 , H01L29/6656
摘要： A method (300) of fabricating a semiconductor device. An oxide layer (220) is produced on a sidewall (211) of a stacked gate (210) and over a shallow trench (212) adjacent to the stacked gate. The thickness of the oxide layer is sufficient to withstand a subsequent etch. A first layer (222) of material is deposited over the oxide layer. In a first etch, the first layer is reduced to a first thickness along the sidewall. Because the oxide layer has a depth sufficient to withstand the first etch, the oxide layer serves as a protective layer for the shallow trench during the first etch. Accordingly, a protective liner layer does not need to be deposited in addition to the oxide layer.
摘要翻译：一种制造半导体器件的方法（300）。在层叠栅极（210）的侧壁（211）上和与堆叠栅极相邻的浅沟槽（212）之上产生氧化物层（220）。氧化物层的厚度足以承受随后的蚀刻。材料的第一层（222）沉积在氧化物层上。在第一蚀刻中，第一层沿侧壁被还原成第一厚度。因为氧化物层具有足以承受第一蚀刻的深度，所以氧化物层在第一次蚀刻期间用作浅沟槽的保护层。因此，除了氧化物层之外，不需要沉积保护衬垫层。

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