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1. 发明申请

US20070052002A1 Junction leakage suppression in memory devices 有权
标题翻译：存储器件中的结漏电抑制
公开(公告)号：US20070052002A1
公开(公告)日：2007-03-08
申请号：US11152375
申请日：2005-06-15
申请人： Shibly Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
发明人： Shibly Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
IPC分类号： H01L29/788
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.
摘要翻译：存储器件包括衬底和形成在衬底中的源区和漏区。源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

2. 发明授权

US08536011B2 Junction leakage suppression in memory devices 有权
标题翻译：存储器件中的结漏电抑制
公开(公告)号：US08536011B2
公开(公告)日：2013-09-17
申请号：US13074836
申请日：2011-03-29
申请人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
发明人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
IPC分类号： H01L21/336 , H01L21/44 , H01L29/788
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.
摘要翻译：存储器件包括衬底和形成在衬底中的源区和漏区。源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

3. 发明授权

US07939440B2 Junction leakage suppression in memory devices 有权
标题翻译：存储器件中的结漏电抑制
公开(公告)号：US07939440B2
公开(公告)日：2011-05-10
申请号：US11152375
申请日：2005-06-15
申请人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
发明人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
IPC分类号： H01L21/425 , H01L21/44
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.
摘要翻译：存储器件包括衬底和形成在衬底中的源区和漏区。源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

4. 发明授权

US08912014B1 Controlling the latchup effect 有权
标题翻译：控制闭锁效果
公开(公告)号：US08912014B1
公开(公告)日：2014-12-16
申请号：US11333208
申请日：2006-01-18
申请人： Chuan Lin , Dong-Hyuk Ju , Imran Khan , Jun Kang , Shibly S. Ahmed
发明人： Chuan Lin , Dong-Hyuk Ju , Imran Khan , Jun Kang , Shibly S. Ahmed
IPC分类号： H01L21/66
CPC分类号： G01R31/27 , G01R31/2884 , H01L22/12 , H01L22/34 , H01L27/0921
摘要： A method includes varying spacing between at least one of a source region or a drain region and a well contact region to create a group of configurations. The method further includes determining an effect of latchup on each configuration.
摘要翻译：一种方法包括在源极区域或漏极区域中的至少一个与阱接触区域之间改变间隔以产生一组构型。该方法还包括确定闭锁对每个配置的影响。

5. 发明申请

US20080268630A1 METHOD TO OBTAIN MULTIPLE GATE THICKNESSES USING IN-SITU GATE ETCH MASK APPROACH 有权
标题翻译：使用现场浇口掩模方法获取多个浇口厚度的方法
公开(公告)号：US20080268630A1
公开(公告)日：2008-10-30
申请号：US11741998
申请日：2007-04-30
申请人： Imran Khan , Ahmed Shibly , Dong-Hyuk Ju
发明人： Imran Khan , Ahmed Shibly , Dong-Hyuk Ju
IPC分类号： H01L21/3205
CPC分类号： H01L21/31144 , H01L21/823456 , H01L21/823462 , H01L21/82385 , H01L21/823857
摘要： Making gates having multiple thicknesses on the same substrate in a given process flow is provided. For example, a method of making a semiconductor structure having at least two gates of different thickness involves forming a first gate layer having a first thickness; patterning a first hard mask over a portion of the first gate layer to define a first gate underneath the first hard mask having a first gate thickness; forming a second gate layer having a second thickness over the first gate layer and the first hard mask; patterning a second hard mask over a portion of the second gate layer to define a second gate underneath the second hard mask having a second gate thickness; removing portions of the first gate layer and the second gate layer that are not under the first hard mask and the second hard mask; and removing the first hard mask and the second hard mask to provide two gates of different thicknesses.
摘要翻译：提供了在给定的工艺流程中在同一基板上制造具有多个厚度的浇口。例如，制造具有不同厚度的至少两个栅极的半导体结构的方法包括形成具有第一厚度的第一栅极层; 在第一栅极层的一部分上图案化第一硬掩模以限定具有第一栅极厚度的第一硬掩模下面的第一栅极; 在所述第一栅极层和所述第一硬掩模上形成具有第二厚度的第二栅极层; 在第二栅极层的一部分上图案化第二硬掩模以限定具有第二栅极厚度的第二硬掩模下方的第二栅极; 去除不在第一硬掩模下面的第一栅极层和第二栅极层的部分和第二硬掩模; 以及去除第一硬掩模和第二硬掩模以提供不同厚度的两个栅极。

6. 发明授权

US08530977B1 Apparatus and method for a metal oxide semiconductor field effect transistor with source side punch-through protection implant 有权
标题翻译：具有源极穿通保护植入物的金属氧化物半导体场效应晶体管的装置和方法
公开(公告)号：US08530977B1
公开(公告)日：2013-09-10
申请号：US10609159
申请日：2003-06-27
申请人： Imran Khan , Richard M. Fastow , Dong-Hyuk Ju
发明人： Imran Khan , Richard M. Fastow , Dong-Hyuk Ju
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/66492 , H01L21/26586 , H01L29/66575 , H01L29/66659 , H01L29/7835
摘要： A metal oxide semiconductor field effect transistor (MOSFET) with source side punch-through protection implant. Specifically, the MOSFET comprises a semiconductor substrate, a gate stack formed above the semiconductor substrate, source and drain regions, and a protection implant. The semiconductor substrate comprises a first p-type doping concentration. The source and drain regions comprise an n-type doping concentration, and are formed on opposing sides of the gate stack in the semiconductor substrate. The protection implant comprises a second p-type doping concentration, and is formed in the semiconductor substrate under the source region and surrounds the source region in order to protect the source region from the depletion region corresponding to the drain region.
摘要翻译：具有源极穿通保护植入物的金属氧化物半导体场效应晶体管（MOSFET）。具体地，MOSFET包括半导体衬底，形成在半导体衬底上的栅极堆叠，源极和漏极区域以及保护注入。半导体衬底包括第一p型掺杂浓度。源极和漏极区域包括n型掺杂浓度，并且形成在半导体衬底中的栅极堆叠的相对侧上。保护注入包括第二p型掺杂浓度，并且形成在源极区域下方的半导体衬底中并且围绕源极区域以保护源极区域与对应于漏极区域的耗尽区域保护。

7. 发明授权

US07776696B2 Method to obtain multiple gate thicknesses using in-situ gate etch mask approach 有权
标题翻译：使用原位栅极蚀刻掩模法获得多个栅极厚度的方法
公开(公告)号：US07776696B2
公开(公告)日：2010-08-17
申请号：US11741998
申请日：2007-04-30
申请人： Imran Khan , Ahmed Shibly , Dong-Hyuk Ju
发明人： Imran Khan , Ahmed Shibly , Dong-Hyuk Ju
IPC分类号： H01L21/8234
CPC分类号： H01L21/31144 , H01L21/823456 , H01L21/823462 , H01L21/82385 , H01L21/823857
摘要： Making gates having multiple thicknesses on the same substrate in a given process flow is provided. For example, a method of making a semiconductor structure having at least two gates of different thickness involves forming a first gate layer having a first thickness; patterning a first hard mask over a portion of the first gate layer to define a first gate underneath the first hard mask having a first gate thickness; forming a second gate layer having a second thickness over the first gate layer and the first hard mask; patterning a second hard mask over a portion of the second gate layer to define a second gate underneath the second hard mask having a second gate thickness; removing portions of the first gate layer and the second gate layer that are not under the first hard mask and the second hard mask; and removing the first hard mask and the second hard mask to provide two gates of different thicknesses.
摘要翻译：提供了在给定的工艺流程中在同一基板上制造具有多个厚度的浇口。例如，制造具有不同厚度的至少两个栅极的半导体结构的方法包括形成具有第一厚度的第一栅极层; 在第一栅极层的一部分上图案化第一硬掩模以限定具有第一栅极厚度的第一硬掩模下面的第一栅极; 在所述第一栅极层和所述第一硬掩模上形成具有第二厚度的第二栅极层; 在第二栅极层的一部分上图案化第二硬掩模以限定具有第二栅极厚度的第二硬掩模下方的第二栅极; 去除不在第一硬掩模下面的第一栅极层和第二栅极层的部分和第二硬掩模; 以及去除第一硬掩模和第二硬掩模以提供不同厚度的两个栅极。

8. 发明申请

US20120228704A1 High-Voltage MOSFET with High Breakdown Voltage and Low On-Resistance and Method of Manufacturing the Same 审中-公开
标题翻译：具有高击穿电压和低导通电阻的高压MOSFET及其制造方法
公开(公告)号：US20120228704A1
公开(公告)日：2012-09-13
申请号：US13041512
申请日：2011-03-07
申请人： Dong-Hyuk Ju
发明人： Dong-Hyuk Ju
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/402 , H01L29/0878 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66689 , H01L29/7816
摘要： A high-voltage transistor is formed in a deep well of a first conductivity type that has been formed in a semiconductor substrate or epitaxial layer of a second conductivity type. A body region of the second conductivity type is formed in the deep well, into which a source region of the first conductivity type is formed. A drain region of the first conductivity type is formed in the deep well and separated from the body region by a drift region in the deep well. A gate dielectric layer is formed over the body region, and a first polysilicon layer formed over the gate dielectric layer embodies the gate of the transistor. The field plate dielectric layer is formed over the drift region after the gate has been formed. Finally, the field plate dielectric is covered by a second polysilicon layer having a field plate positioned over the field plate dielectric layer in the drift region.
摘要翻译：高压晶体管形成在已经形成在半导体衬底或第二导电类型的外延层中的第一导电类型的深阱中。第二导电类型的体区形成在深阱中，形成第一导电类型的源极区。第一导电类型的漏极区域形成在深井中，并且通过深井中的漂移区域与身体区域分离。栅极电介质层形成在体区上，并且形成在栅极电介质层上的第一多晶硅层体现晶体管的栅极。在形成栅极之后，在漂移区上形成场板电介质层。最后，场板电介质被第二多晶硅层覆盖，该第二多晶硅层具有位于漂移区中的场板电介质层上的场板。

9. 发明授权

US06713819B1 SOI MOSFET having amorphized source drain and method of fabrication 失效
标题翻译：具有非晶化源极漏极和制造方法的SOI MOSFET
公开(公告)号：US06713819B1
公开(公告)日：2004-03-30
申请号：US10118364
申请日：2002-04-08
申请人： William G. En , Dong-Hyuk Ju , Srinath Krishnan
发明人： William G. En , Dong-Hyuk Ju , Srinath Krishnan
IPC分类号： H01L2976
CPC分类号： H01L29/78609 , H01L21/84 , H01L27/1203 , H01L29/78612
摘要： An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.
摘要翻译：一种以绝缘体半导体形式形成的集成电路。集成电路包括设置在绝缘层上的半导体材料层，其中设置在基板上的绝缘层。提供第一和第二MOSFET，使得第一MOSFET的源极和漏极中的一个被设置为邻近第二MOSFET的源极和漏极之一。在半导体材料层中形成非晶区域并从半导体材料层的上表面延伸到隔离层。非晶区域形成在第一MOSFET的源极和漏极之一的结晶部分和第二MOSFET的源极和漏极之一的结晶部分之间。

10. 发明授权

US06277698B1 Method of manufacturing semiconductor devices having uniform, fully doped gate electrodes 有权
标题翻译：具有均匀的，完全掺杂的栅电极的半导体器件的制造方法
公开(公告)号：US06277698B1
公开(公告)日：2001-08-21
申请号：US09382580
申请日：1999-08-25
申请人： Emi Ishida , Dong-Hyuk Ju , David Wu
发明人： Emi Ishida , Dong-Hyuk Ju , David Wu
IPC分类号： H01L21336
CPC分类号： H01L29/66583 , H01L21/823842
摘要： A semiconductor device is provided with a gate electrode having a substantially rectangular profile by forming a dielectric film prior to depositing the gate electrode layer. The dielectric film is patterned and etched to form regions having a rectangular profile separated by open regions. A gate electrode layer is then deposited followed by planarization to form gate electrodes having a substantially rectangular profile.
摘要翻译：通过在沉积栅极电极层之前形成电介质膜，半导体器件设置有具有大致矩形轮廓的栅电极。对电介质膜进行图案化和蚀刻以形成具有由开放区域分开的矩形轮廓的区域。然后沉积栅极电极层，然后平坦化以形成具有基本上矩形轮廓的栅电极。

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