专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07297592B1 Semiconductor memory with data retention liner 有权
标题翻译：具有数据保留衬垫的半导体存储器
公开(公告)号：US07297592B1
公开(公告)日：2007-11-20
申请号：US11195201
申请日：2005-08-01
申请人： Minh Van Ngo , Arvind Halliyal , Tazrien Kamal , Hidehiko Shiraiwa , Rinji Sugino , Dawn Hopper , Pei-Yuan Gao
发明人： Minh Van Ngo , Arvind Halliyal , Tazrien Kamal , Hidehiko Shiraiwa , Rinji Sugino , Dawn Hopper , Pei-Yuan Gao
IPC分类号： H01L21/8247
CPC分类号： H01L21/28282 , H01L21/3185 , H01L27/11568
摘要： A manufacturing method for a dual bit flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer with the depositing performed without using ammonia at an ultra-slow deposition rate. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, high-density data retention liner to reduce charge loss, covers the wordline and the charge-trapping dielectric layer. An interlayer dielectric layer is deposited over the data retention liner.
摘要翻译：一种用于双位闪速存储器的制造方法包括提供半导体衬底和沉积电荷捕获电介质层，其中沉积是以超低沉积速率使用氨而不使用氨。植入第一和第二位线，并存放字线层。硬掩模层沉积在字线层上。光刻胶沉积在字线层上并用于形成硬掩模。去除光致抗蚀剂。使用硬掩模处理字线层以形成字线，并且去除硬掩模。减少氢，高密度数据保持衬垫以减少电荷损失，覆盖字线和电荷捕获电介质层。层间绝缘层沉积在数据保持衬里上。

2. 发明授权

US06900121B1 Laser thermal annealing to eliminate oxide voiding 失效
标题翻译：激光热退火以消除氧化物空隙
公开(公告)号：US06900121B1
公开(公告)日：2005-05-31
申请号：US10097015
申请日：2002-03-14
申请人： Minh Van Ngo , Arvind Halliyal , Dawn Hopper
发明人： Minh Van Ngo , Arvind Halliyal , Dawn Hopper
IPC分类号： H01L21/3105 , H01L21/4763 , H01L21/768 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L21/3105 , H01L21/76819 , H01L27/115
摘要： Oxide voiding is eliminated was substantially reduced by laser thermal annealing. Embodiments include fabricating flash memory devices by depositing a BPSG over spaced apart transistors as the first interlayer dielectric with voids formed in gaps between the transistors and laser thermal annealing the BPSG layer in flowing nitrogen to eliminate or substantially reduce the voids by reflowing the BPSG layer.
摘要翻译：通过激光热退火基本上减少了氧化物空隙。实施例包括通过在间隔开的晶体管上沉积BPSG来制造闪速存储器件，作为第一层间电介质，其中形成在晶体管之间的间隙中的空隙，并且在流动的氮气中激发热退火BPSG层，以通过回流BPSG层来消除或基本上减少空隙。

3. 发明授权

US06693004B1 Interfacial barrier layer in semiconductor devices with high-K gate dielectric material 有权
标题翻译：具有高K栅极电介质材料的半导体器件中的界面阻挡层
公开(公告)号：US06693004B1
公开(公告)日：2004-02-17
申请号：US10085318
申请日：2002-02-27
申请人： Arvind Halliyal , Joong S. Jeon , Minh Van Ngo , William G. En , Effiong Ibok
发明人： Arvind Halliyal , Joong S. Jeon , Minh Van Ngo , William G. En , Effiong Ibok
IPC分类号： H01L218242
CPC分类号： H01L21/28194 , H01L21/2807 , H01L21/28273 , H01L21/28282 , H01L21/28291 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A semiconductor device and a process for fabricating the device, including, in one embodiment, a silicon substrate; a first interfacial barrier layer on the silicon substrate, in which the first interfacial barrier layer may include aluminum oxide, silicon nitride, silicon oxynitride or a mixture thereof; and a layer of a high-K dielectric material. The device may further include a second interfacial barrier layer on the high-K dielectric material layer, and may further include a polysilicon or polysilicon-germanium gate electrode formed on the second interfacial barrier layer.
摘要翻译：一种半导体器件和用于制造器件的工艺，在一个实施例中包括硅衬底; 硅衬底上的第一界面阻挡层，其中第一界面阻挡层可以包括氧化铝，氮化硅，氮氧化硅或其混合物; 和一层高K电介质材料。该器件还可以包括在高K电介质材料层上的第二界面阻挡层，并且还可以包括形成在第二界面阻挡层上的多晶硅或多晶硅 - 锗栅电极。

4. 发明授权

US06617215B1 Memory wordline hard mask 有权
标题翻译：内存字线硬掩模
公开(公告)号：US06617215B1
公开(公告)日：2003-09-09
申请号：US10109235
申请日：2002-03-27
申请人： Arvind Halliyal , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang , Emmanuil Lingunis , Angela T. Hui , Jusuke Ogura
发明人： Arvind Halliyal , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang , Emmanuil Lingunis , Angela T. Hui , Jusuke Ogura
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/0332 , H01L21/32139 , H01L27/115
摘要： A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric material. First and second bitlines are implanted and a wordline material is deposited. A hard mask material is deposited over the wordline material. The hard mask material is of a material having the characteristic of being deposited rather than grown. A photoresist material is deposited over the wordline material and is patterned to form a patterned hard mask. The patterned photoresist material is removed. The wordline material is processed using the patterned hard mask to form a wordline. The patterned hard mask material is removed.
摘要翻译：用于MirrorBit（R）闪存的制造方法包括提供半导体衬底和沉积电荷俘获电介质材料。植入第一和第二位线，并存放字线材料。硬掩模材料沉积在字线材料上。硬掩模材料是具有沉积而不是生长的特征的材料。光致抗蚀剂材料沉积在字线材料上并被图案化以形成图案化的硬掩模。去除图案化的光致抗蚀剂材料。使用图案化的硬掩模处理字线材料以形成字线。去除图案化的硬掩模材料。

5. 发明授权

US06509282B1 Silicon-starved PECVD method for metal gate electrode dielectric spacer 失效
标题翻译：用于金属栅极电介质间隔物的硅缺陷PECVD方法
公开(公告)号：US06509282B1
公开(公告)日：2003-01-21
申请号：US09994128
申请日：2001-11-26
申请人： Minh Van Ngo , Arvind Halliyal
发明人： Minh Van Ngo , Arvind Halliyal
IPC分类号： H01L2131
CPC分类号： H01L21/3145 , C23C16/308 , H01L21/28079 , H01L21/28088 , H01L2924/0002 , H01L2924/00
摘要： A method of making a semiconductor device including a metal gate electrode on a semiconductor substrate with a silicon oxynitride spacer formed on a surface of the metal gate electrode, wherein an interface of the silicon oxynitride spacer and the metal gate electrode is substantially free of metal silicide. The process includes steps of forming a metal gate electrode on a semiconductor substrate; forming by PECVD on a surface of the metal gate electrode a silicon oxynitride spacer, wherein the silicon oxynitride spacer is formed under initially silicon-starved conditions in which a first quantity of at least one silicon-containing material is provided to a PECVD apparatus which is reduced relative to an amount of at least one other reactant, as a result of which substantially no silicide is formed.
摘要翻译：一种在半导体衬底上制造半导体器件的方法，该半导体器件在金属栅电极的表面上形成有氧氮化硅间隔物，其中氧氮化硅间隔物和金属栅电极的界面基本上不含金属硅化物。该方法包括在半导体衬底上形成金属栅电极的步骤; 通过PECVD在金属栅电极的表面上形成氮氧化硅间隔物，其中在最初的硅饥饿条件下形成氮氧化硅间隔物，其中第一量的至少一种含硅材料被提供给PECVD装置，该PECVD装置是相对于至少一种其它反应物的量减少，结果基本上没有形成硅化物。

6. 发明授权

US06828199B2 Monos device having buried metal silicide bit line 有权
标题翻译：具有埋置金属硅化物位线的单体器件
公开(公告)号：US06828199B2
公开(公告)日：2004-12-07
申请号：US10022798
申请日：2001-12-20
申请人： Jusuke Ogura , Mark T. Ramsbey , Arvind Halliyal , Zoran Krivokapic , Minh Van Ngo , Nicholas H. Tripisas
发明人： Jusuke Ogura , Mark T. Ramsbey , Arvind Halliyal , Zoran Krivokapic , Minh Van Ngo , Nicholas H. Tripisas
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/743 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： A MONOS device and method for making the device has a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer, formed on a substrate. A recess is created through the ONO layer and in the substrate. A metal silicide bit line is formed in the recess and bit line oxide is formed on top of the metal silicide. A word line is formed over the ONO layer and the bit line oxide, and a low resistance silicide is provided on top of the word line. The silicide is formed by laser thermal annealing, for example.
摘要翻译：用于制造该器件的MONOS器件和方法具有形成在衬底上的电荷捕获介电层，例如氧化物 - 氮化物 - 氧化物（ONO）层。通过ONO层和衬底产生凹陷。在凹部中形成金属硅化物位线，并且在金属硅化物的顶部上形成位线氧化物。在ONO层和位线氧化物之间形成字线，并且在字线的顶部提供低电阻硅化物。硅化物例如由激光热退火形成。

7. 发明授权

US06645882B1 Preparation of composite high-K/standard-K dielectrics for semiconductor devices 有权
标题翻译：制备用于半导体器件的复合高K /标准K电介质
公开(公告)号：US06645882B1
公开(公告)日：2003-11-11
申请号：US10051790
申请日：2002-01-17
申请人： Arvind Halliyal , Joong S. Jeon , Minh Van Ngo , Robert B. Ogle
发明人： Arvind Halliyal , Joong S. Jeon , Minh Van Ngo , Robert B. Ogle
IPC分类号： H01L21469
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/316 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of fabricating the semiconductor device having a composite dielectric layer including steps of providing a semiconductor substrate; depositing on the semiconductor substrate alternating sub-layers of a first dielectric material and a second dielectric material to form a layered dielectric structure having at least two sub-layers of at least one of the first dielectric material and the second dielectric material, in which one of the first dielectric material and the second dielectric material is a high-K dielectric material and an other of the first dielectric material and the second dielectric material is a standard-K dielectric material comprising aluminum oxide; and annealing the layered dielectric structure at an elevated temperature to form a composite dielectric layer.
摘要翻译：一种半导体器件和制造具有复合介电层的半导体器件的方法，包括提供半导体衬底的步骤; 在所述半导体衬底上沉积交替的第一电介质材料和第二介电材料的子层，以形成具有至少两个第二电介质材料和所述第二电介质材料中的至少一个的子层的层状电介质结构，其中一个所述第一电介质材料和所述第二电介质材料是高K电介质材料，所述第一电介质材料和所述第二电介质材料中的另一个是包含氧化铝的标准K电介质材料; 以及在升高的温度下退火所述层状电介质结构以形成复合介电层。

8. 发明授权

US06605848B2 Semiconductor device with metal gate electrode and silicon oxynitride spacer 有权
公开(公告)号：US06605848B2
公开(公告)日：2003-08-12
申请号：US10246267
申请日：2002-09-18
申请人： Minh Van Ngo , Arvind Halliyal
发明人： Minh Van Ngo , Arvind Halliyal
IPC分类号： H01L2976
CPC分类号： H01L21/3145 , C23C16/308 , H01L21/28079 , H01L21/28088 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including a semiconductor substrate; a metal gate electrode; and a silicon oxynitride spacer formed on a surface of the metal gate electrode, wherein an interface of the silicon oxynitride spacer and the metal gate electrode is substantially free of metal silicide. In one embodiment, the silicon oxynitride spacer includes a first portion and a second portion, in which the first portion is formed under starving silicon conditions.

9. 发明授权

US08368219B2 Buried silicide local interconnect with sidewall spacers and method for making the same 有权
标题翻译：埋入硅化物与侧壁间隔物的局部互连及其制造方法
公开(公告)号：US08368219B2
公开(公告)日：2013-02-05
申请号：US13281491
申请日：2011-10-26
申请人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jusuke Ogura
发明人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jusuke Ogura
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/28518 , H01L21/743 , H01L21/76895
摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
摘要翻译：掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。凹槽里填充有抛光的填充材料。然后去除硬掩模以形成硅化物掩埋的局部互连。

10. 发明授权

US08049334B1 Buried silicide local interconnect with sidewall spacers and method for making the same 有权
标题翻译：埋入硅化物与侧壁间隔物的局部互连及其制造方法
公开(公告)号：US08049334B1
公开(公告)日：2011-11-01
申请号：US12843131
申请日：2010-07-26
申请人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jusuke Ogura
发明人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jusuke Ogura
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/28518 , H01L21/743 , H01L21/76895
摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
摘要翻译：掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。凹槽里填充有抛光的填充材料。然后去除硬掩模以形成硅化物掩埋的局部互连。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式