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1. 发明授权

US08368219B2 Buried silicide local interconnect with sidewall spacers and method for making the same 有权
标题翻译：埋入硅化物与侧壁间隔物的局部互连及其制造方法
公开(公告)号：US08368219B2
公开(公告)日：2013-02-05
申请号：US13281491
申请日：2011-10-26
申请人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jusuke Ogura
发明人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jusuke Ogura
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/28518 , H01L21/743 , H01L21/76895
摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
摘要翻译：掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。凹槽里填充有抛光的填充材料。然后去除硬掩模以形成硅化物掩埋的局部互连。

2. 发明授权

US08049334B1 Buried silicide local interconnect with sidewall spacers and method for making the same 有权
标题翻译：埋入硅化物与侧壁间隔物的局部互连及其制造方法
公开(公告)号：US08049334B1
公开(公告)日：2011-11-01
申请号：US12843131
申请日：2010-07-26
申请人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jusuke Ogura
发明人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jusuke Ogura
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/28518 , H01L21/743 , H01L21/76895
摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
摘要翻译：掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。凹槽里填充有抛光的填充材料。然后去除硬掩模以形成硅化物掩埋的局部互连。

3. 发明授权

US06617215B1 Memory wordline hard mask 有权
标题翻译：内存字线硬掩模
公开(公告)号：US06617215B1
公开(公告)日：2003-09-09
申请号：US10109235
申请日：2002-03-27
申请人： Arvind Halliyal , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang , Emmanuil Lingunis , Angela T. Hui , Jusuke Ogura
发明人： Arvind Halliyal , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang , Emmanuil Lingunis , Angela T. Hui , Jusuke Ogura
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/0332 , H01L21/32139 , H01L27/115
摘要： A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric material. First and second bitlines are implanted and a wordline material is deposited. A hard mask material is deposited over the wordline material. The hard mask material is of a material having the characteristic of being deposited rather than grown. A photoresist material is deposited over the wordline material and is patterned to form a patterned hard mask. The patterned photoresist material is removed. The wordline material is processed using the patterned hard mask to form a wordline. The patterned hard mask material is removed.
摘要翻译：用于MirrorBit（R）闪存的制造方法包括提供半导体衬底和沉积电荷俘获电介质材料。植入第一和第二位线，并存放字线材料。硬掩模材料沉积在字线材料上。硬掩模材料是具有沉积而不是生长的特征的材料。光致抗蚀剂材料沉积在字线材料上并被图案化以形成图案化的硬掩模。去除图案化的光致抗蚀剂材料。使用图案化的硬掩模处理字线材料以形成字线。去除图案化的硬掩模材料。

4. 发明授权

US06667243B1 Etch damage repair with thermal annealing 有权
标题翻译：蚀刻损伤修复与热退火
公开(公告)号：US06667243B1
公开(公告)日：2003-12-23
申请号：US10222248
申请日：2002-08-16
申请人： Mark T. Ramsbey , Nicholas H. Tripsas , Arvind Halliyal , Jeffrey A. Shields , Yider Wu
发明人： Mark T. Ramsbey , Nicholas H. Tripsas , Arvind Halliyal , Jeffrey A. Shields , Yider Wu
IPC分类号： H01L21302
CPC分类号： H01L21/02071 , H01L21/31138 , H01L21/32137 , H01L21/32139 , H01L29/6659 , Y10S438/906 , Y10S438/94
摘要： A method of manufacturing a semiconductor device etches a feature on a substrate in accordance with a photoresist mask. The photoresist mask is removed by plasma etching. Laser thermal annealing is performed to vaporize polymer residue created during the stripping of the photoresist mask, and to repair damage to the substrate.
摘要翻译：半导体器件的制造方法根据光致抗蚀剂掩模蚀刻衬底上的特征。通过等离子体蚀刻去除光致抗蚀剂掩模。进行激光热退火以蒸发在光刻胶掩模剥离期间产生的聚合物残余物，并修复对基材的损伤。

5. 发明授权

US06774432B1 UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL 有权
标题翻译：紫外线阻挡层，用于降低BEOL中SONOS双位闪存器件的UV感应充电
公开(公告)号：US06774432B1
公开(公告)日：2004-08-10
申请号：US10358589
申请日：2003-02-05
申请人： Minh V. Ngo , Tazrien Kamal , Mark T. Ramsbey , Arvind Halliyal , Jaeyong Park , Ning Cheng , Jeff P. Erhardt , Clarence B. Ferguson , Jeffrey A. Shields , Angela T. Hui , Robert A. Huertas , Tyagamohan Gottipati
发明人： Minh V. Ngo , Tazrien Kamal , Mark T. Ramsbey , Arvind Halliyal , Jaeyong Park , Ning Cheng , Jeff P. Erhardt , Clarence B. Ferguson , Jeffrey A. Shields , Angela T. Hui , Robert A. Huertas , Tyagamohan Gottipati
IPC分类号： H01L29792
CPC分类号： H01L29/66833 , H01L21/28282 , H01L23/552 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. A SONOS flash memory device, including a SONOS flash memory cell; and at least one UV-protective layer, in which the UV-protective layer comprises a substantially UV-opaque material, is provided. In one embodiment, the device includes a substantially UV-opaque contact cap layer.
摘要翻译：一种保护SONOS闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造SONOS闪存单元; 并且在所述SONOS闪存单元上沉积至少一个UV保护层，所述UV保护层包括基本上不透紫外线的材料。 SONOS闪存设备，包括SONOS闪存单元; 以及至少一个UV保护层，其中UV保护层包括基本上不透紫外线的材料。在一个实施例中，该装置包括基本上不透紫外线的接触盖层。

6. 发明授权

US07018896B2 UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing 有权
标题翻译：紫外线阻挡层，用于在BEOL处理中减少SONOS双位闪存器件的紫外线充电
公开(公告)号：US07018896B2
公开(公告)日：2006-03-28
申请号：US10818112
申请日：2004-04-05
申请人： Minh V. Ngo , Tazrien Kamal , Mark T. Ramsbey , Arvind Halliyal , Jaeyong Park , Ning Cheng , Jeff P. Erhardt , Clarence B. Ferguson , Jeffrey A. Shields , Angela T. Hui , Robert A. Huertas , Tyagamohan Gottipati
发明人： Minh V. Ngo , Tazrien Kamal , Mark T. Ramsbey , Arvind Halliyal , Jaeyong Park , Ning Cheng , Jeff P. Erhardt , Clarence B. Ferguson , Jeffrey A. Shields , Angela T. Hui , Robert A. Huertas , Tyagamohan Gottipati
IPC分类号： H01L21/00
CPC分类号： H01L29/66833 , H01L21/28282 , H01L23/552 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. In one embodiment, the device includes a substantially UV-opaque sub-layer of a contact cap layer or a substantially UV-opaque contact cap layer.
摘要翻译：一种保护SONOS闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造SONOS闪存单元; 并且在所述SONOS闪存单元上沉积至少一个UV保护层，所述UV保护层包括基本上不透紫外线的材料。在一个实施例中，该装置包括接触帽层或基本上不透紫外线的接触覆盖层的基本不透紫外不透明的子层。

7. 发明授权

US07091088B1 UV-blocking etch stop layer for reducing UV-induced charging of charge storage layer in memory devices in BEOL processing 有权
标题翻译：用于减少BEOL处理中的存储器件中的电荷存储层的UV诱导的充电的UV阻挡蚀刻停止层
公开(公告)号：US07091088B1
公开(公告)日：2006-08-15
申请号：US10861437
申请日：2004-06-03
申请人： Ning Cheng , Clarence B. Ferguson , Emmanuil H. Lingunis , Minh Van Ngo , Joerg Reiss , Jean Y. Yang , Jeffrey A. Shields , Cyrus Tabery
发明人： Ning Cheng , Clarence B. Ferguson , Emmanuil H. Lingunis , Minh Van Ngo , Joerg Reiss , Jean Y. Yang , Jeffrey A. Shields , Cyrus Tabery
IPC分类号： H01L21/336
CPC分类号： H01L23/53295 , H01L21/76829 , H01L27/115 , H01L27/11568 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing over the charge trapping dielectric flash memory cell at least one UV-protective layer; forming at least one layer over the at least one UV-protective layer; and etching the at least one layer to form an opening therein with an etchant species selective to stop on a layer below the at least one UV-protective layer, wherein the UV-protective layer comprises a substantially UV-opaque material.
摘要翻译：一种保护电荷捕获电介质闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造电荷俘获电介质闪存单元; 在电荷捕获电介质闪存单元上沉积至少一个UV保护层; 在所述至少一个UV保护层上形成至少一层; 以及蚀刻所述至少一个层以在其中形成具有选择性地停留在所述至少一个UV保护层下方的层上的蚀刻剂物质的开口，其中所述UV保护层包括基本上不透紫外线的材料。

8. 发明授权

US08022468B1 Ultraviolet radiation blocking interlayer dielectric 有权
标题翻译：紫外辐射阻挡层间电介质
公开(公告)号：US08022468B1
公开(公告)日：2011-09-20
申请号：US11091519
申请日：2005-03-29
申请人： Minh Van Ngo , Wenmei Li , Jeffrey A. Shields , Ning Cheng , Angela Hui , Cinti Xiaohua Chen
发明人： Minh Van Ngo , Wenmei Li , Jeffrey A. Shields , Ning Cheng , Angela Hui , Cinti Xiaohua Chen
IPC分类号： H01L29/66
CPC分类号： H01L27/11521 , H01L23/552 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer. The memory device may further include an interlayer dielectric formed over the control gate and the substrate, where the interlayer dielectric includes a material that is substantially opaque to ultraviolet radiation.
摘要翻译：存储器件可以包括衬底，形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。存储器件还可以包括形成在电荷存储元件上的第二介电层和形成在第二介电层上的控制栅极。存储器件还可以包括在控制栅极和衬底上形成的层间电介质，其中层间电介质包括对紫外线辐射基本不透明的材料。

9. 发明授权

US07232765B1 Utilization of a Ta-containing cap over copper to facilitate concurrent formation of copper vias and memory element structures 有权
标题翻译：在铜上利用含Ta的盖以促进铜通孔和记忆元件结构的同时形成
公开(公告)号：US07232765B1
公开(公告)日：2007-06-19
申请号：US10988239
申请日：2004-11-12
申请人： Steven C. Avanzino , Nicholas H. Tripsas , Jeffrey A. Shields , Fei Wang , Richard P. Kingsborough , William Leonard , Suzette K. Pangrle
发明人： Steven C. Avanzino , Nicholas H. Tripsas , Jeffrey A. Shields , Fei Wang , Richard P. Kingsborough , William Leonard , Suzette K. Pangrle
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76849 , H01L21/7685 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L51/0021
摘要： Disclosed are methods for facilitating concurrent formation of copper vias and memory element structures. The methods involve forming vias over metal lines and forming copper plugs, wherein the copper plugs comprise memory element film forming copper plugs (memE copper plugs) and non-memory element forming copper plugs (non-memE copper plugs), forming a tantalum-containing cap over an upper surface of non-memE copper plugs, and depositing memory element films. The tantalum-containing cap prevents the formation of the memory element films in the non-memE copper plugs. The subject invention advantageously facilitates cost-effective manufacturing of semiconductor devices.
摘要翻译：公开了促进铜通孔和记忆元件结构的同时形成的方法。所述方法包括在金属线上形成通孔并形成铜塞，其中铜塞包括记忆元件膜形成铜塞（memE铜塞）和形成铜塞（非memE铜塞）的非存储元件，形成含钽覆盖非memE铜插头的上表面，并沉积存储元件膜。含钽盖防止在非memE铜插头中形成记忆元件膜。本发明有利地有助于半导体器件的成本有效的制造。

10. 发明授权

US06620717B1 Memory with disposable ARC for wordline formation 失效
标题翻译：具有一次性ARC用于字线形成的记忆
公开(公告)号：US06620717B1
公开(公告)日：2003-09-16
申请号：US10100487
申请日：2002-03-14
申请人： Tazrien Kamal , Scott A. Bell , Kouros Ghandehari , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang
发明人： Tazrien Kamal , Scott A. Bell , Kouros Ghandehari , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang
IPC分类号： H01L213205
CPC分类号： H01L27/11568 , H01L21/32139 , H01L27/115
摘要： A method of manufacturing for a Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines. A wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited. A disposable anti-reflective coating (ARC) material and a photoresist material are deposited followed by processing to form a patterned photoresist material and a patterned ARC material. The hard mask material is processed to form a patterned hard mask material. The patterned photoresist is removed and then the patterned ARC without damaging the patterned hard mask material or the wordline material. The wordline material is processed using the patterned hard mask material to form a wordline and the patterned hard mask material is removed without damaging the wordline or the charge-trapping dielectric material.
摘要翻译：一种用于闪速存储器的制造方法包括在半导体衬底上沉积电荷捕获材料并植入第一和第二位线。字线材料沉积在电荷捕获电介质材料上并沉积硬掩模材料。沉积一次性抗反射涂层（ARC）材料和光致抗蚀剂材料，然后进行处理以形成图案化的光致抗蚀剂材料和图案化的ARC材料。加工硬掩模材料以形成图案化的硬掩模材料。去除图案化的光致抗蚀剂，然后去除图案化的ARC，而不损坏图案化的硬掩模材料或字线材料。使用图案化的硬掩模材料处理字线材料以形成字线，并且去除图案化的硬掩模材料而不损坏字线或电荷捕获电介质材料。

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