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1. 发明授权

US07205217B2 Method for forming trench gate dielectric layer 有权
标题翻译：形成沟槽栅极电介质层的方法
公开(公告)号：US07205217B2
公开(公告)日：2007-04-17
申请号：US11161177
申请日：2005-07-26
申请人： Min-San Huang , Hann-Jye Hsu , Liang-Chuan Lai
发明人： Min-San Huang , Hann-Jye Hsu , Liang-Chuan Lai
IPC分类号： H01L21/28 , H01L21/285
CPC分类号： H01L29/4236 , H01L21/28194 , H01L21/28238 , H01L29/66734
摘要： A method for forming a trench gate dielectric layer is described. First, a substrate having a trench therein is provided. An in-situ steam generated oxidation process is performed to form a sacrificial layer on the surface of the trench. Then, the sacrificial layer is removed. Next, a low-pressure chemical vapor deposition is performed to form a gate dielectric layer on the surface of the trench.
摘要翻译：描述了形成沟槽栅介质层的方法。首先，提供其中具有沟槽的衬底。执行原位蒸汽生成的氧化工艺以在沟槽的表面上形成牺牲层。然后，除去牺牲层。接下来，进行低压化学气相沉积以在沟槽的表面上形成栅极电介质层。

2. 发明申请

US20060160306A1 METHOD FOR FORMING TRENCH GATE DIELECTRIC LAYER 有权
标题翻译：形成铁基电介质层的方法
公开(公告)号：US20060160306A1
公开(公告)日：2006-07-20
申请号：US11161177
申请日：2005-07-26
申请人： Min-San Huang , Hann-Jye Hsu , Liang-Chuan Lai
发明人： Min-San Huang , Hann-Jye Hsu , Liang-Chuan Lai
IPC分类号： H01L21/336
CPC分类号： H01L29/4236 , H01L21/28194 , H01L21/28238 , H01L29/66734
摘要： A method for forming a trench gate dielectric layer is described. First, a substrate having a trench therein is provided. An in-situ steam generated oxidation process is performed to form a sacrificial layer on the surface of the trench. Then, the sacrificial layer is removed. Next, a low-pressure chemical vapor deposition is performed to form a gate dielectric layer on the surface of the trench.
摘要翻译：描述了形成沟槽栅介质层的方法。首先，提供其中具有沟槽的衬底。执行原位蒸汽生成的氧化工艺以在沟槽的表面上形成牺牲层。然后，除去牺牲层。接下来，进行低压化学气相沉积以在沟槽的表面上形成栅极电介质层。

3. 发明授权

US07612433B2 Semiconductor device having self-aligned contact 有权
标题翻译：具有自对准接触的半导体器件
公开(公告)号：US07612433B2
公开(公告)日：2009-11-03
申请号：US11162725
申请日：2005-09-21
申请人： Min-San Huang , Hann-Jye Hsu , Yung-Chung Yao
发明人： Min-San Huang , Hann-Jye Hsu , Yung-Chung Yao
IPC分类号： H01L29/06 , H01L23/58
CPC分类号： H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.
摘要翻译：提供一种制造具有自对准触点的半导体器件的方法。在衬底上形成多个隔离结构以限定有源区。在基板上形成多个栅极结构。在每个栅极结构旁边的衬底中形成多个掺杂区域。在每个栅极结构的侧壁上形成多个第一间隔物。多个第二间隔件形成在每个隔离结构的侧壁上。在基板上形成电介质层。然后，进行自对准工艺以在栅极结构之间的介电层中形成多个接触开口。导电材料填充在接触开口中。

4. 发明授权

US07550372B2 Method of fabricating conductive lines with silicide layer 有权
标题翻译：用硅化物层制作导线的方法
公开(公告)号：US07550372B2
公开(公告)日：2009-06-23
申请号：US11162115
申请日：2005-08-29
申请人： Su-Yuan Chang , Min-San Huang , Hann-Jye Hsu
发明人： Su-Yuan Chang , Min-San Huang , Hann-Jye Hsu
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/461
CPC分类号： H01L21/76838 , H01L21/76889
摘要： A method of fabricating conductive lines is described. A substrate having a polysilicon layer thereon is provided. A mask layer having an opening that exposes the polysilicon layer is formed on the polysilicon layer. Then, spacers are formed on the sidewalls of the mask layer. Using the mask layer and the spacers as a mask, a portion of the polysilicon layer is removed until the substrate is exposed. After that, an insulating layer that completely fills the opening is formed over the substrate. The insulating layer has an etching selectivity different from the mask layer. Thereafter, the mask layer is removed to expose the polysilicon layer and then a metal silicide layer is formed on the upper surface of the polysilicon layer.
摘要翻译：描述制造导线的方法。提供其上具有多晶硅层的基板。在多晶硅层上形成具有露出多晶硅层的开口的掩模层。然后，在掩模层的侧壁上形成间隔物。使用掩模层和间隔物作为掩模，去除多晶硅层的一部分直到基板被暴露。之后，在基板上形成完全填充开口的绝缘层。绝缘层具有与掩模层不同的蚀刻选择性。此后，除去掩模层以露出多晶硅层，然后在多晶硅层的上表面上形成金属硅化物层。

5. 发明申请

US20060183295A1 SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED CONTACT AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有自对准接触件的半导体器件及其制造方法
公开(公告)号：US20060183295A1
公开(公告)日：2006-08-17
申请号：US11162725
申请日：2005-09-21
申请人： Min-San Huang , Hann-Jye Hsu , Yung-Chung Yao
发明人： Min-San Huang , Hann-Jye Hsu , Yung-Chung Yao
IPC分类号： H01L21/76
CPC分类号： H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.
摘要翻译：提供一种制造具有自对准触点的半导体器件的方法。在衬底上形成多个隔离结构以限定有源区。在基板上形成多个栅极结构。在每个栅极结构旁边的衬底中形成多个掺杂区域。在每个栅极结构的侧壁上形成多个第一间隔物。多个第二间隔件形成在每个隔离结构的侧壁上。在基板上形成电介质层。然后，进行自对准工艺以在栅极结构之间的介电层中形成多个接触开口。导电材料填充在接触开口中。

6. 发明申请

US20060166497A1 METHOD OF FABRICATING CONDUCTIVE LINES 有权
标题翻译：制导导线的方法
公开(公告)号：US20060166497A1
公开(公告)日：2006-07-27
申请号：US11162115
申请日：2005-08-29
申请人： Su-Yuan Chang , Min-San Huang , Hann-Jye Hsu
发明人： Su-Yuan Chang , Min-San Huang , Hann-Jye Hsu
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L21/76889
摘要： A method of fabricating conductive lines is described. A substrate having a polysilicon layer thereon is provided. A mask layer having an opening that exposes the polysilicon layer is formed on the polysilicon layer. Then, spacers are formed on the sidewalls of the mask layer. Using the mask layer and the spacers as a mask, a portion of the polysilicon layer is removed until the substrate is exposed. After that, an insulating layer that completely fills the opening is formed over the substrate. The insulating layer has an etching selectivity different from the mask layer. Thereafter, the mask layer is removed to expose the polysilicon layer and then a metal silicide layer is formed on the upper surface of the polysilicon layer.
摘要翻译：描述制造导线的方法。提供其上具有多晶硅层的基板。在多晶硅层上形成具有露出多晶硅层的开口的掩模层。然后，在掩模层的侧壁上形成间隔物。使用掩模层和间隔物作为掩模，去除多晶硅层的一部分直到基板被暴露。之后，在基板上形成完全填充开口的绝缘层。绝缘层具有与掩模层不同的蚀刻选择性。此后，除去掩模层以露出多晶硅层，然后在多晶硅层的上表面上形成金属硅化物层。

7. 发明授权

US07803692B2 Manufacturing method of semiconductor device having self-aligned contact 有权
标题翻译：具有自对准接触的半导体器件的制造方法
公开(公告)号：US07803692B2
公开(公告)日：2010-09-28
申请号：US12562142
申请日：2009-09-18
申请人： Min-San Huang , Hann-Jye Hsu , Yung-Chung Yao
发明人： Min-San Huang , Hann-Jye Hsu , Yung-Chung Yao
IPC分类号： H01L21/76 , H01L21/336
CPC分类号： H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.
摘要翻译：提供一种制造具有自对准触点的半导体器件的方法。在衬底上形成多个隔离结构以限定有源区。在基板上形成多个栅极结构。在每个栅极结构旁边的衬底中形成多个掺杂区域。在每个栅极结构的侧壁上形成多个第一间隔物。多个第二间隔件形成在每个隔离结构的侧壁上。在基板上形成电介质层。然后，进行自对准工艺以在栅极结构之间的介电层中形成多个接触开口。导电材料填充在接触开口中。

8. 发明申请

US20100003796A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED CONTACT 有权
标题翻译：具有自对准接触的半导体器件的制造方法
公开(公告)号：US20100003796A1
公开(公告)日：2010-01-07
申请号：US12562142
申请日：2009-09-18
申请人： Min-San Huang , Hann-Jye Hsu , Yung-Chung Yao
发明人： Min-San Huang , Hann-Jye Hsu , Yung-Chung Yao
IPC分类号： H01L21/77
CPC分类号： H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.
摘要翻译：提供一种制造具有自对准触点的半导体器件的方法。在衬底上形成多个隔离结构以限定有源区。在基板上形成多个栅极结构。在每个栅极结构旁边的衬底中形成多个掺杂区域。在每个栅极结构的侧壁上形成多个第一间隔物。多个第二间隔件形成在每个隔离结构的侧壁上。在基板上形成电介质层。然后，进行自对准工艺以在栅极结构之间的介电层中形成多个接触开口。导电材料填充在接触开口中。

9. 发明申请

US20060189074A1 STRUCTURE CONTAINING SELF-ALIGNED CONDUCTIVE LINES AND FABRICATING METHOD THEREOF 审中-公开
标题翻译：包含自对准导线的结构及其制造方法
公开(公告)号：US20060189074A1
公开(公告)日：2006-08-24
申请号：US11162077
申请日：2005-08-29
申请人： Hann-Jye Hsu , Su-Yuan Chang , Min-San Huang
发明人： Hann-Jye Hsu , Su-Yuan Chang , Min-San Huang
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L27/115 , H01L27/11556
摘要： A method for fabricating self-aligned conductive lines is provided. A substrate with a plurality of isolation structures is provided. The isolation structures are protrusive from the surface of the substrate, and an active region is defined between two adjacent isolation structures. A plurality of semiconductor devices is formed in the active region. A conductive material layer is then formed on the substrate. Thereafter, a portion of the conductive material layer is removed by using the isolation structures as a removing-stop layer until the surfaces of the isolation structures are exposed and a plurality of conductive lines are formed in a self-aligned manner to electrically connect devices. As the size of the devices is scaled down, the design rule of the lithography process does not limit the size of self-aligned conductive lines. Consequently, the fabricated conductive lines are capable of effectively connecting the semiconductor devices.
摘要翻译：提供一种制造自对准导电线的方法。提供具有多个隔离结构的基板。隔离结构从衬底的表面突出，并且在两个相邻隔离结构之间限定有源区。在有源区域中形成多个半导体器件。然后在衬底上形成导电材料层。此后，通过使用隔离结构作为去除阻挡层去除导电材料层的一部分，直到隔离结构的表面露出，并且以自对准的方式形成多个导电线以电连接器件。随着器件的尺寸缩小，光刻工艺的设计规则并不限制自对准导电线的尺寸。因此，制造的导线能够有效地连接半导体器件。

10. 发明授权

US06768162B1 Split gate flash memory cell and manufacturing method thereof 有权
公开(公告)号：US06768162B1
公开(公告)日：2004-07-27
申请号：US10604612
申请日：2003-08-05
申请人： Ko-Hsing Chang , Hann-Jye Hsu
发明人： Ko-Hsing Chang , Hann-Jye Hsu
IPC分类号： H01L29788
CPC分类号： H01L27/11553 , H01L27/11556 , H01L29/42324 , H01L29/7883
摘要： A split gate flash memory cell includes a substrate having a trench, a stack structure disposed on the substrate, wherein the stack structure includes a tunneling dielectric layer, a floating gate and a cap layer; a first inter-gate dielectric layer and a second inter-gate dielectric layer disposed on the sidewalls of the stack structure, wherein the first inter-gate dielectric layer is contiguous to the top of the trench; a selective gate disposed on the sidwalls of the first inter-gate dielectric layer and the trench; a selective gate dielectric layer disposed between the selective gate and the substrate; a source region configured in the substrate beside the side of the stack structure with the second inter-gate dielectric layer; and a drain region configured at the bottom of the trench beside one side of the selective gate.

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