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1. 发明申请

US20090004796A1 METHOD OF MANUFACTURING NON-VOLATILE MEMORY 审中-公开
标题翻译：制造非易失性存储器的方法
公开(公告)号：US20090004796A1
公开(公告)日：2009-01-01
申请号：US12211074
申请日：2008-09-15
申请人： Ko-Hsing Chang , Tsung-Cheng Huang , Yan-Hung Huang
发明人： Ko-Hsing Chang , Tsung-Cheng Huang , Yan-Hung Huang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： A method of manufacturing a non-volatile memory includes providing a substrate and forming a patterned mask layer, a tunnel dielectric layer, and a first conductive layer on the substrate. The first conductive layer on the mask layer is removed to form second conductive layers disposed on the sidewall of the mask layer and the substrate. The mask layer is then removed and a source region is formed. Subsequently, an inter-gate dielectric layer and a third conductive layer are formed on the substrate. The third conductive layer is patterned to cover the source region and a portion of the second conductive layer on both sides of the source region. A portion of the inter-gate dielectric layer and the second conductive layers are then removed. After that, a dielectric layer, a fourth conductive layer, and a drain region are formed, respectively.
摘要翻译：制造非易失性存储器的方法包括提供衬底并在衬底上形成图案化掩模层，隧道介电层和第一导电层。去除掩模层上的第一导电层以形成布置在掩模层和基板的侧壁上的第二导电层。然后去除掩模层并形成源区。随后，在衬底上形成栅极间电介质层和第三导电层。第三导电层被图案化以覆盖源极区域和源区域两侧上的第二导电层的一部分。然后去除栅极间电介质层和第二导电层的一部分。之后，分别形成电介质层，第四导电层和漏极区域。

2. 发明授权

US07164177B2 Multi-level memory cell 失效
标题翻译：多级存储单元
公开(公告)号：US07164177B2
公开(公告)日：2007-01-16
申请号：US10707677
申请日：2004-01-02
申请人： Ko-Hsing Chang , Chiu-Tsung Huang
发明人： Ko-Hsing Chang , Chiu-Tsung Huang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/7923
摘要： A multi-level memory cell including a substrate, a tunneling dielectric layer, a charge-trapping layer, a top dielectric layer, a gate and a pair of source/drain regions is provided. The tunneling dielectric layer, the charge-trapping layer and the top dielectric layer are sequentially formed between the substrate and the gate. The top dielectric layer has at least two portions, and the top dielectric layer in each portion has a different thickness. The source/drain regions are disposed in the substrate on each side of the gate. Since the thickness of the top dielectric layer in each portion is different, the electric field strength between the gate and the substrate when a voltage is applied to the memory cell are different in each portion. With the number of charges trapped within the charge-trapping layer different in each portion, a multiple of data bits can be stored within each memory cell.
摘要翻译：提供了包括衬底，隧道电介质层，电荷俘获层，顶部电介质层，栅极和一对源极/漏极区域的多层存储单元。隧道介电层，电荷俘获层和顶部电介质层依次形成在基板和栅极之间。顶部电介质层具有至少两个部分，并且每个部分中的顶部电介质层具有不同的厚度。源极/漏极区域设置在栅极的每一侧的衬底中。由于各部分的顶部电介质层的厚度不同，所以当向存储单元施加电压时，栅极与衬底之间的电场强度各不相同。由于每个部分中的电荷俘获层内陷入的电荷数量不同，所以可以在每个存储单元内存储多个数据位。

3. 发明申请

US20060208298A1 MEMORY CELL OF DYNAMIC RANDOM ACCESS MEMORY AND ARRAY STRUCTURE THEREOF 审中-公开
标题翻译：动态随机存取存储器的存储单元及其阵列结构
公开(公告)号：US20060208298A1
公开(公告)日：2006-09-21
申请号：US11163222
申请日：2005-10-11
申请人： Ko-Hsing Chang , Chia-Chiang Wang
发明人： Ko-Hsing Chang , Chia-Chiang Wang
IPC分类号： H01L29/94
CPC分类号： H01L27/108 , H01L29/945
摘要： A DRAM cell including a trench capacitor structure, a transistor and a stacked capacitor structure is provided. A first electrode of the trench capacitor structure is disposed in the substrate at the bottom of a trench. A second electrode of the trench capacitor structure is disposed in the trench. The transistor includes a gate, first and second source/drain regions. The gate is disposed on the substrate beside the trench capacitor structure. The first and the second source/drain regions are disposed in the substrate on respective sides of the gate. A third electrode of the stacked capacitor structure is disposed on the substrate between the gate of the transistor and the trench capacitor structure. A fourth electrode of the stacked capacitor structure is disposed on the third electrode above the substrate. The first electrode connects electrically with the fourth electrode, and the second electrode connects electrically with the third electrode.
摘要翻译：提供了包括沟槽电容器结构，晶体管和堆叠电容器结构的DRAM单元。沟槽电容器结构的第一电极设置在沟槽底部的衬底中。沟槽电容器结构的第二电极设置在沟槽中。晶体管包括栅极，第一和第二源极/漏极区域。栅极设置在沟槽电容器结构旁边的衬底上。第一和第二源极/漏极区域设置在栅极的相应侧面上的衬底中。层叠电容器结构的第三电极设置在晶体管的栅极和沟槽电容器结构之间的衬底上。层叠电容器结构的第四电极设置在基板上方的第三电极上。第一电极与第四电极电连接，第二电极与第三电极电连接。

4. 发明授权

US07091550B2 Non-volatile memory device and method of manufacturing the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07091550B2
公开(公告)日：2006-08-15
申请号：US10707704
申请日：2004-01-06
申请人： Hann-Jye Hsu , Ko-Hsing Chang
发明人： Hann-Jye Hsu , Ko-Hsing Chang
IPC分类号： H01L21/336
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/28202 , H01L29/517 , H01L29/518 , H01L29/78 , H01L29/792
摘要： A non-volatile memory device and method of manufacturing the same is provided. A substrate is provided and then a trench is formed in the substrate. Thereafter, a bottom oxide layer, a charge-trapping layer and a top oxide layer are sequentially formed over the substrate and the surface of the trench. A conductive layer is formed over the top oxide layer filling the trench. The conductive layer is patterned to form a gate over the trench. The top oxide layer, the charge-trapping layer and the bottom oxide layer outside the gate are removed. A source/drain doping process is carried out. Because the non-volatile memory device is manufactured within the trench, storage efficiency of the device is improved through an increase in the coupling ratio. Furthermore, more charges can be stored by increasing the depth of the trench.
摘要翻译：提供了一种非易失性存储器件及其制造方法。提供衬底，然后在衬底中形成沟槽。此后，在衬底和沟槽的表面上顺序地形成底部氧化物层，电荷捕获层和顶部氧化物层。在填充沟槽的顶部氧化物层上形成导电层。将导电层图案化以在沟槽上形成栅极。除去顶部氧化物层，电荷捕获层和栅极外部的底部氧化物层。进行源极/漏极掺杂工艺。由于在沟槽内制造了非易失性存储器件，所以通过增加耦合比来提高器件的存储效率。此外，通过增加沟槽的深度可以存储更多的电荷。

5. 发明申请

US20060154418A1 METHOD FOR MANUFACTURING ONE-TIME ELECTRICALLY PROGRAMMABLE READ ONLY MEMORY 失效
标题翻译：制造一次性可编程只读存储器的方法
公开(公告)号：US20060154418A1
公开(公告)日：2006-07-13
申请号：US11160176
申请日：2005-06-13
申请人： Ko-Hsing Chang , Tung-Po Chen , Tung-Ming Lai , Chen-Chiu Hsue
发明人： Ko-Hsing Chang , Tung-Po Chen , Tung-Ming Lai , Chen-Chiu Hsue
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/7833
摘要： A method for manufacturing an OTEPROM is described. A tunneling oxide layer, a first conductive layer, a first patterned mask layer are formed on a substrate. A trench is formed in the substrate. An insulating layer is formed to fill the trench. A portion of the first conductive layer destined to form the floating gate is exposed and then a cap layer is formed thereon. The first patterned mask layer is removed and then a second conductive layer and a second patterned mask layer are formed over the substrate. A word line and a floating gate are formed using the second patterned mask layer and the cap layer as a mask. The second patterned mask layer is removed and then source/drain regions are formed in the substrate on both sides of the word line and the floating gate and between the word line and the floating gate.
摘要翻译：描述了用于制造OTEPROM的方法。在衬底上形成隧道氧化物层，第一导电层，第一图案化掩模层。在衬底中形成沟槽。形成绝缘层以填充沟槽。目的地形成浮栅的第一导电层的一部分被暴露，然后在其上形成覆盖层。去除第一图案化掩模层，然后在衬底上形成第二导电层和第二图案化掩模层。使用第二图案化掩模层和盖层作为掩模形成字线和浮栅。去除第二图案化掩模层，然后在字线和浮栅两侧以及字线和浮栅之间的衬底中形成源极/漏极区。

6. 发明申请

US20060102948A1 METHOD OF FABRICATING FLASH MEMORY 审中-公开
标题翻译：制作闪速存储器的方法
公开(公告)号：US20060102948A1
公开(公告)日：2006-05-18
申请号：US11160326
申请日：2005-06-20
申请人： Ko-Hsing Chang , Su-Yuan Chang
发明人： Ko-Hsing Chang , Su-Yuan Chang
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method of fabricating a flash memory is provided. The method includes forming a mask layer with first openings on the substrate. A tunneling dielectric layer is formed at bottom in the first openings. Strips of conductive spacers are formed on sidewalls of the first openings, and source/drain regions are formed in the substrate within the first openings. The strips of conductive spacers are patterned to form floating gates. A first inter-gate dielectric layer is formed over the substrate. Control gates are formed on the substrate to fill the first openings. Mask layer is removed to form second openings. Gate dielectric layer is formed at bottom of second openings, and second inter-gate dielectric layer is formed on the sidewalls of floating gates, and the sidewalls and top surface of the control gates. Word lines are formed to fill second openings disposed between the floating gates and cover the control gates.
摘要翻译：提供一种制造闪速存储器的方法。该方法包括在基板上形成具有第一开口的掩模层。隧道电介质层形成在第一开口的底部。导电间隔物条形成在第一开口的侧壁上，并且源/漏区形成在第一开口内的基板中。将导电间隔物的条带图案化以形成浮栅。在衬底上形成第一栅极间电介质层。在基板上形成控制栅极以填充第一开口。去除掩模层以形成第二开口。栅介电层形成在第二开口的底部，第二栅极间电介质层形成在浮动栅极的侧壁以及控制栅极的侧壁和顶表面上。字线被形成以填充设置在浮动栅极之间并覆盖控制栅极的第二开口。

7. 发明授权

US07038267B2 Non-volatile memory cell and manufacturing method thereof 失效
标题翻译：非易失性存储单元及其制造方法
公开(公告)号：US07038267B2
公开(公告)日：2006-05-02
申请号：US10709372
申请日：2004-04-30
申请人： Ko-Hsing Chang , Chiu-Tsung Huang
发明人： Ko-Hsing Chang , Chiu-Tsung Huang
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7926
摘要： A non-volatile memory cell is provided. The non-volatile memory at least includes a substrate, a gate, a first source/drain region, a composite dielectric layer and a second source/drain region. A trench is formed in a substrate and a gate is formed inside the trench. The first source/drain region is formed at the bottom of the trench. The composite dielectric layer is formed between the gate and the surface of the trench. The composite dielectric layer includes at least a charge-trapping layer. The second source/drain region is formed in the substrate next to the sides of the gate.
摘要翻译：提供非易失性存储单元。非易失性存储器至少包括衬底，栅极，第一源极/漏极区域，复合电介质层和第二源极/漏极区域。在衬底中形成沟槽，并且在沟槽内形成栅极。第一源极/漏极区域形成在沟槽的底部。复合电介质层形成在沟槽的栅极和表面之间。复合介电层至少包括电荷捕获层。第二源极/漏极区域形成在栅极侧面旁边的衬底中。

8. 发明授权

US06943404B2 Sonos multi-level memory cell 有权
标题翻译： Sonos多层记忆体
公开(公告)号：US06943404B2
公开(公告)日：2005-09-13
申请号：US10604613
申请日：2003-08-05
申请人： Chiu-Tsung Huang , Ko-Hsing Chang
发明人： Chiu-Tsung Huang , Ko-Hsing Chang
IPC分类号： H01L21/28 , H01L21/336 , H01L29/792
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/7923
摘要： A multi-level memory cell includes a substrate, an insulation layer, a silicon stripe, a first control gate, a second control gate, source/drain regions, silicon oxide/silicon nitride/silicon oxide composite layers. The insulation layer and the silicon stripe are sequentially disposed on the substrate. The first control gate and the second control gate are respectively disposed on the sidewalls of the silicon stripe, while the source/drain regions are configured in the silicon stripe beside both sides of the first control gate and the second control gate. The composite dielectric layers are disposed between the first control gate and the silicon stripe, and between the second control gate and the silicon stripe. Since a single memory structure can store a multiple bit of information, it is advantageous for minimizing devices.
摘要翻译：多层存储单元包括衬底，绝缘层，硅条，第一控制栅极，第二控制栅极，源极/漏极区域，氧化硅/氮化硅/氧化硅复合层。绝缘层和硅条依次设置在基板上。第一控制栅极和第二控制栅极分别设置在硅条的侧壁上，而源极/漏极区域配置在除了第一控制栅极和第二控制栅极两侧的硅条纹之外。复合电介质层设置在第一控制栅极和硅条之间以及第二控制栅极和硅条之间。由于单个存储器结构可以存储多个位的信息，所以最小化器件是有利的。

9. 发明申请

US20050145920A1 Non-volatile memory and fabricating method thereof 审中-公开
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20050145920A1
公开(公告)日：2005-07-07
申请号：US10707650
申请日：2003-12-30
申请人： Ko-Hsing Chang , Chiu-Tsung Huang
发明人： Ko-Hsing Chang , Chiu-Tsung Huang
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42336 , H01L29/7883
摘要： A non-volatile memory structure and a fabricating method thereof are described. In the fabricating method, a mask layer is formed over a substrate first. A trench is formed in the mask layer and the substrate, and then a tunnel dielectric layer is formed in the trench. A floating gate is formed inside the trench, and then the mask layer is removed. A high-voltage doped region is formed in the substrate on one side of the floating gate, serving as a first source/drain region and a control gate simultaneously. A second source/drain region is then formed in the substrate on the other side of the floating gate.
摘要翻译：描述了非易失性存储器结构及其制造方法。在制造方法中，首先在衬底上形成掩模层。在掩模层和衬底中形成沟槽，然后在沟槽中形成隧道电介质层。在沟槽内形成浮栅，然后去除掩模层。高电压掺杂区域形成在浮置栅极一侧的衬底中，同时用作第一源极/漏极区域和控制栅极。然后在浮动栅极的另一侧上的衬底中形成第二源极/漏极区域。

10. 发明申请

US20050082600A1 [NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME] 失效
标题翻译： [非易失性存储器件及其制造方法]
公开(公告)号：US20050082600A1
公开(公告)日：2005-04-21
申请号：US10707704
申请日：2004-01-06
申请人： HANN-JYE HSU , KO-HSING CHANG
发明人： HANN-JYE HSU , KO-HSING CHANG
IPC分类号： H01L21/28 , H01L29/423 , H01L29/51 , H01L29/792 , H01L21/336 , H01L29/788
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/28202 , H01L29/517 , H01L29/518 , H01L29/78 , H01L29/792
摘要： A non-volatile memory device and method of manufacturing the same is provided. A substrate is provided and then a trench is formed in the substrate. Thereafter, a bottom oxide layer, a charge-trapping layer and a top oxide layer are sequentially formed over the substrate and the surface of the trench. A conductive layer is formed over the top oxide layer filling the trench. The conductive layer is patterned to form a gate over the trench. The top oxide layer, the charge-trapping layer and the bottom oxide layer outside the gate are removed. A source/drain doping process is carried out. Because the non-volatile memory device is manufactured within the trench, storage efficiency of the device is improved through an increase in the coupling ratio. Furthermore, more charges can be stored by increasing the depth of the trench.
摘要翻译：提供了一种非易失性存储器件及其制造方法。提供衬底，然后在衬底中形成沟槽。此后，在衬底和沟槽的表面上顺序地形成底部氧化物层，电荷捕获层和顶部氧化物层。在填充沟槽的顶部氧化物层上形成导电层。将导电层图案化以在沟槽上形成栅极。除去顶部氧化物层，电荷捕获层和栅极外部的底部氧化物层。进行源极/漏极掺杂工艺。由于在沟槽内制造了非易失性存储器件，所以通过增加耦合比来提高器件的存储效率。此外，通过增加沟槽的深度可以存储更多的电荷。

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